1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "i830_context.h"
32 #include "intel_batchbuffer.h"
34 #include "tnl/t_context.h"
35 #include "tnl/t_vertex.h"
37 static GLboolean
i830_check_vertex_size( intelContextPtr intel
,
40 #define SZ_TO_HW(sz) ((sz-2)&0x3)
41 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
42 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
44 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
45 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
46 intel->vertex_attr_count++; \
50 #define EMIT_PAD( N ) \
52 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
53 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
54 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
55 intel->vertex_attr_count++; \
59 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
60 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
62 static void i830_render_start( intelContextPtr intel
)
64 GLcontext
*ctx
= &intel
->ctx
;
65 i830ContextPtr i830
= I830_CONTEXT(intel
);
66 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
67 struct vertex_buffer
*VB
= &tnl
->vb
;
68 GLuint index
= tnl
->render_inputs
;
69 GLuint v0
= _3DSTATE_VFT0_CMD
;
70 GLuint v2
= _3DSTATE_VFT1_CMD
;
75 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
76 intel
->vertex_attr_count
= 0;
78 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
79 * build up a hardware vertex.
81 if (index
& _TNL_BITS_TEX_ANY
) {
82 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_4F_VIEWPORT
, VFT0_XYZW
);
83 intel
->coloroffset
= 4;
86 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_3F_VIEWPORT
, VFT0_XYZ
);
87 intel
->coloroffset
= 3;
90 if (index
& _TNL_BIT_POINTSIZE
) {
91 EMIT_ATTR( _TNL_ATTRIB_POINTSIZE
, EMIT_1F
, VFT0_POINT_WIDTH
);
94 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_BGRA
, VFT0_DIFFUSE
);
96 intel
->specoffset
= 0;
97 if (index
& (_TNL_BIT_COLOR1
|_TNL_BIT_FOG
)) {
98 if (index
& _TNL_BIT_COLOR1
) {
99 intel
->specoffset
= intel
->coloroffset
+ 1;
100 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
, VFT0_SPEC
);
105 if (index
& _TNL_BIT_FOG
)
106 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
, VFT0_SPEC
);
111 if (index
& _TNL_BITS_TEX_ANY
) {
114 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
115 if (index
& _TNL_BIT_TEX(i
)) {
116 GLuint sz
= VB
->TexCoordPtr
[i
]->size
;
118 GLuint mcs
= (i830
->state
.Tex
[i
][I830_TEXREG_MCS
] &
126 mcs
|= TEXCOORDTYPE_CARTESIAN
;
131 mcs
|= TEXCOORDTYPE_VECTOR
;
136 mcs
|= TEXCOORDTYPE_HOMOGENEOUS
;
143 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, emit
, 0 );
144 v2
|= VRTX_TEX_SET_FMT(count
, SZ_TO_HW(sz
));
145 mcsb1
|= (count
+8)<<(i
*4);
147 if (mcs
!= i830
->state
.Tex
[i
][I830_TEXREG_MCS
]) {
148 I830_STATECHANGE(i830
, I830_UPLOAD_TEX(i
));
149 i830
->state
.Tex
[i
][I830_TEXREG_MCS
] = mcs
;
156 v0
|= VFT0_TEX_COUNT(count
);
159 /* Only need to change the vertex emit code if there has been a
160 * statechange to a new hardware vertex format:
162 if (v0
!= i830
->state
.Ctx
[I830_CTXREG_VF
] ||
163 v2
!= i830
->state
.Ctx
[I830_CTXREG_VF2
] ||
164 mcsb1
!= i830
->state
.Ctx
[I830_CTXREG_MCSB1
] ||
165 index
!= i830
->last_index
) {
167 I830_STATECHANGE( i830
, I830_UPLOAD_CTX
);
169 /* Must do this *after* statechange, so as not to affect
170 * buffered vertices reliant on the old state:
173 _tnl_install_attrs( ctx
,
175 intel
->vertex_attr_count
,
176 intel
->ViewportMatrix
.m
, 0 );
178 intel
->vertex_size
>>= 2;
180 i830
->state
.Ctx
[I830_CTXREG_VF
] = v0
;
181 i830
->state
.Ctx
[I830_CTXREG_VF2
] = v2
;
182 i830
->state
.Ctx
[I830_CTXREG_MCSB1
] = mcsb1
;
183 i830
->last_index
= index
;
185 assert(i830_check_vertex_size( intel
, intel
->vertex_size
));
189 static void i830_reduced_primitive_state( intelContextPtr intel
,
192 i830ContextPtr i830
= I830_CONTEXT(intel
);
193 GLuint st1
= i830
->state
.Stipple
[I830_STPREG_ST1
];
199 if (intel
->ctx
.Polygon
.StippleFlag
&&
209 i830
->intel
.reduced_primitive
= rprim
;
211 if (st1
!= i830
->state
.Stipple
[I830_STPREG_ST1
]) {
212 I830_STATECHANGE(i830
, I830_UPLOAD_STIPPLE
);
213 i830
->state
.Stipple
[I830_STPREG_ST1
] = st1
;
217 /* Pull apart the vertex format registers and figure out how large a
218 * vertex is supposed to be.
220 static GLboolean
i830_check_vertex_size( intelContextPtr intel
,
223 i830ContextPtr i830
= I830_CONTEXT(intel
);
224 int vft0
= i830
->current
->Ctx
[I830_CTXREG_VF
];
225 int vft1
= i830
->current
->Ctx
[I830_CTXREG_VF2
];
226 int nrtex
= (vft0
& VFT0_TEX_COUNT_MASK
) >> VFT0_TEX_COUNT_SHIFT
;
229 switch (vft0
& VFT0_XYZW_MASK
) {
230 case VFT0_XY
: sz
= 2; break;
231 case VFT0_XYZ
: sz
= 3; break;
232 case VFT0_XYW
: sz
= 3; break;
233 case VFT0_XYZW
: sz
= 4; break;
235 fprintf(stderr
, "no xyzw specified\n");
239 if (vft0
& VFT0_SPEC
) sz
++;
240 if (vft0
& VFT0_DIFFUSE
) sz
++;
241 if (vft0
& VFT0_DEPTH_OFFSET
) sz
++;
242 if (vft0
& VFT0_POINT_WIDTH
) sz
++;
244 for (i
= 0 ; i
< nrtex
; i
++) {
245 switch (vft1
& VFT1_TEX0_MASK
) {
246 case TEXCOORDFMT_2D
: sz
+= 2; break;
247 case TEXCOORDFMT_3D
: sz
+= 3; break;
248 case TEXCOORDFMT_4D
: sz
+= 4; break;
249 case TEXCOORDFMT_1D
: sz
+= 1; break;
251 vft1
>>= VFT1_TEX1_SHIFT
;
255 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
257 return sz
== expected
;
260 static void i830_emit_invarient_state( intelContextPtr intel
)
266 OUT_BATCH(_3DSTATE_MAP_CUBE
| MAP_UNIT(0));
267 OUT_BATCH(_3DSTATE_MAP_CUBE
| MAP_UNIT(1));
268 OUT_BATCH(_3DSTATE_MAP_CUBE
| MAP_UNIT(2));
269 OUT_BATCH(_3DSTATE_MAP_CUBE
| MAP_UNIT(3));
271 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
274 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
277 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
280 OUT_BATCH(_3DSTATE_FOG_MODE_CMD
);
281 OUT_BATCH(FOGFUNC_ENABLE
|
289 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
291 DISABLE_TEX_STREAM_BUMP
|
292 ENABLE_TEX_STREAM_COORD_SET
|
293 TEX_STREAM_COORD_SET(0) |
294 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(0));
295 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
297 DISABLE_TEX_STREAM_BUMP
|
298 ENABLE_TEX_STREAM_COORD_SET
|
299 TEX_STREAM_COORD_SET(1) |
300 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(1));
301 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
303 DISABLE_TEX_STREAM_BUMP
|
304 ENABLE_TEX_STREAM_COORD_SET
|
305 TEX_STREAM_COORD_SET(2) |
306 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(2));
307 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
309 DISABLE_TEX_STREAM_BUMP
|
310 ENABLE_TEX_STREAM_COORD_SET
|
311 TEX_STREAM_COORD_SET(3) |
312 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(3));
314 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
315 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(0));
316 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
317 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(1));
318 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
319 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(2));
320 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
321 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(3));
323 OUT_BATCH(_3DSTATE_RASTER_RULES_CMD
|
324 ENABLE_POINT_RASTER_RULE
|
325 OGL_POINT_RASTER_RULE
|
326 ENABLE_LINE_STRIP_PROVOKE_VRTX
|
327 ENABLE_TRI_FAN_PROVOKE_VRTX
|
328 ENABLE_TRI_STRIP_PROVOKE_VRTX
|
329 LINE_STRIP_PROVOKE_VRTX(1) |
330 TRI_FAN_PROVOKE_VRTX(2) |
331 TRI_STRIP_PROVOKE_VRTX(2));
333 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD
|
334 DISABLE_SCISSOR_RECT
);
336 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD
);
340 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM
);
341 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM
| DISABLE_PERSPECTIVE_DIVIDE
);
343 OUT_BATCH(_3DSTATE_W_STATE_CMD
);
344 OUT_BATCH(MAGIC_W_STATE_DWORD1
);
345 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
348 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD
);
349 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
355 #define emit( intel, state, size ) \
358 BEGIN_BATCH( size / sizeof(GLuint)); \
359 for (k = 0 ; k < size / sizeof(GLuint) ; k++) \
360 OUT_BATCH(state[k]); \
365 /* Push the state into the sarea and/or texture memory.
367 static void i830_emit_state( intelContextPtr intel
)
369 i830ContextPtr i830
= I830_CONTEXT(intel
);
370 struct i830_hw_state
*state
= i830
->current
;
375 dirty
= state
->active
& ~state
->emitted
;
377 if (dirty
& I830_UPLOAD_CTX
) {
378 if (VERBOSE
) fprintf(stderr
, "I830_UPLOAD_CTX:\n");
379 emit( i830
, state
->Ctx
, sizeof(state
->Ctx
) );
382 if (dirty
& I830_UPLOAD_BUFFERS
) {
383 if (VERBOSE
) fprintf(stderr
, "I830_UPLOAD_BUFFERS:\n");
384 emit( i830
, state
->Buffer
, sizeof(state
->Buffer
) );
387 if (dirty
& I830_UPLOAD_STIPPLE
) {
388 if (VERBOSE
) fprintf(stderr
, "I830_UPLOAD_STIPPLE:\n");
389 emit( i830
, state
->Stipple
, sizeof(state
->Stipple
) );
392 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
393 if ((dirty
& I830_UPLOAD_TEX(i
))) {
394 if (VERBOSE
) fprintf(stderr
, "I830_UPLOAD_TEX(%d):\n", i
);
395 emit( i830
, state
->Tex
[i
], sizeof(state
->Tex
[i
]));
398 if (dirty
& I830_UPLOAD_TEXBLEND(i
)) {
399 if (VERBOSE
) fprintf(stderr
, "I830_UPLOAD_TEXBLEND(%d):\n", i
);
400 emit( i830
, state
->TexBlend
[i
],
401 state
->TexBlendWordsUsed
[i
] * 4 );
405 state
->emitted
|= dirty
;
408 static void i830_destroy_context( intelContextPtr intel
)
410 _tnl_free_vertices(&intel
->ctx
);
413 static void i830_set_draw_offset( intelContextPtr intel
, int offset
)
415 i830ContextPtr i830
= I830_CONTEXT(intel
);
416 I830_STATECHANGE( i830
, I830_UPLOAD_BUFFERS
);
417 i830
->state
.Buffer
[I830_DESTREG_CBUFADDR2
] = offset
;
420 /* This isn't really handled at the moment.
422 static void i830_lost_hardware( intelContextPtr intel
)
424 I830_CONTEXT(intel
)->state
.emitted
= 0;
429 static void i830_emit_flush( intelContextPtr intel
)
434 OUT_BATCH( MI_FLUSH
| FLUSH_MAP_CACHE
);
442 void i830InitVtbl( i830ContextPtr i830
)
444 i830
->intel
.vtbl
.alloc_tex_obj
= i830AllocTexObj
;
445 i830
->intel
.vtbl
.check_vertex_size
= i830_check_vertex_size
;
446 i830
->intel
.vtbl
.clear_with_tris
= i830ClearWithTris
;
447 i830
->intel
.vtbl
.destroy
= i830_destroy_context
;
448 i830
->intel
.vtbl
.emit_invarient_state
= i830_emit_invarient_state
;
449 i830
->intel
.vtbl
.emit_state
= i830_emit_state
;
450 i830
->intel
.vtbl
.lost_hardware
= i830_lost_hardware
;
451 i830
->intel
.vtbl
.reduced_primitive_state
= i830_reduced_primitive_state
;
452 i830
->intel
.vtbl
.set_draw_offset
= i830_set_draw_offset
;
453 i830
->intel
.vtbl
.update_texture_state
= i830UpdateTextureState
;
454 i830
->intel
.vtbl
.emit_flush
= i830_emit_flush
;
455 i830
->intel
.vtbl
.render_start
= i830_render_start
;