1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "i830_context.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_regions.h"
33 #include "intel_tris.h"
34 #include "intel_fbo.h"
35 #include "intel_buffers.h"
37 #include "tnl/t_context.h"
38 #include "tnl/t_vertex.h"
39 #include "swrast_setup/swrast_setup.h"
40 #include "main/renderbuffer.h"
41 #include "main/framebuffer.h"
43 #define FILE_DEBUG_FLAG DEBUG_STATE
45 static bool i830_check_vertex_size(struct intel_context
*intel
,
48 #define SZ_TO_HW(sz) ((sz-2)&0x3)
49 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
50 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
52 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
53 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
54 intel->vertex_attr_count++; \
58 #define EMIT_PAD( N ) \
60 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
61 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
62 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
63 intel->vertex_attr_count++; \
67 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
68 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
71 i830_render_prevalidate(struct intel_context
*intel
)
76 i830_render_start(struct intel_context
*intel
)
78 struct gl_context
*ctx
= &intel
->ctx
;
79 struct i830_context
*i830
= i830_context(ctx
);
80 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
81 struct vertex_buffer
*VB
= &tnl
->vb
;
82 GLbitfield64 index_bitset
= tnl
->render_inputs_bitset
;
83 GLuint v0
= _3DSTATE_VFT0_CMD
;
84 GLuint v2
= _3DSTATE_VFT1_CMD
;
89 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
90 intel
->vertex_attr_count
= 0;
92 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
93 * build up a hardware vertex.
95 if (index_bitset
& BITFIELD64_RANGE(_TNL_ATTRIB_TEX0
, _TNL_NUM_TEX
)) {
96 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_4F_VIEWPORT
, VFT0_XYZW
);
97 intel
->coloroffset
= 4;
100 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_3F_VIEWPORT
, VFT0_XYZ
);
101 intel
->coloroffset
= 3;
104 if (index_bitset
& BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE
)) {
105 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE
, EMIT_1F
, VFT0_POINT_WIDTH
);
108 EMIT_ATTR(_TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_BGRA
, VFT0_DIFFUSE
);
110 intel
->specoffset
= 0;
111 if (index_bitset
& (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1
) |
112 BITFIELD64_BIT(_TNL_ATTRIB_FOG
))) {
113 if (index_bitset
& BITFIELD64_BIT(_TNL_ATTRIB_COLOR1
)) {
114 intel
->specoffset
= intel
->coloroffset
+ 1;
115 EMIT_ATTR(_TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
, VFT0_SPEC
);
120 if (index_bitset
& BITFIELD64_BIT(_TNL_ATTRIB_FOG
))
121 EMIT_ATTR(_TNL_ATTRIB_FOG
, EMIT_1UB_1F
, VFT0_SPEC
);
126 if (index_bitset
& BITFIELD64_RANGE(_TNL_ATTRIB_TEX0
, _TNL_NUM_TEX
)) {
129 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
130 if (index_bitset
& BITFIELD64_BIT(_TNL_ATTRIB_TEX(i
))) {
131 GLuint sz
= VB
->AttribPtr
[_TNL_ATTRIB_TEX0
+ i
]->size
;
133 GLuint mcs
= (i830
->state
.Tex
[i
][I830_TEXREG_MCS
] &
141 mcs
|= TEXCOORDTYPE_CARTESIAN
;
146 mcs
|= TEXCOORDTYPE_VECTOR
;
151 mcs
|= TEXCOORDTYPE_HOMOGENEOUS
;
158 EMIT_ATTR(_TNL_ATTRIB_TEX0
+ i
, emit
, 0);
159 v2
|= VRTX_TEX_SET_FMT(count
, SZ_TO_HW(sz
));
160 mcsb1
|= (count
+ 8) << (i
* 4);
162 if (mcs
!= i830
->state
.Tex
[i
][I830_TEXREG_MCS
]) {
163 I830_STATECHANGE(i830
, I830_UPLOAD_TEX(i
));
164 i830
->state
.Tex
[i
][I830_TEXREG_MCS
] = mcs
;
171 v0
|= VFT0_TEX_COUNT(count
);
174 /* Only need to change the vertex emit code if there has been a
175 * statechange to a new hardware vertex format:
177 if (v0
!= i830
->state
.Ctx
[I830_CTXREG_VF
] ||
178 v2
!= i830
->state
.Ctx
[I830_CTXREG_VF2
] ||
179 mcsb1
!= i830
->state
.Ctx
[I830_CTXREG_MCSB1
] ||
180 index_bitset
!= i830
->last_index_bitset
) {
183 I830_STATECHANGE(i830
, I830_UPLOAD_CTX
);
185 /* Must do this *after* statechange, so as not to affect
186 * buffered vertices reliant on the old state:
189 _tnl_install_attrs(ctx
,
191 intel
->vertex_attr_count
,
192 intel
->ViewportMatrix
.m
, 0);
194 intel
->vertex_size
>>= 2;
196 i830
->state
.Ctx
[I830_CTXREG_VF
] = v0
;
197 i830
->state
.Ctx
[I830_CTXREG_VF2
] = v2
;
198 i830
->state
.Ctx
[I830_CTXREG_MCSB1
] = mcsb1
;
199 i830
->last_index_bitset
= index_bitset
;
201 k
= i830_check_vertex_size(intel
, intel
->vertex_size
);
207 i830_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
209 struct i830_context
*i830
= i830_context(&intel
->ctx
);
210 GLuint st1
= i830
->state
.Stipple
[I830_STPREG_ST1
];
216 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
225 i830
->intel
.reduced_primitive
= rprim
;
227 if (st1
!= i830
->state
.Stipple
[I830_STPREG_ST1
]) {
228 INTEL_FIREVERTICES(intel
);
230 I830_STATECHANGE(i830
, I830_UPLOAD_STIPPLE
);
231 i830
->state
.Stipple
[I830_STPREG_ST1
] = st1
;
235 /* Pull apart the vertex format registers and figure out how large a
236 * vertex is supposed to be.
239 i830_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
241 struct i830_context
*i830
= i830_context(&intel
->ctx
);
242 int vft0
= i830
->state
.Ctx
[I830_CTXREG_VF
];
243 int vft1
= i830
->state
.Ctx
[I830_CTXREG_VF2
];
244 int nrtex
= (vft0
& VFT0_TEX_COUNT_MASK
) >> VFT0_TEX_COUNT_SHIFT
;
247 switch (vft0
& VFT0_XYZW_MASK
) {
261 fprintf(stderr
, "no xyzw specified\n");
265 if (vft0
& VFT0_SPEC
)
267 if (vft0
& VFT0_DIFFUSE
)
269 if (vft0
& VFT0_DEPTH_OFFSET
)
271 if (vft0
& VFT0_POINT_WIDTH
)
274 for (i
= 0; i
< nrtex
; i
++) {
275 switch (vft1
& VFT1_TEX0_MASK
) {
289 vft1
>>= VFT1_TEX1_SHIFT
;
293 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
295 return sz
== expected
;
299 i830_emit_invarient_state(struct intel_context
*intel
)
305 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
308 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
311 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
314 OUT_BATCH(_3DSTATE_FOG_MODE_CMD
);
315 OUT_BATCH(FOGFUNC_ENABLE
|
316 FOG_LINEAR_CONST
| FOGSRC_INDEX_Z
| ENABLE_FOG_DENSITY
);
321 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
323 DISABLE_TEX_STREAM_BUMP
|
324 ENABLE_TEX_STREAM_COORD_SET
|
325 TEX_STREAM_COORD_SET(0) |
326 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(0));
327 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
329 DISABLE_TEX_STREAM_BUMP
|
330 ENABLE_TEX_STREAM_COORD_SET
|
331 TEX_STREAM_COORD_SET(1) |
332 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(1));
333 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
335 DISABLE_TEX_STREAM_BUMP
|
336 ENABLE_TEX_STREAM_COORD_SET
|
337 TEX_STREAM_COORD_SET(2) |
338 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(2));
339 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
341 DISABLE_TEX_STREAM_BUMP
|
342 ENABLE_TEX_STREAM_COORD_SET
|
343 TEX_STREAM_COORD_SET(3) |
344 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(3));
346 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
347 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(0));
348 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
349 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(1));
350 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
351 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(2));
352 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
353 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(3));
355 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM
);
356 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM
| DISABLE_PERSPECTIVE_DIVIDE
);
358 OUT_BATCH(_3DSTATE_W_STATE_CMD
);
359 OUT_BATCH(MAGIC_W_STATE_DWORD1
);
360 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
363 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD
);
364 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
370 #define emit( intel, state, size ) \
371 intel_batchbuffer_data(intel, state, size, false)
374 get_dirty(struct i830_hw_state
*state
)
376 return state
->active
& ~state
->emitted
;
380 get_state_size(struct i830_hw_state
*state
)
382 GLuint dirty
= get_dirty(state
);
386 if (dirty
& I830_UPLOAD_INVARIENT
)
387 sz
+= 40 * sizeof(int);
389 if (dirty
& I830_UPLOAD_RASTER_RULES
)
390 sz
+= sizeof(state
->RasterRules
);
392 if (dirty
& I830_UPLOAD_CTX
)
393 sz
+= sizeof(state
->Ctx
);
395 if (dirty
& I830_UPLOAD_BUFFERS
)
396 sz
+= sizeof(state
->Buffer
);
398 if (dirty
& I830_UPLOAD_STIPPLE
)
399 sz
+= sizeof(state
->Stipple
);
401 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
402 if ((dirty
& I830_UPLOAD_TEX(i
)))
403 sz
+= sizeof(state
->Tex
[i
]);
405 if (dirty
& I830_UPLOAD_TEXBLEND(i
))
406 sz
+= state
->TexBlendWordsUsed
[i
] * 4;
413 /* Push the state into the sarea and/or texture memory.
416 i830_emit_state(struct intel_context
*intel
)
418 struct i830_context
*i830
= i830_context(&intel
->ctx
);
419 struct i830_hw_state
*state
= &i830
->state
;
422 drm_intel_bo
*aper_array
[3 + I830_TEX_UNITS
];
424 GET_CURRENT_CONTEXT(ctx
);
427 /* We don't hold the lock at this point, so want to make sure that
428 * there won't be a buffer wrap between the state emits and the primitive
431 * It might be better to talk about explicit places where
432 * scheduling is allowed, rather than assume that it is whenever a
433 * batchbuffer fills up.
435 intel_batchbuffer_require_space(intel
,
436 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
441 dirty
= get_dirty(state
);
443 aper_array
[aper_count
++] = intel
->batch
.bo
;
444 if (dirty
& I830_UPLOAD_BUFFERS
) {
445 aper_array
[aper_count
++] = state
->draw_region
->bo
;
446 if (state
->depth_region
)
447 aper_array
[aper_count
++] = state
->depth_region
->bo
;
450 for (i
= 0; i
< I830_TEX_UNITS
; i
++)
451 if (dirty
& I830_UPLOAD_TEX(i
)) {
452 if (state
->tex_buffer
[i
]) {
453 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
457 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
460 intel_batchbuffer_flush(intel
);
463 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i830 emit state");
469 /* Do this here as we may have flushed the batchbuffer above,
470 * causing more state to be dirty!
472 dirty
= get_dirty(state
);
473 state
->emitted
|= dirty
;
474 assert(get_dirty(state
) == 0);
476 if (dirty
& I830_UPLOAD_INVARIENT
) {
477 DBG("I830_UPLOAD_INVARIENT:\n");
478 i830_emit_invarient_state(intel
);
481 if (dirty
& I830_UPLOAD_RASTER_RULES
) {
482 DBG("I830_UPLOAD_RASTER_RULES:\n");
483 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
486 if (dirty
& I830_UPLOAD_CTX
) {
487 DBG("I830_UPLOAD_CTX:\n");
488 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
492 if (dirty
& I830_UPLOAD_BUFFERS
) {
495 DBG("I830_UPLOAD_BUFFERS:\n");
497 if (state
->depth_region
)
501 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR0
]);
502 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR1
]);
503 OUT_RELOC(state
->draw_region
->bo
,
504 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
506 if (state
->depth_region
) {
507 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR0
]);
508 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR1
]);
509 OUT_RELOC(state
->depth_region
->bo
,
510 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
513 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV0
]);
514 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV1
]);
515 OUT_BATCH(state
->Buffer
[I830_DESTREG_SENABLE
]);
516 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR0
]);
517 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR1
]);
518 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR2
]);
520 assert(state
->Buffer
[I830_DESTREG_DRAWRECT0
] != MI_NOOP
);
521 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT0
]);
522 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT1
]);
523 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT2
]);
524 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT3
]);
525 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT4
]);
526 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT5
]);
530 if (dirty
& I830_UPLOAD_STIPPLE
) {
531 DBG("I830_UPLOAD_STIPPLE:\n");
532 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
535 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
536 if ((dirty
& I830_UPLOAD_TEX(i
))) {
537 DBG("I830_UPLOAD_TEX(%d):\n", i
);
539 BEGIN_BATCH(I830_TEX_SETUP_SIZE
+ 1);
540 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0LI
]);
542 OUT_RELOC(state
->tex_buffer
[i
],
543 I915_GEM_DOMAIN_SAMPLER
, 0,
544 state
->tex_offset
[i
]);
546 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S1
]);
547 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S2
]);
548 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S3
]);
549 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S4
]);
550 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_MCS
]);
551 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_CUBE
]);
556 if (dirty
& I830_UPLOAD_TEXBLEND(i
)) {
557 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i
,
558 state
->TexBlendWordsUsed
[i
]);
559 emit(intel
, state
->TexBlend
[i
], state
->TexBlendWordsUsed
[i
] * 4);
563 assert(get_dirty(state
) == 0);
567 i830_destroy_context(struct intel_context
*intel
)
570 struct i830_context
*i830
= i830_context(&intel
->ctx
);
572 intel_region_release(&i830
->state
.draw_region
);
573 intel_region_release(&i830
->state
.depth_region
);
575 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
576 if (i830
->state
.tex_buffer
[i
] != NULL
) {
577 drm_intel_bo_unreference(i830
->state
.tex_buffer
[i
]);
578 i830
->state
.tex_buffer
[i
] = NULL
;
582 _tnl_free_vertices(&intel
->ctx
);
585 static uint32_t i830_render_target_format_for_mesa_format
[MESA_FORMAT_COUNT
] =
587 [MESA_FORMAT_ARGB8888
] = DV_PF_8888
,
588 [MESA_FORMAT_XRGB8888
] = DV_PF_8888
,
589 [MESA_FORMAT_RGB565
] = DV_PF_565
,
590 [MESA_FORMAT_ARGB1555
] = DV_PF_1555
,
591 [MESA_FORMAT_ARGB4444
] = DV_PF_4444
,
595 i830_render_target_supported(struct intel_context
*intel
,
596 struct gl_renderbuffer
*rb
)
598 gl_format format
= rb
->Format
;
600 if (format
== MESA_FORMAT_S8_Z24
||
601 format
== MESA_FORMAT_X8_Z24
||
602 format
== MESA_FORMAT_Z16
) {
606 return i830_render_target_format_for_mesa_format
[format
] != 0;
610 i830_set_draw_region(struct intel_context
*intel
,
611 struct intel_region
*color_regions
[],
612 struct intel_region
*depth_region
,
615 struct i830_context
*i830
= i830_context(&intel
->ctx
);
616 struct gl_context
*ctx
= &intel
->ctx
;
617 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
618 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
619 struct gl_renderbuffer
*drb
;
620 struct intel_renderbuffer
*idrb
= NULL
;
622 struct i830_hw_state
*state
= &i830
->state
;
623 uint32_t draw_x
, draw_y
;
625 if (state
->draw_region
!= color_regions
[0]) {
626 intel_region_reference(&state
->draw_region
, color_regions
[0]);
628 if (state
->depth_region
!= depth_region
) {
629 intel_region_reference(&state
->depth_region
, depth_region
);
633 * Set stride/cpp values
635 i915_set_buf_info_for_region(&state
->Buffer
[I830_DESTREG_CBUFADDR0
],
636 color_regions
[0], BUF_3D_ID_COLOR_BACK
);
638 i915_set_buf_info_for_region(&state
->Buffer
[I830_DESTREG_DBUFADDR0
],
639 depth_region
, BUF_3D_ID_DEPTH
);
642 * Compute/set I830_DESTREG_DV1 value
644 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
645 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z
); /* .5 */
648 value
|= i830_render_target_format_for_mesa_format
[intel_rb_format(irb
)];
651 if (depth_region
&& depth_region
->cpp
== 4) {
652 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
655 value
|= DEPTH_FRMT_16_FIXED
;
657 state
->Buffer
[I830_DESTREG_DV1
] = value
;
659 drb
= ctx
->DrawBuffer
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
661 drb
= ctx
->DrawBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
664 idrb
= intel_renderbuffer(drb
);
666 /* We set up the drawing rectangle to be offset into the color
667 * region's location in the miptree. If it doesn't match with
668 * depth's offsets, we can't render to it.
670 * (Well, not actually true -- the hw grew a bit to let depth's
671 * offset get forced to 0,0. We may want to use that if people are
672 * hitting that case. Also, some configurations may be supportable
673 * by tweaking the start offset of the buffers around, which we
674 * can't do in general due to tiling)
676 FALLBACK(intel
, I830_FALLBACK_DRAW_OFFSET
,
677 idrb
&& irb
&& (idrb
->draw_x
!= irb
->draw_x
||
678 idrb
->draw_y
!= irb
->draw_y
));
681 draw_x
= irb
->draw_x
;
682 draw_y
= irb
->draw_y
;
684 draw_x
= idrb
->draw_x
;
685 draw_y
= idrb
->draw_y
;
691 state
->Buffer
[I830_DESTREG_DRAWRECT0
] = _3DSTATE_DRAWRECT_INFO
;
692 state
->Buffer
[I830_DESTREG_DRAWRECT1
] = 0;
693 state
->Buffer
[I830_DESTREG_DRAWRECT2
] = (draw_y
<< 16) | draw_x
;
694 state
->Buffer
[I830_DESTREG_DRAWRECT3
] =
695 ((ctx
->DrawBuffer
->Width
+ draw_x
- 1) & 0xffff) |
696 ((ctx
->DrawBuffer
->Height
+ draw_y
- 1) << 16);
697 state
->Buffer
[I830_DESTREG_DRAWRECT4
] = (draw_y
<< 16) | draw_x
;
698 state
->Buffer
[I830_DESTREG_DRAWRECT5
] = MI_NOOP
;
700 I830_STATECHANGE(i830
, I830_UPLOAD_BUFFERS
);
704 * Update the hardware state for drawing into a window or framebuffer object.
706 * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
707 * places within the driver.
709 * Basically, this needs to be called any time the current framebuffer
710 * changes, the renderbuffers change, or we need to draw into different
714 i830_update_draw_buffer(struct intel_context
*intel
)
716 struct gl_context
*ctx
= &intel
->ctx
;
717 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
718 struct intel_region
*colorRegions
[MAX_DRAW_BUFFERS
], *depthRegion
= NULL
;
719 struct intel_renderbuffer
*irbDepth
= NULL
, *irbStencil
= NULL
;
722 /* this can happen during the initial context initialization */
726 irbDepth
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
727 irbStencil
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
729 /* Do this here, not core Mesa, since this function is called from
730 * many places within the driver.
732 if (ctx
->NewState
& _NEW_BUFFERS
) {
733 /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
734 _mesa_update_framebuffer(ctx
);
735 /* this updates the DrawBuffer's Width/Height if it's a FBO */
736 _mesa_update_draw_buffer_bounds(ctx
);
739 if (fb
->_Status
!= GL_FRAMEBUFFER_COMPLETE_EXT
) {
740 /* this may occur when we're called by glBindFrameBuffer() during
741 * the process of someone setting up renderbuffers, etc.
743 /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
747 /* How many color buffers are we drawing into?
749 * If there are zero buffers or the buffer is too big, don't configure any
750 * regions for hardware drawing. We'll fallback to software below. Not
751 * having regions set makes some of the software fallback paths faster.
753 if ((fb
->Width
> ctx
->Const
.MaxRenderbufferSize
)
754 || (fb
->Height
> ctx
->Const
.MaxRenderbufferSize
)
755 || (fb
->_NumColorDrawBuffers
== 0)) {
757 colorRegions
[0] = NULL
;
759 else if (fb
->_NumColorDrawBuffers
> 1) {
761 struct intel_renderbuffer
*irb
;
763 for (i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
764 irb
= intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
765 colorRegions
[i
] = (irb
&& irb
->mt
) ? irb
->mt
->region
: NULL
;
769 /* Get the intel_renderbuffer for the single colorbuffer we're drawing
773 /* drawing to window system buffer */
774 if (fb
->_ColorDrawBufferIndexes
[0] == BUFFER_FRONT_LEFT
)
775 colorRegions
[0] = intel_get_rb_region(fb
, BUFFER_FRONT_LEFT
);
777 colorRegions
[0] = intel_get_rb_region(fb
, BUFFER_BACK_LEFT
);
780 /* drawing to user-created FBO */
781 struct intel_renderbuffer
*irb
;
782 irb
= intel_renderbuffer(fb
->_ColorDrawBuffers
[0]);
783 colorRegions
[0] = (irb
&& irb
->mt
->region
) ? irb
->mt
->region
: NULL
;
787 if (!colorRegions
[0]) {
788 FALLBACK(intel
, INTEL_FALLBACK_DRAW_BUFFER
, true);
791 FALLBACK(intel
, INTEL_FALLBACK_DRAW_BUFFER
, false);
794 /* Check for depth fallback. */
795 if (irbDepth
&& irbDepth
->mt
) {
796 FALLBACK(intel
, INTEL_FALLBACK_DEPTH_BUFFER
, false);
797 depthRegion
= irbDepth
->mt
->region
;
798 } else if (irbDepth
&& !irbDepth
->mt
) {
799 FALLBACK(intel
, INTEL_FALLBACK_DEPTH_BUFFER
, true);
801 } else { /* !irbDepth */
802 /* No fallback is needed because there is no depth buffer. */
803 FALLBACK(intel
, INTEL_FALLBACK_DEPTH_BUFFER
, false);
807 /* Check for stencil fallback. */
808 if (irbStencil
&& irbStencil
->mt
) {
809 assert(intel_rb_format(irbStencil
) == MESA_FORMAT_S8_Z24
);
810 FALLBACK(intel
, INTEL_FALLBACK_STENCIL_BUFFER
, false);
811 } else if (irbStencil
&& !irbStencil
->mt
) {
812 FALLBACK(intel
, INTEL_FALLBACK_STENCIL_BUFFER
, true);
813 } else { /* !irbStencil */
814 /* No fallback is needed because there is no stencil buffer. */
815 FALLBACK(intel
, INTEL_FALLBACK_STENCIL_BUFFER
, false);
818 /* If we have a (packed) stencil buffer attached but no depth buffer,
819 * we still need to set up the shared depth/stencil state so we can use it.
821 if (depthRegion
== NULL
&& irbStencil
&& irbStencil
->mt
822 && intel_rb_format(irbStencil
) == MESA_FORMAT_S8_Z24
) {
823 depthRegion
= irbStencil
->mt
->region
;
827 * Update depth and stencil test state
829 ctx
->Driver
.Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
830 ctx
->Driver
.Enable(ctx
, GL_STENCIL_TEST
,
831 (ctx
->Stencil
.Enabled
&& fb
->Visual
.stencilBits
> 0));
833 intel
->vtbl
.set_draw_region(intel
, colorRegions
, depthRegion
,
834 fb
->_NumColorDrawBuffers
);
835 intel
->NewGLState
|= _NEW_BUFFERS
;
837 /* update viewport since it depends on window size */
838 intelCalcViewport(ctx
);
840 /* Set state we know depends on drawable parameters:
842 ctx
->Driver
.Scissor(ctx
, ctx
->Scissor
.X
, ctx
->Scissor
.Y
,
843 ctx
->Scissor
.Width
, ctx
->Scissor
.Height
);
845 ctx
->Driver
.DepthRange(ctx
, ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
847 /* Update culling direction which changes depending on the
848 * orientation of the buffer:
850 ctx
->Driver
.FrontFace(ctx
, ctx
->Polygon
.FrontFace
);
853 /* This isn't really handled at the moment.
856 i830_new_batch(struct intel_context
*intel
)
858 struct i830_context
*i830
= i830_context(&intel
->ctx
);
859 i830
->state
.emitted
= 0;
863 i830_assert_not_dirty( struct intel_context
*intel
)
865 struct i830_context
*i830
= i830_context(&intel
->ctx
);
866 assert(!get_dirty(&i830
->state
));
871 i830_invalidate_state(struct intel_context
*intel
, GLuint new_state
)
873 struct gl_context
*ctx
= &intel
->ctx
;
875 _swsetup_InvalidateState(ctx
, new_state
);
876 _tnl_InvalidateState(ctx
, new_state
);
877 _tnl_invalidate_vertex_state(ctx
, new_state
);
879 if (new_state
& _NEW_LIGHT
)
880 i830_update_provoking_vertex(&intel
->ctx
);
884 i830_is_hiz_depth_format(struct intel_context
*intel
, gl_format format
)
890 i830InitVtbl(struct i830_context
*i830
)
892 i830
->intel
.vtbl
.check_vertex_size
= i830_check_vertex_size
;
893 i830
->intel
.vtbl
.destroy
= i830_destroy_context
;
894 i830
->intel
.vtbl
.emit_state
= i830_emit_state
;
895 i830
->intel
.vtbl
.new_batch
= i830_new_batch
;
896 i830
->intel
.vtbl
.reduced_primitive_state
= i830_reduced_primitive_state
;
897 i830
->intel
.vtbl
.set_draw_region
= i830_set_draw_region
;
898 i830
->intel
.vtbl
.update_draw_buffer
= i830_update_draw_buffer
;
899 i830
->intel
.vtbl
.update_texture_state
= i830UpdateTextureState
;
900 i830
->intel
.vtbl
.render_start
= i830_render_start
;
901 i830
->intel
.vtbl
.render_prevalidate
= i830_render_prevalidate
;
902 i830
->intel
.vtbl
.assert_not_dirty
= i830_assert_not_dirty
;
903 i830
->intel
.vtbl
.finish_batch
= intel_finish_vb
;
904 i830
->intel
.vtbl
.invalidate_state
= i830_invalidate_state
;
905 i830
->intel
.vtbl
.render_target_supported
= i830_render_target_supported
;
906 i830
->intel
.vtbl
.is_hiz_depth_format
= i830_is_hiz_depth_format
;