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6dd64ef45e89c23bbf8bdbe274d11aa24dd1a77e
[mesa.git] / src / mesa / drivers / dri / i915 / i830_vtbl.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "i830_context.h"
29 #include "i830_reg.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_regions.h"
32 #include "intel_tris.h"
33 #include "intel_fbo.h"
34 #include "tnl/t_context.h"
35 #include "tnl/t_vertex.h"
36
37 #define FILE_DEBUG_FLAG DEBUG_STATE
38
39 static GLboolean i830_check_vertex_size(struct intel_context *intel,
40 GLuint expected);
41
42 #define SZ_TO_HW(sz) ((sz-2)&0x3)
43 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
44 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
45 do { \
46 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
47 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
48 intel->vertex_attr_count++; \
49 v0 |= V0; \
50 } while (0)
51
52 #define EMIT_PAD( N ) \
53 do { \
54 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
55 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
56 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
57 intel->vertex_attr_count++; \
58 } while (0)
59
60
61 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
62 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
63
64 static void
65 i830_render_prevalidate(struct intel_context *intel)
66 {
67 }
68
69 static void
70 i830_render_start(struct intel_context *intel)
71 {
72 GLcontext *ctx = &intel->ctx;
73 struct i830_context *i830 = i830_context(ctx);
74 TNLcontext *tnl = TNL_CONTEXT(ctx);
75 struct vertex_buffer *VB = &tnl->vb;
76 DECLARE_RENDERINPUTS(index_bitset);
77 GLuint v0 = _3DSTATE_VFT0_CMD;
78 GLuint v2 = _3DSTATE_VFT1_CMD;
79 GLuint mcsb1 = 0;
80
81 RENDERINPUTS_COPY(index_bitset, tnl->render_inputs_bitset);
82
83 /* Important:
84 */
85 VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
86 intel->vertex_attr_count = 0;
87
88 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
89 * build up a hardware vertex.
90 */
91 if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
92 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW);
93 intel->coloroffset = 4;
94 }
95 else {
96 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ);
97 intel->coloroffset = 3;
98 }
99
100 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_POINTSIZE)) {
101 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH);
102 }
103
104 EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE);
105
106 intel->specoffset = 0;
107 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1) ||
108 RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) {
109 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1)) {
110 intel->specoffset = intel->coloroffset + 1;
111 EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC);
112 }
113 else
114 EMIT_PAD(3);
115
116 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG))
117 EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC);
118 else
119 EMIT_PAD(1);
120 }
121
122 if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
123 int i, count = 0;
124
125 for (i = 0; i < I830_TEX_UNITS; i++) {
126 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) {
127 GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
128 GLuint emit;
129 GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
130 ~TEXCOORDTYPE_MASK);
131
132 switch (sz) {
133 case 1:
134 case 2:
135 emit = EMIT_2F;
136 sz = 2;
137 mcs |= TEXCOORDTYPE_CARTESIAN;
138 break;
139 case 3:
140 emit = EMIT_3F;
141 sz = 3;
142 mcs |= TEXCOORDTYPE_VECTOR;
143 break;
144 case 4:
145 emit = EMIT_3F_XYW;
146 sz = 3;
147 mcs |= TEXCOORDTYPE_HOMOGENEOUS;
148 break;
149 default:
150 continue;
151 };
152
153
154 EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
155 v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
156 mcsb1 |= (count + 8) << (i * 4);
157
158 if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) {
159 I830_STATECHANGE(i830, I830_UPLOAD_TEX(i));
160 i830->state.Tex[i][I830_TEXREG_MCS] = mcs;
161 }
162
163 count++;
164 }
165 }
166
167 v0 |= VFT0_TEX_COUNT(count);
168 }
169
170 /* Only need to change the vertex emit code if there has been a
171 * statechange to a new hardware vertex format:
172 */
173 if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
174 v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
175 mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
176 !RENDERINPUTS_EQUAL(index_bitset, i830->last_index_bitset)) {
177 int k;
178
179 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
180
181 /* Must do this *after* statechange, so as not to affect
182 * buffered vertices reliant on the old state:
183 */
184 intel->vertex_size =
185 _tnl_install_attrs(ctx,
186 intel->vertex_attrs,
187 intel->vertex_attr_count,
188 intel->ViewportMatrix.m, 0);
189
190 intel->vertex_size >>= 2;
191
192 i830->state.Ctx[I830_CTXREG_VF] = v0;
193 i830->state.Ctx[I830_CTXREG_VF2] = v2;
194 i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
195 RENDERINPUTS_COPY(i830->last_index_bitset, index_bitset);
196
197 k = i830_check_vertex_size(intel, intel->vertex_size);
198 assert(k);
199 }
200 }
201
202 static void
203 i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
204 {
205 struct i830_context *i830 = i830_context(&intel->ctx);
206 GLuint st1 = i830->state.Stipple[I830_STPREG_ST1];
207
208 st1 &= ~ST1_ENABLE;
209
210 switch (rprim) {
211 case GL_TRIANGLES:
212 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
213 st1 |= ST1_ENABLE;
214 break;
215 case GL_LINES:
216 case GL_POINTS:
217 default:
218 break;
219 }
220
221 i830->intel.reduced_primitive = rprim;
222
223 if (st1 != i830->state.Stipple[I830_STPREG_ST1]) {
224 INTEL_FIREVERTICES(intel);
225
226 I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
227 i830->state.Stipple[I830_STPREG_ST1] = st1;
228 }
229 }
230
231 /* Pull apart the vertex format registers and figure out how large a
232 * vertex is supposed to be.
233 */
234 static GLboolean
235 i830_check_vertex_size(struct intel_context *intel, GLuint expected)
236 {
237 struct i830_context *i830 = i830_context(&intel->ctx);
238 int vft0 = i830->current->Ctx[I830_CTXREG_VF];
239 int vft1 = i830->current->Ctx[I830_CTXREG_VF2];
240 int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT;
241 int i, sz = 0;
242
243 switch (vft0 & VFT0_XYZW_MASK) {
244 case VFT0_XY:
245 sz = 2;
246 break;
247 case VFT0_XYZ:
248 sz = 3;
249 break;
250 case VFT0_XYW:
251 sz = 3;
252 break;
253 case VFT0_XYZW:
254 sz = 4;
255 break;
256 default:
257 fprintf(stderr, "no xyzw specified\n");
258 return 0;
259 }
260
261 if (vft0 & VFT0_SPEC)
262 sz++;
263 if (vft0 & VFT0_DIFFUSE)
264 sz++;
265 if (vft0 & VFT0_DEPTH_OFFSET)
266 sz++;
267 if (vft0 & VFT0_POINT_WIDTH)
268 sz++;
269
270 for (i = 0; i < nrtex; i++) {
271 switch (vft1 & VFT1_TEX0_MASK) {
272 case TEXCOORDFMT_2D:
273 sz += 2;
274 break;
275 case TEXCOORDFMT_3D:
276 sz += 3;
277 break;
278 case TEXCOORDFMT_4D:
279 sz += 4;
280 break;
281 case TEXCOORDFMT_1D:
282 sz += 1;
283 break;
284 }
285 vft1 >>= VFT1_TEX1_SHIFT;
286 }
287
288 if (sz != expected)
289 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
290
291 return sz == expected;
292 }
293
294 static void
295 i830_emit_invarient_state(struct intel_context *intel)
296 {
297 BATCH_LOCALS;
298
299 BEGIN_BATCH(29);
300
301 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
302 OUT_BATCH(0);
303
304 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
305 OUT_BATCH(0);
306
307 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
308 OUT_BATCH(0);
309
310 OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
311 OUT_BATCH(FOGFUNC_ENABLE |
312 FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
313 OUT_BATCH(0);
314 OUT_BATCH(0);
315
316
317 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
318 MAP_UNIT(0) |
319 DISABLE_TEX_STREAM_BUMP |
320 ENABLE_TEX_STREAM_COORD_SET |
321 TEX_STREAM_COORD_SET(0) |
322 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
323 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
324 MAP_UNIT(1) |
325 DISABLE_TEX_STREAM_BUMP |
326 ENABLE_TEX_STREAM_COORD_SET |
327 TEX_STREAM_COORD_SET(1) |
328 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
329 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
330 MAP_UNIT(2) |
331 DISABLE_TEX_STREAM_BUMP |
332 ENABLE_TEX_STREAM_COORD_SET |
333 TEX_STREAM_COORD_SET(2) |
334 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
335 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
336 MAP_UNIT(3) |
337 DISABLE_TEX_STREAM_BUMP |
338 ENABLE_TEX_STREAM_COORD_SET |
339 TEX_STREAM_COORD_SET(3) |
340 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
341
342 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
343 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
344 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
345 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
346 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
347 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
348 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
349 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
350
351 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
352 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
353
354 OUT_BATCH(_3DSTATE_W_STATE_CMD);
355 OUT_BATCH(MAGIC_W_STATE_DWORD1);
356 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
357
358
359 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
360 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
361
362 ADVANCE_BATCH();
363 }
364
365
366 #define emit( intel, state, size ) \
367 intel_batchbuffer_data(intel->batch, state, size )
368
369 static GLuint
370 get_dirty(struct i830_hw_state *state)
371 {
372 return state->active & ~state->emitted;
373 }
374
375 static GLuint
376 get_state_size(struct i830_hw_state *state)
377 {
378 GLuint dirty = get_dirty(state);
379 GLuint sz = 0;
380 GLuint i;
381
382 if (dirty & I830_UPLOAD_INVARIENT)
383 sz += 40 * sizeof(int);
384
385 if (dirty & I830_UPLOAD_RASTER_RULES)
386 sz += sizeof(state->RasterRules);
387
388 if (dirty & I830_UPLOAD_CTX)
389 sz += sizeof(state->Ctx);
390
391 if (dirty & I830_UPLOAD_BUFFERS)
392 sz += sizeof(state->Buffer);
393
394 if (dirty & I830_UPLOAD_STIPPLE)
395 sz += sizeof(state->Stipple);
396
397 for (i = 0; i < I830_TEX_UNITS; i++) {
398 if ((dirty & I830_UPLOAD_TEX(i)))
399 sz += sizeof(state->Tex[i]);
400
401 if (dirty & I830_UPLOAD_TEXBLEND(i))
402 sz += state->TexBlendWordsUsed[i] * 4;
403 }
404
405 return sz;
406 }
407
408
409 /* Push the state into the sarea and/or texture memory.
410 */
411 static void
412 i830_emit_state(struct intel_context *intel)
413 {
414 struct i830_context *i830 = i830_context(&intel->ctx);
415 struct i830_hw_state *state = i830->current;
416 int i, count;
417 GLuint dirty;
418 dri_bo *aper_array[3 + I830_TEX_UNITS];
419 int aper_count;
420 GET_CURRENT_CONTEXT(ctx);
421 BATCH_LOCALS;
422
423 /* We don't hold the lock at this point, so want to make sure that
424 * there won't be a buffer wrap between the state emits and the primitive
425 * emit header.
426 *
427 * It might be better to talk about explicit places where
428 * scheduling is allowed, rather than assume that it is whenever a
429 * batchbuffer fills up.
430 */
431 intel_batchbuffer_require_space(intel->batch,
432 get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
433 count = 0;
434 again:
435 aper_count = 0;
436 dirty = get_dirty(state);
437
438 aper_array[aper_count++] = intel->batch->buf;
439 if (dirty & I830_UPLOAD_BUFFERS) {
440 aper_array[aper_count++] = state->draw_region->buffer;
441 if (state->depth_region)
442 aper_array[aper_count++] = state->depth_region->buffer;
443 }
444
445 for (i = 0; i < I830_TEX_UNITS; i++)
446 if (dirty & I830_UPLOAD_TEX(i)) {
447 if (state->tex_buffer[i]) {
448 aper_array[aper_count++] = state->tex_buffer[i];
449 }
450 }
451
452 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
453 if (count == 0) {
454 count++;
455 intel_batchbuffer_flush(intel->batch);
456 goto again;
457 } else {
458 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state");
459 assert(0);
460 }
461 }
462
463
464 /* Do this here as we may have flushed the batchbuffer above,
465 * causing more state to be dirty!
466 */
467 dirty = get_dirty(state);
468 state->emitted |= dirty;
469 assert(get_dirty(state) == 0);
470
471 if (dirty & I830_UPLOAD_INVARIENT) {
472 DBG("I830_UPLOAD_INVARIENT:\n");
473 i830_emit_invarient_state(intel);
474 }
475
476 if (dirty & I830_UPLOAD_RASTER_RULES) {
477 DBG("I830_UPLOAD_RASTER_RULES:\n");
478 emit(intel, state->RasterRules, sizeof(state->RasterRules));
479 }
480
481 if (dirty & I830_UPLOAD_CTX) {
482 DBG("I830_UPLOAD_CTX:\n");
483 emit(intel, state->Ctx, sizeof(state->Ctx));
484
485 }
486
487 if (dirty & I830_UPLOAD_BUFFERS) {
488 GLuint count = 15;
489
490 DBG("I830_UPLOAD_BUFFERS:\n");
491
492 if (state->depth_region)
493 count += 3;
494
495 BEGIN_BATCH(count);
496 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
497 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
498 OUT_RELOC(state->draw_region->buffer,
499 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
500 state->draw_region->draw_offset);
501
502 if (state->depth_region) {
503 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
504 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
505 OUT_RELOC(state->depth_region->buffer,
506 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
507 state->depth_region->draw_offset);
508 }
509
510 OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
511 OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
512 OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
513 OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
514 OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
515 OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
516
517 assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
518 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
519 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
520 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
521 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
522 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
523 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
524 ADVANCE_BATCH();
525 }
526
527 if (dirty & I830_UPLOAD_STIPPLE) {
528 DBG("I830_UPLOAD_STIPPLE:\n");
529 emit(intel, state->Stipple, sizeof(state->Stipple));
530 }
531
532 for (i = 0; i < I830_TEX_UNITS; i++) {
533 if ((dirty & I830_UPLOAD_TEX(i))) {
534 DBG("I830_UPLOAD_TEX(%d):\n", i);
535
536 BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1);
537 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
538
539 if (state->tex_buffer[i]) {
540 OUT_RELOC(state->tex_buffer[i],
541 I915_GEM_DOMAIN_SAMPLER, 0,
542 state->tex_offset[i]);
543 }
544 else {
545 OUT_BATCH(state->tex_offset[i]);
546 }
547
548 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]);
549 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]);
550 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]);
551 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]);
552 OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]);
553 OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]);
554
555 ADVANCE_BATCH();
556 }
557
558 if (dirty & I830_UPLOAD_TEXBLEND(i)) {
559 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
560 state->TexBlendWordsUsed[i]);
561 emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
562 }
563 }
564
565 intel->batch->dirty_state &= ~dirty;
566 assert(get_dirty(state) == 0);
567 assert((intel->batch->dirty_state & (1<<1)) == 0);
568 }
569
570 static void
571 i830_destroy_context(struct intel_context *intel)
572 {
573 GLuint i;
574 struct i830_context *i830 = i830_context(&intel->ctx);
575
576 intel_region_release(&i830->state.draw_region);
577 intel_region_release(&i830->state.depth_region);
578 intel_region_release(&i830->initial.draw_region);
579 intel_region_release(&i830->initial.depth_region);
580
581 for (i = 0; i < I830_TEX_UNITS; i++) {
582 if (i830->state.tex_buffer[i] != NULL) {
583 dri_bo_unreference(i830->state.tex_buffer[i]);
584 i830->state.tex_buffer[i] = NULL;
585 }
586 }
587
588 _tnl_free_vertices(&intel->ctx);
589 }
590
591 static void
592 i830_set_draw_region(struct intel_context *intel,
593 struct intel_region *color_regions[],
594 struct intel_region *depth_region,
595 GLuint num_regions)
596 {
597 struct i830_context *i830 = i830_context(&intel->ctx);
598 GLcontext *ctx = &intel->ctx;
599 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
600 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
601 GLuint value;
602 struct i830_hw_state *state = &i830->state;
603
604 if (state->draw_region != color_regions[0]) {
605 intel_region_release(&state->draw_region);
606 intel_region_reference(&state->draw_region, color_regions[0]);
607 }
608 if (state->depth_region != depth_region) {
609 intel_region_release(&state->depth_region);
610 intel_region_reference(&state->depth_region, depth_region);
611 }
612
613 /*
614 * Set stride/cpp values
615 */
616 i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_CBUFADDR0],
617 color_regions[0], BUF_3D_ID_COLOR_BACK);
618
619 i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_DBUFADDR0],
620 depth_region, BUF_3D_ID_DEPTH);
621
622 /*
623 * Compute/set I830_DESTREG_DV1 value
624 */
625 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
626 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */
627
628 if (irb != NULL) {
629 switch (irb->Base.Format) {
630 case MESA_FORMAT_ARGB8888:
631 case MESA_FORMAT_XRGB8888:
632 value |= DV_PF_8888;
633 break;
634 case MESA_FORMAT_RGB565:
635 value |= DV_PF_565;
636 break;
637 case MESA_FORMAT_ARGB1555:
638 value |= DV_PF_1555;
639 break;
640 case MESA_FORMAT_ARGB4444:
641 value |= DV_PF_4444;
642 break;
643 default:
644 _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
645 irb->Base.Format);
646 }
647 }
648
649 if (depth_region && depth_region->cpp == 4) {
650 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
651 }
652 else {
653 value |= DEPTH_FRMT_16_FIXED;
654 }
655 state->Buffer[I830_DESTREG_DV1] = value;
656
657 state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
658 state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
659 state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
660 state->Buffer[I830_DESTREG_DRAWRECT3] =
661 (ctx->DrawBuffer->Width & 0xffff) |
662 (ctx->DrawBuffer->Height << 16);
663 state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
664 state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
665
666 I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
667 }
668
669 /* This isn't really handled at the moment.
670 */
671 static void
672 i830_new_batch(struct intel_context *intel)
673 {
674 struct i830_context *i830 = i830_context(&intel->ctx);
675 i830->state.emitted = 0;
676 }
677
678 static void
679 i830_assert_not_dirty( struct intel_context *intel )
680 {
681 struct i830_context *i830 = i830_context(&intel->ctx);
682 struct i830_hw_state *state = i830->current;
683 assert(!get_dirty(state));
684 }
685
686 static void
687 i830_invalidate_state(struct intel_context *intel, GLuint new_state)
688 {
689 if (new_state & _NEW_LIGHT)
690 i830_update_provoking_vertex(&intel->ctx);
691 }
692
693 void
694 i830InitVtbl(struct i830_context *i830)
695 {
696 i830->intel.vtbl.check_vertex_size = i830_check_vertex_size;
697 i830->intel.vtbl.destroy = i830_destroy_context;
698 i830->intel.vtbl.emit_state = i830_emit_state;
699 i830->intel.vtbl.new_batch = i830_new_batch;
700 i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state;
701 i830->intel.vtbl.set_draw_region = i830_set_draw_region;
702 i830->intel.vtbl.update_texture_state = i830UpdateTextureState;
703 i830->intel.vtbl.render_start = i830_render_start;
704 i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
705 i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
706 i830->intel.vtbl.finish_batch = intel_finish_vb;
707 i830->intel.vtbl.invalidate_state = i830_invalidate_state;
708 }