src/mesa/drivers/dri/i915/i830_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "glapi/glapi.h"
  29 #include "main/texformat.h"
  30
  31 #include "i830_context.h"
  32 #include "i830_reg.h"
  33 #include "intel_batchbuffer.h"
  34 #include "intel_regions.h"
  35 #include "intel_tris.h"
  36 #include "intel_fbo.h"
  37 #include "tnl/t_context.h"
  38 #include "tnl/t_vertex.h"
  39
  40 #define FILE_DEBUG_FLAG DEBUG_STATE
  41
  42 static GLboolean i830_check_vertex_size(struct intel_context *intel,
  43                                         GLuint expected);
  44
  45 #define SZ_TO_HW(sz)  ((sz-2)&0x3)
  46 #define EMIT_SZ(sz)   (EMIT_1F + (sz) - 1)
  47 #define EMIT_ATTR( ATTR, STYLE, V0 )                                    \
  48 do {                                                                    \
  49    intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR);       \
  50    intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE);      \
  51    intel->vertex_attr_count++;                                          \
  52    v0 |= V0;                                                            \
  53 } while (0)
  54
  55 #define EMIT_PAD( N )                                                   \
  56 do {                                                                    \
  57    intel->vertex_attrs[intel->vertex_attr_count].attrib = 0;            \
  58    intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD;     \
  59    intel->vertex_attrs[intel->vertex_attr_count].offset = (N);          \
  60    intel->vertex_attr_count++;                                          \
  61 } while (0)
  62
  63
  64 #define VRTX_TEX_SET_FMT(n, x)          ((x)<<((n)*2))
  65 #define TEXBIND_SET(n, x)               ((x)<<((n)*4))
  66
  67 static void
  68 i830_render_prevalidate(struct intel_context *intel)
  69 {
  70 }
  71
  72 static void
  73 i830_render_start(struct intel_context *intel)
  74 {
  75    GLcontext *ctx = &intel->ctx;
  76    struct i830_context *i830 = i830_context(ctx);
  77    TNLcontext *tnl = TNL_CONTEXT(ctx);
  78    struct vertex_buffer *VB = &tnl->vb;
  79    DECLARE_RENDERINPUTS(index_bitset);
  80    GLuint v0 = _3DSTATE_VFT0_CMD;
  81    GLuint v2 = _3DSTATE_VFT1_CMD;
  82    GLuint mcsb1 = 0;
  83
  84    RENDERINPUTS_COPY(index_bitset, tnl->render_inputs_bitset);
  85
  86    /* Important:
  87     */
  88    VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
  89    intel->vertex_attr_count = 0;
  90
  91    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
  92     * build up a hardware vertex.
  93     */
  94    if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
  95       EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW);
  96       intel->coloroffset = 4;
  97    }
  98    else {
  99       EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ);
 100       intel->coloroffset = 3;
 101    }
 102
 103    if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_POINTSIZE)) {
 104       EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH);
 105    }
 106
 107    EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE);
 108
 109    intel->specoffset = 0;
 110    if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1) ||
 111        RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) {
 112       if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1)) {
 113          intel->specoffset = intel->coloroffset + 1;
 114          EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC);
 115       }
 116       else
 117          EMIT_PAD(3);
 118
 119       if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG))
 120          EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC);
 121       else
 122          EMIT_PAD(1);
 123    }
 124
 125    if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
 126       int i, count = 0;
 127
 128       for (i = 0; i < I830_TEX_UNITS; i++) {
 129          if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) {
 130             GLuint sz = VB->TexCoordPtr[i]->size;
 131             GLuint emit;
 132             GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
 133                           ~TEXCOORDTYPE_MASK);
 134
 135             switch (sz) {
 136             case 1:
 137             case 2:
 138                emit = EMIT_2F;
 139                sz = 2;
 140                mcs |= TEXCOORDTYPE_CARTESIAN;
 141                break;
 142             case 3:
 143                emit = EMIT_3F;
 144                sz = 3;
 145                mcs |= TEXCOORDTYPE_VECTOR;
 146                break;
 147             case 4:
 148                emit = EMIT_3F_XYW;
 149                sz = 3;
 150                mcs |= TEXCOORDTYPE_HOMOGENEOUS;
 151                break;
 152             default:
 153                continue;
 154             };
 155
 156
 157             EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
 158             v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
 159             mcsb1 |= (count + 8) << (i * 4);
 160
 161             if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) {
 162                I830_STATECHANGE(i830, I830_UPLOAD_TEX(i));
 163                i830->state.Tex[i][I830_TEXREG_MCS] = mcs;
 164             }
 165
 166             count++;
 167          }
 168       }
 169
 170       v0 |= VFT0_TEX_COUNT(count);
 171    }
 172
 173    /* Only need to change the vertex emit code if there has been a
 174     * statechange to a new hardware vertex format:
 175     */
 176    if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
 177        v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
 178        mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
 179        !RENDERINPUTS_EQUAL(index_bitset, i830->last_index_bitset)) {
 180       int k;
 181
 182       I830_STATECHANGE(i830, I830_UPLOAD_CTX);
 183
 184       /* Must do this *after* statechange, so as not to affect
 185        * buffered vertices reliant on the old state:
 186        */
 187       intel->vertex_size =
 188          _tnl_install_attrs(ctx,
 189                             intel->vertex_attrs,
 190                             intel->vertex_attr_count,
 191                             intel->ViewportMatrix.m, 0);
 192
 193       intel->vertex_size >>= 2;
 194
 195       i830->state.Ctx[I830_CTXREG_VF] = v0;
 196       i830->state.Ctx[I830_CTXREG_VF2] = v2;
 197       i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
 198       RENDERINPUTS_COPY(i830->last_index_bitset, index_bitset);
 199
 200       k = i830_check_vertex_size(intel, intel->vertex_size);
 201       assert(k);
 202    }
 203 }
 204
 205 static void
 206 i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
 207 {
 208    struct i830_context *i830 = i830_context(&intel->ctx);
 209    GLuint st1 = i830->state.Stipple[I830_STPREG_ST1];
 210
 211    st1 &= ~ST1_ENABLE;
 212
 213    switch (rprim) {
 214    case GL_TRIANGLES:
 215       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
 216          st1 |= ST1_ENABLE;
 217       break;
 218    case GL_LINES:
 219    case GL_POINTS:
 220    default:
 221       break;
 222    }
 223
 224    i830->intel.reduced_primitive = rprim;
 225
 226    if (st1 != i830->state.Stipple[I830_STPREG_ST1]) {
 227       INTEL_FIREVERTICES(intel);
 228
 229       I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
 230       i830->state.Stipple[I830_STPREG_ST1] = st1;
 231    }
 232 }
 233
 234 /* Pull apart the vertex format registers and figure out how large a
 235  * vertex is supposed to be.
 236  */
 237 static GLboolean
 238 i830_check_vertex_size(struct intel_context *intel, GLuint expected)
 239 {
 240    struct i830_context *i830 = i830_context(&intel->ctx);
 241    int vft0 = i830->current->Ctx[I830_CTXREG_VF];
 242    int vft1 = i830->current->Ctx[I830_CTXREG_VF2];
 243    int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT;
 244    int i, sz = 0;
 245
 246    switch (vft0 & VFT0_XYZW_MASK) {
 247    case VFT0_XY:
 248       sz = 2;
 249       break;
 250    case VFT0_XYZ:
 251       sz = 3;
 252       break;
 253    case VFT0_XYW:
 254       sz = 3;
 255       break;
 256    case VFT0_XYZW:
 257       sz = 4;
 258       break;
 259    default:
 260       fprintf(stderr, "no xyzw specified\n");
 261       return 0;
 262    }
 263
 264    if (vft0 & VFT0_SPEC)
 265       sz++;
 266    if (vft0 & VFT0_DIFFUSE)
 267       sz++;
 268    if (vft0 & VFT0_DEPTH_OFFSET)
 269       sz++;
 270    if (vft0 & VFT0_POINT_WIDTH)
 271       sz++;
 272
 273    for (i = 0; i < nrtex; i++) {
 274       switch (vft1 & VFT1_TEX0_MASK) {
 275       case TEXCOORDFMT_2D:
 276          sz += 2;
 277          break;
 278       case TEXCOORDFMT_3D:
 279          sz += 3;
 280          break;
 281       case TEXCOORDFMT_4D:
 282          sz += 4;
 283          break;
 284       case TEXCOORDFMT_1D:
 285          sz += 1;
 286          break;
 287       }
 288       vft1 >>= VFT1_TEX1_SHIFT;
 289    }
 290
 291    if (sz != expected)
 292       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 293
 294    return sz == expected;
 295 }
 296
 297 static void
 298 i830_emit_invarient_state(struct intel_context *intel)
 299 {
 300    BATCH_LOCALS;
 301
 302    BEGIN_BATCH(29, IGNORE_CLIPRECTS);
 303
 304    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 305    OUT_BATCH(0);
 306
 307    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 308    OUT_BATCH(0);
 309
 310    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 311    OUT_BATCH(0);
 312
 313    OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
 314    OUT_BATCH(FOGFUNC_ENABLE |
 315              FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
 316    OUT_BATCH(0);
 317    OUT_BATCH(0);
 318
 319
 320    OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 321              MAP_UNIT(0) |
 322              DISABLE_TEX_STREAM_BUMP |
 323              ENABLE_TEX_STREAM_COORD_SET |
 324              TEX_STREAM_COORD_SET(0) |
 325              ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
 326    OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 327              MAP_UNIT(1) |
 328              DISABLE_TEX_STREAM_BUMP |
 329              ENABLE_TEX_STREAM_COORD_SET |
 330              TEX_STREAM_COORD_SET(1) |
 331              ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
 332    OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 333              MAP_UNIT(2) |
 334              DISABLE_TEX_STREAM_BUMP |
 335              ENABLE_TEX_STREAM_COORD_SET |
 336              TEX_STREAM_COORD_SET(2) |
 337              ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
 338    OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 339              MAP_UNIT(3) |
 340              DISABLE_TEX_STREAM_BUMP |
 341              ENABLE_TEX_STREAM_COORD_SET |
 342              TEX_STREAM_COORD_SET(3) |
 343              ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
 344
 345    OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
 346    OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
 347    OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
 348    OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
 349    OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
 350    OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
 351    OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
 352    OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
 353
 354    OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
 355    OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
 356
 357    OUT_BATCH(_3DSTATE_W_STATE_CMD);
 358    OUT_BATCH(MAGIC_W_STATE_DWORD1);
 359    OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
 360
 361
 362    OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
 363    OUT_BATCH(0x80808080);       /* .5 required in alpha for GL_DOT3_RGBA_EXT */
 364
 365    ADVANCE_BATCH();
 366 }
 367
 368
 369 #define emit( intel, state, size )                      \
 370    intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
 371
 372 static GLuint
 373 get_dirty(struct i830_hw_state *state)
 374 {
 375    return state->active & ~state->emitted;
 376 }
 377
 378 static GLuint
 379 get_state_size(struct i830_hw_state *state)
 380 {
 381    GLuint dirty = get_dirty(state);
 382    GLuint sz = 0;
 383    GLuint i;
 384
 385    if (dirty & I830_UPLOAD_INVARIENT)
 386       sz += 40 * sizeof(int);
 387
 388    if (dirty & I830_UPLOAD_RASTER_RULES)
 389       sz += sizeof(state->RasterRules);
 390
 391    if (dirty & I830_UPLOAD_CTX)
 392       sz += sizeof(state->Ctx);
 393
 394    if (dirty & I830_UPLOAD_BUFFERS)
 395       sz += sizeof(state->Buffer);
 396
 397    if (dirty & I830_UPLOAD_STIPPLE)
 398       sz += sizeof(state->Stipple);
 399
 400    for (i = 0; i < I830_TEX_UNITS; i++) {
 401       if ((dirty & I830_UPLOAD_TEX(i)))
 402          sz += sizeof(state->Tex[i]);
 403
 404       if (dirty & I830_UPLOAD_TEXBLEND(i))
 405          sz += state->TexBlendWordsUsed[i] * 4;
 406    }
 407
 408    return sz;
 409 }
 410
 411
 412 /* Push the state into the sarea and/or texture memory.
 413  */
 414 static void
 415 i830_emit_state(struct intel_context *intel)
 416 {
 417    struct i830_context *i830 = i830_context(&intel->ctx);
 418    struct i830_hw_state *state = i830->current;
 419    int i, count;
 420    GLuint dirty;
 421    dri_bo *aper_array[3 + I830_TEX_UNITS];
 422    int aper_count;
 423    GET_CURRENT_CONTEXT(ctx);
 424    BATCH_LOCALS;
 425
 426    /* We don't hold the lock at this point, so want to make sure that
 427     * there won't be a buffer wrap between the state emits and the primitive
 428     * emit header.
 429     *
 430     * It might be better to talk about explicit places where
 431     * scheduling is allowed, rather than assume that it is whenever a
 432     * batchbuffer fills up.
 433     *
 434     * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
 435     * will be emitted under.
 436     */
 437    intel_batchbuffer_require_space(intel->batch,
 438                                    get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
 439                                    LOOP_CLIPRECTS);
 440    count = 0;
 441  again:
 442    aper_count = 0;
 443    dirty = get_dirty(state);
 444
 445    aper_array[aper_count++] = intel->batch->buf;
 446    if (dirty & I830_UPLOAD_BUFFERS) {
 447       aper_array[aper_count++] = state->draw_region->buffer;
 448       if (state->depth_region)
 449          aper_array[aper_count++] = state->depth_region->buffer;
 450    }
 451
 452    for (i = 0; i < I830_TEX_UNITS; i++)
 453      if (dirty & I830_UPLOAD_TEX(i)) {
 454         if (state->tex_buffer[i]) {
 455            aper_array[aper_count++] = state->tex_buffer[i];
 456         }
 457      }
 458
 459    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
 460        if (count == 0) {
 461            count++;
 462            intel_batchbuffer_flush(intel->batch);
 463            goto again;
 464        } else {
 465            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state");
 466            assert(0);
 467        }
 468    }
 469
 470
 471    /* Do this here as we may have flushed the batchbuffer above,
 472     * causing more state to be dirty!
 473     */
 474    dirty = get_dirty(state);
 475    state->emitted |= dirty;
 476    assert(get_dirty(state) == 0);
 477
 478    if (dirty & I830_UPLOAD_INVARIENT) {
 479       DBG("I830_UPLOAD_INVARIENT:\n");
 480       i830_emit_invarient_state(intel);
 481    }
 482
 483    if (dirty & I830_UPLOAD_RASTER_RULES) {
 484       DBG("I830_UPLOAD_RASTER_RULES:\n");
 485       emit(intel, state->RasterRules, sizeof(state->RasterRules));
 486    }
 487
 488    if (dirty & I830_UPLOAD_CTX) {
 489       DBG("I830_UPLOAD_CTX:\n");
 490       emit(intel, state->Ctx, sizeof(state->Ctx));
 491
 492    }
 493
 494    if (dirty & I830_UPLOAD_BUFFERS) {
 495       GLuint count = 9;
 496
 497       DBG("I830_UPLOAD_BUFFERS:\n");
 498
 499       if (state->depth_region)
 500           count += 3;
 501
 502       if (intel->constant_cliprect)
 503           count += 6;
 504
 505       BEGIN_BATCH(count, IGNORE_CLIPRECTS);
 506       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
 507       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
 508       OUT_RELOC(state->draw_region->buffer,
 509                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 510                 state->draw_region->draw_offset);
 511
 512       if (state->depth_region) {
 513          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
 514          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
 515          OUT_RELOC(state->depth_region->buffer,
 516                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 517                    state->depth_region->draw_offset);
 518       }
 519
 520       OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
 521       OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
 522       OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
 523       OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
 524       OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
 525       OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
 526
 527       if (intel->constant_cliprect) {
 528          assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
 529          OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
 530          OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
 531          OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
 532          OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
 533          OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
 534          OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
 535       }
 536       ADVANCE_BATCH();
 537    }
 538
 539    if (dirty & I830_UPLOAD_STIPPLE) {
 540       DBG("I830_UPLOAD_STIPPLE:\n");
 541       emit(intel, state->Stipple, sizeof(state->Stipple));
 542    }
 543
 544    for (i = 0; i < I830_TEX_UNITS; i++) {
 545       if ((dirty & I830_UPLOAD_TEX(i))) {
 546          DBG("I830_UPLOAD_TEX(%d):\n", i);
 547
 548          BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, IGNORE_CLIPRECTS);
 549          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
 550
 551          if (state->tex_buffer[i]) {
 552             OUT_RELOC(state->tex_buffer[i],
 553                       I915_GEM_DOMAIN_SAMPLER, 0,
 554                       state->tex_offset[i]);
 555          }
 556          else if (state == &i830->meta) {
 557             assert(i == 0);
 558             OUT_BATCH(0);
 559          }
 560          else {
 561             OUT_BATCH(state->tex_offset[i]);
 562          }
 563
 564          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]);
 565          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]);
 566          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]);
 567          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]);
 568          OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]);
 569          OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]);
 570
 571          ADVANCE_BATCH();
 572       }
 573
 574       if (dirty & I830_UPLOAD_TEXBLEND(i)) {
 575          DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
 576              state->TexBlendWordsUsed[i]);
 577          emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
 578       }
 579    }
 580
 581    intel->batch->dirty_state &= ~dirty;
 582    assert(get_dirty(state) == 0);
 583    assert((intel->batch->dirty_state & (1<<1)) == 0);
 584 }
 585
 586 static void
 587 i830_destroy_context(struct intel_context *intel)
 588 {
 589    GLuint i;
 590    struct i830_context *i830 = i830_context(&intel->ctx);
 591
 592    intel_region_release(&i830->state.draw_region);
 593    intel_region_release(&i830->state.depth_region);
 594    intel_region_release(&i830->meta.draw_region);
 595    intel_region_release(&i830->meta.depth_region);
 596    intel_region_release(&i830->initial.draw_region);
 597    intel_region_release(&i830->initial.depth_region);
 598
 599    for (i = 0; i < I830_TEX_UNITS; i++) {
 600       if (i830->state.tex_buffer[i] != NULL) {
 601          dri_bo_unreference(i830->state.tex_buffer[i]);
 602          i830->state.tex_buffer[i] = NULL;
 603       }
 604    }
 605
 606    _tnl_free_vertices(&intel->ctx);
 607 }
 608
 609
 610 void
 611 i830_state_draw_region(struct intel_context *intel,
 612                        struct i830_hw_state *state,
 613                        struct intel_region *color_region,
 614                        struct intel_region *depth_region)
 615 {
 616    struct i830_context *i830 = i830_context(&intel->ctx);
 617    GLcontext *ctx = &intel->ctx;
 618    struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
 619    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 620    GLuint value;
 621
 622    ASSERT(state == &i830->state || state == &i830->meta);
 623
 624    if (state->draw_region != color_region) {
 625       intel_region_release(&state->draw_region);
 626       intel_region_reference(&state->draw_region, color_region);
 627    }
 628    if (state->depth_region != depth_region) {
 629       intel_region_release(&state->depth_region);
 630       intel_region_reference(&state->depth_region, depth_region);
 631    }
 632
 633    /*
 634     * Set stride/cpp values
 635     */
 636    i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_CBUFADDR0],
 637                                 color_region, BUF_3D_ID_COLOR_BACK);
 638
 639    i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_DBUFADDR0],
 640                                 depth_region, BUF_3D_ID_DEPTH);
 641
 642    /*
 643     * Compute/set I830_DESTREG_DV1 value
 644     */
 645    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 646             DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z);    /* .5 */
 647
 648    if (irb != NULL) {
 649       switch (irb->texformat->MesaFormat) {
 650       case MESA_FORMAT_ARGB8888:
 651          value |= DV_PF_8888;
 652          break;
 653       case MESA_FORMAT_RGB565:
 654          value |= DV_PF_565;
 655          break;
 656       case MESA_FORMAT_ARGB1555:
 657          value |= DV_PF_1555;
 658          break;
 659       case MESA_FORMAT_ARGB4444:
 660          value |= DV_PF_4444;
 661          break;
 662       default:
 663          _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
 664                        irb->texformat->MesaFormat);
 665       }
 666    }
 667
 668    if (depth_region && depth_region->cpp == 4) {
 669       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 670    }
 671    else {
 672       value |= DEPTH_FRMT_16_FIXED;
 673    }
 674    state->Buffer[I830_DESTREG_DV1] = value;
 675
 676    if (intel->constant_cliprect) {
 677       state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
 678       state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
 679       state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
 680       state->Buffer[I830_DESTREG_DRAWRECT3] =
 681          (ctx->DrawBuffer->Width & 0xffff) |
 682          (ctx->DrawBuffer->Height << 16);
 683       state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
 684       state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
 685    } else {
 686       state->Buffer[I830_DESTREG_DRAWRECT0] = MI_NOOP;
 687       state->Buffer[I830_DESTREG_DRAWRECT1] = MI_NOOP;
 688       state->Buffer[I830_DESTREG_DRAWRECT2] = MI_NOOP;
 689       state->Buffer[I830_DESTREG_DRAWRECT3] = MI_NOOP;
 690       state->Buffer[I830_DESTREG_DRAWRECT4] = MI_NOOP;
 691       state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
 692    }
 693
 694    I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
 695
 696
 697 }
 698
 699
 700 static void
 701 i830_set_draw_region(struct intel_context *intel,
 702                      struct intel_region *color_regions[],
 703                      struct intel_region *depth_region,
 704                      GLuint num_regions)
 705 {
 706    struct i830_context *i830 = i830_context(&intel->ctx);
 707    i830_state_draw_region(intel, &i830->state, color_regions[0], depth_region);
 708 }
 709
 710 /* This isn't really handled at the moment.
 711  */
 712 static void
 713 i830_new_batch(struct intel_context *intel)
 714 {
 715    struct i830_context *i830 = i830_context(&intel->ctx);
 716    i830->state.emitted = 0;
 717
 718    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 719    assert(!intel->no_batch_wrap);
 720 }
 721
 722
 723
 724 static GLuint
 725 i830_flush_cmd(void)
 726 {
 727    return MI_FLUSH | FLUSH_MAP_CACHE;
 728 }
 729
 730
 731 static void
 732 i830_assert_not_dirty( struct intel_context *intel )
 733 {
 734    struct i830_context *i830 = i830_context(&intel->ctx);
 735    struct i830_hw_state *state = i830->current;
 736    assert(!get_dirty(state));
 737 }
 738
 739 static void
 740 i830_invalidate_state(struct intel_context *intel, GLuint new_state)
 741 {
 742    if (new_state & _NEW_LIGHT)
 743       i830_update_provoking_vertex(&intel->ctx);
 744 }
 745
 746 void
 747 i830InitVtbl(struct i830_context *i830)
 748 {
 749    i830->intel.vtbl.check_vertex_size = i830_check_vertex_size;
 750    i830->intel.vtbl.destroy = i830_destroy_context;
 751    i830->intel.vtbl.emit_state = i830_emit_state;
 752    i830->intel.vtbl.new_batch = i830_new_batch;
 753    i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state;
 754    i830->intel.vtbl.set_draw_region = i830_set_draw_region;
 755    i830->intel.vtbl.update_texture_state = i830UpdateTextureState;
 756    i830->intel.vtbl.flush_cmd = i830_flush_cmd;
 757    i830->intel.vtbl.render_start = i830_render_start;
 758    i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
 759    i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
 760    i830->intel.vtbl.finish_batch = intel_finish_vb;
 761    i830->intel.vtbl.invalidate_state = i830_invalidate_state;
 762 }