src/mesa/drivers/dri/i915/i830_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "i830_context.h"
  30 #include "i830_reg.h"
  31 #include "intel_batchbuffer.h"
  32 #include "intel_regions.h"
  33 #include "tnl/t_context.h"
  34 #include "tnl/t_vertex.h"
  35
  36 #define FILE_DEBUG_FLAG DEBUG_STATE
  37
  38 static GLboolean i830_check_vertex_size(struct intel_context *intel,
  39                                         GLuint expected);
  40
  41 #define SZ_TO_HW(sz)  ((sz-2)&0x3)
  42 #define EMIT_SZ(sz)   (EMIT_1F + (sz) - 1)
  43 #define EMIT_ATTR( ATTR, STYLE, V0 )                                    \
  44 do {                                                                    \
  45    intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR);       \
  46    intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE);      \
  47    intel->vertex_attr_count++;                                          \
  48    v0 |= V0;                                                            \
  49 } while (0)
  50
  51 #define EMIT_PAD( N )                                                   \
  52 do {                                                                    \
  53    intel->vertex_attrs[intel->vertex_attr_count].attrib = 0;            \
  54    intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD;     \
  55    intel->vertex_attrs[intel->vertex_attr_count].offset = (N);          \
  56    intel->vertex_attr_count++;                                          \
  57 } while (0)
  58
  59
  60 #define VRTX_TEX_SET_FMT(n, x)          ((x)<<((n)*2))
  61 #define TEXBIND_SET(n, x)               ((x)<<((n)*4))
  62
  63 static void
  64 i830_render_prevalidate(struct intel_context *intel)
  65 {
  66 }
  67
  68 static void
  69 i830_render_start(struct intel_context *intel)
  70 {
  71    GLcontext *ctx = &intel->ctx;
  72    struct i830_context *i830 = i830_context(ctx);
  73    TNLcontext *tnl = TNL_CONTEXT(ctx);
  74    struct vertex_buffer *VB = &tnl->vb;
  75    DECLARE_RENDERINPUTS(index_bitset);
  76    GLuint v0 = _3DSTATE_VFT0_CMD;
  77    GLuint v2 = _3DSTATE_VFT1_CMD;
  78    GLuint mcsb1 = 0;
  79
  80    RENDERINPUTS_COPY(index_bitset, tnl->render_inputs_bitset);
  81
  82    /* Important:
  83     */
  84    VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
  85    intel->vertex_attr_count = 0;
  86
  87    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
  88     * build up a hardware vertex.
  89     */
  90    if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
  91       EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW);
  92       intel->coloroffset = 4;
  93    }
  94    else {
  95       EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ);
  96       intel->coloroffset = 3;
  97    }
  98
  99    if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_POINTSIZE)) {
 100       EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH);
 101    }
 102
 103    EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE);
 104
 105    intel->specoffset = 0;
 106    if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1) ||
 107        RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) {
 108       if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1)) {
 109          intel->specoffset = intel->coloroffset + 1;
 110          EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC);
 111       }
 112       else
 113          EMIT_PAD(3);
 114
 115       if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG))
 116          EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC);
 117       else
 118          EMIT_PAD(1);
 119    }
 120
 121    if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
 122       int i, count = 0;
 123
 124       for (i = 0; i < I830_TEX_UNITS; i++) {
 125          if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) {
 126             GLuint sz = VB->TexCoordPtr[i]->size;
 127             GLuint emit;
 128             GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
 129                           ~TEXCOORDTYPE_MASK);
 130
 131             switch (sz) {
 132             case 1:
 133             case 2:
 134                emit = EMIT_2F;
 135                sz = 2;
 136                mcs |= TEXCOORDTYPE_CARTESIAN;
 137                break;
 138             case 3:
 139                emit = EMIT_3F;
 140                sz = 3;
 141                mcs |= TEXCOORDTYPE_VECTOR;
 142                break;
 143             case 4:
 144                emit = EMIT_3F_XYW;
 145                sz = 3;
 146                mcs |= TEXCOORDTYPE_HOMOGENEOUS;
 147                break;
 148             default:
 149                continue;
 150             };
 151
 152
 153             EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
 154             v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
 155             mcsb1 |= (count + 8) << (i * 4);
 156
 157             if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) {
 158                I830_STATECHANGE(i830, I830_UPLOAD_TEX(i));
 159                i830->state.Tex[i][I830_TEXREG_MCS] = mcs;
 160             }
 161
 162             count++;
 163          }
 164       }
 165
 166       v0 |= VFT0_TEX_COUNT(count);
 167    }
 168
 169    /* Only need to change the vertex emit code if there has been a
 170     * statechange to a new hardware vertex format:
 171     */
 172    if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
 173        v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
 174        mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
 175        !RENDERINPUTS_EQUAL(index_bitset, i830->last_index_bitset)) {
 176       int k;
 177
 178       I830_STATECHANGE(i830, I830_UPLOAD_CTX);
 179
 180       /* Must do this *after* statechange, so as not to affect
 181        * buffered vertices reliant on the old state:
 182        */
 183       intel->vertex_size =
 184          _tnl_install_attrs(ctx,
 185                             intel->vertex_attrs,
 186                             intel->vertex_attr_count,
 187                             intel->ViewportMatrix.m, 0);
 188
 189       intel->vertex_size >>= 2;
 190
 191       i830->state.Ctx[I830_CTXREG_VF] = v0;
 192       i830->state.Ctx[I830_CTXREG_VF2] = v2;
 193       i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
 194       RENDERINPUTS_COPY(i830->last_index_bitset, index_bitset);
 195
 196       k = i830_check_vertex_size(intel, intel->vertex_size);
 197       assert(k);
 198    }
 199 }
 200
 201 static void
 202 i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
 203 {
 204    struct i830_context *i830 = i830_context(&intel->ctx);
 205    GLuint st1 = i830->state.Stipple[I830_STPREG_ST1];
 206
 207    st1 &= ~ST1_ENABLE;
 208
 209    switch (rprim) {
 210    case GL_TRIANGLES:
 211       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
 212          st1 |= ST1_ENABLE;
 213       break;
 214    case GL_LINES:
 215    case GL_POINTS:
 216    default:
 217       break;
 218    }
 219
 220    i830->intel.reduced_primitive = rprim;
 221
 222    if (st1 != i830->state.Stipple[I830_STPREG_ST1]) {
 223       INTEL_FIREVERTICES(intel);
 224
 225       I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
 226       i830->state.Stipple[I830_STPREG_ST1] = st1;
 227    }
 228 }
 229
 230 /* Pull apart the vertex format registers and figure out how large a
 231  * vertex is supposed to be.
 232  */
 233 static GLboolean
 234 i830_check_vertex_size(struct intel_context *intel, GLuint expected)
 235 {
 236    struct i830_context *i830 = i830_context(&intel->ctx);
 237    int vft0 = i830->current->Ctx[I830_CTXREG_VF];
 238    int vft1 = i830->current->Ctx[I830_CTXREG_VF2];
 239    int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT;
 240    int i, sz = 0;
 241
 242    switch (vft0 & VFT0_XYZW_MASK) {
 243    case VFT0_XY:
 244       sz = 2;
 245       break;
 246    case VFT0_XYZ:
 247       sz = 3;
 248       break;
 249    case VFT0_XYW:
 250       sz = 3;
 251       break;
 252    case VFT0_XYZW:
 253       sz = 4;
 254       break;
 255    default:
 256       fprintf(stderr, "no xyzw specified\n");
 257       return 0;
 258    }
 259
 260    if (vft0 & VFT0_SPEC)
 261       sz++;
 262    if (vft0 & VFT0_DIFFUSE)
 263       sz++;
 264    if (vft0 & VFT0_DEPTH_OFFSET)
 265       sz++;
 266    if (vft0 & VFT0_POINT_WIDTH)
 267       sz++;
 268
 269    for (i = 0; i < nrtex; i++) {
 270       switch (vft1 & VFT1_TEX0_MASK) {
 271       case TEXCOORDFMT_2D:
 272          sz += 2;
 273          break;
 274       case TEXCOORDFMT_3D:
 275          sz += 3;
 276          break;
 277       case TEXCOORDFMT_4D:
 278          sz += 4;
 279          break;
 280       case TEXCOORDFMT_1D:
 281          sz += 1;
 282          break;
 283       }
 284       vft1 >>= VFT1_TEX1_SHIFT;
 285    }
 286
 287    if (sz != expected)
 288       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 289
 290    return sz == expected;
 291 }
 292
 293 static void
 294 i830_emit_invarient_state(struct intel_context *intel)
 295 {
 296    BATCH_LOCALS;
 297
 298    BEGIN_BATCH(40, 0);
 299
 300    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 301    OUT_BATCH(0);
 302
 303    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 304    OUT_BATCH(0);
 305
 306    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 307    OUT_BATCH(0);
 308
 309    OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
 310    OUT_BATCH(FOGFUNC_ENABLE |
 311              FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
 312    OUT_BATCH(0);
 313    OUT_BATCH(0);
 314
 315
 316    OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 317              MAP_UNIT(0) |
 318              DISABLE_TEX_STREAM_BUMP |
 319              ENABLE_TEX_STREAM_COORD_SET |
 320              TEX_STREAM_COORD_SET(0) |
 321              ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
 322    OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 323              MAP_UNIT(1) |
 324              DISABLE_TEX_STREAM_BUMP |
 325              ENABLE_TEX_STREAM_COORD_SET |
 326              TEX_STREAM_COORD_SET(1) |
 327              ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
 328    OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 329              MAP_UNIT(2) |
 330              DISABLE_TEX_STREAM_BUMP |
 331              ENABLE_TEX_STREAM_COORD_SET |
 332              TEX_STREAM_COORD_SET(2) |
 333              ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
 334    OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
 335              MAP_UNIT(3) |
 336              DISABLE_TEX_STREAM_BUMP |
 337              ENABLE_TEX_STREAM_COORD_SET |
 338              TEX_STREAM_COORD_SET(3) |
 339              ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
 340
 341    OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
 342    OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
 343    OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
 344    OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
 345    OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
 346    OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
 347    OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
 348    OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
 349
 350    OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 351              ENABLE_POINT_RASTER_RULE |
 352              OGL_POINT_RASTER_RULE |
 353              ENABLE_LINE_STRIP_PROVOKE_VRTX |
 354              ENABLE_TRI_FAN_PROVOKE_VRTX |
 355              ENABLE_TRI_STRIP_PROVOKE_VRTX |
 356              LINE_STRIP_PROVOKE_VRTX(1) |
 357              TRI_FAN_PROVOKE_VRTX(2) | TRI_STRIP_PROVOKE_VRTX(2));
 358
 359    OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
 360    OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
 361
 362    OUT_BATCH(_3DSTATE_W_STATE_CMD);
 363    OUT_BATCH(MAGIC_W_STATE_DWORD1);
 364    OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
 365
 366
 367    OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
 368    OUT_BATCH(0x80808080);       /* .5 required in alpha for GL_DOT3_RGBA_EXT */
 369
 370    ADVANCE_BATCH();
 371 }
 372
 373
 374 #define emit( intel, state, size )                      \
 375 do {                                                    \
 376    int k;                                               \
 377    BEGIN_BATCH(size / sizeof(GLuint), 0);               \
 378    for (k = 0 ; k < size / sizeof(GLuint) ; k++) {      \
 379       if (0) _mesa_printf("  0x%08x\n", state[k]);              \
 380       OUT_BATCH(state[k]);                              \
 381    }                                                    \
 382    ADVANCE_BATCH();                                     \
 383 } while (0)
 384
 385 static GLuint
 386 get_dirty(struct i830_hw_state *state)
 387 {
 388    return state->active & ~state->emitted;
 389 }
 390
 391 static GLuint
 392 get_state_size(struct i830_hw_state *state)
 393 {
 394    GLuint dirty = get_dirty(state);
 395    GLuint sz = 0;
 396    GLuint i;
 397
 398    if (dirty & I830_UPLOAD_INVARIENT)
 399       sz += 40 * sizeof(int);
 400
 401    if (dirty & I830_UPLOAD_CTX)
 402       sz += sizeof(state->Ctx);
 403
 404    if (dirty & I830_UPLOAD_BUFFERS)
 405       sz += sizeof(state->Buffer);
 406
 407    if (dirty & I830_UPLOAD_STIPPLE)
 408       sz += sizeof(state->Stipple);
 409
 410    for (i = 0; i < I830_TEX_UNITS; i++) {
 411       if ((dirty & I830_UPLOAD_TEX(i)))
 412          sz += sizeof(state->Tex[i]);
 413
 414       if (dirty & I830_UPLOAD_TEXBLEND(i))
 415          sz += state->TexBlendWordsUsed[i] * 4;
 416    }
 417
 418    return sz;
 419 }
 420
 421
 422 /* Push the state into the sarea and/or texture memory.
 423  */
 424 static void
 425 i830_do_emit_state(struct intel_context *intel)
 426 {
 427    struct i830_context *i830 = i830_context(&intel->ctx);
 428    struct i830_hw_state *state = i830->current;
 429    int i;
 430    GLuint dirty;
 431    BATCH_LOCALS;
 432
 433    /* We don't hold the lock at this point, so want to make sure that
 434     * there won't be a buffer wrap.
 435     *
 436     * It might be better to talk about explicit places where
 437     * scheduling is allowed, rather than assume that it is whenever a
 438     * batchbuffer fills up.
 439     */
 440    intel_batchbuffer_require_space(intel->batch, get_state_size(state), 0);
 441
 442    /* Workaround.  There are cases I haven't been able to track down
 443     * where we aren't emitting a full state at the start of a new
 444     * batchbuffer.  This code spots that we are on a new batchbuffer
 445     * and forces a full state emit no matter what.
 446     *
 447     * In the normal case state->emitted is already zero, this code is
 448     * another set of checks to make sure it really is.
 449     */
 450    if (intel->batch->id != intel->last_state_batch_id ||
 451        intel->batch->map == intel->batch->ptr)
 452    {
 453       state->emitted = 0;
 454       intel_batchbuffer_require_space(intel->batch, get_state_size(state), 0);
 455    }
 456
 457    /* Do this here as we may have flushed the batchbuffer above,
 458     * causing more state to be dirty!
 459     */
 460    dirty = get_dirty(state);
 461    state->emitted |= dirty;
 462    assert(get_dirty(state) == 0);
 463
 464    if (intel->batch->id != intel->last_state_batch_id) {
 465       assert(dirty & I830_UPLOAD_CTX);
 466       intel->last_state_batch_id = intel->batch->id;
 467    }
 468
 469    if (dirty & I830_UPLOAD_INVARIENT) {
 470       DBG("I830_UPLOAD_INVARIENT:\n");
 471       i830_emit_invarient_state(intel);
 472    }
 473
 474    if (dirty & I830_UPLOAD_CTX) {
 475       DBG("I830_UPLOAD_CTX:\n");
 476       emit(i830, state->Ctx, sizeof(state->Ctx));
 477
 478    }
 479
 480    if (dirty & I830_UPLOAD_BUFFERS) {
 481       DBG("I830_UPLOAD_BUFFERS:\n");
 482       BEGIN_BATCH(I830_DEST_SETUP_SIZE + 2, 0);
 483       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
 484       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
 485       OUT_RELOC(state->draw_region->buffer,
 486                 DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
 487                 state->draw_region->draw_offset);
 488
 489       if (state->depth_region) {
 490          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
 491          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
 492          OUT_RELOC(state->depth_region->buffer,
 493                    DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
 494                    state->depth_region->draw_offset);
 495       }
 496
 497       OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
 498       OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
 499       OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
 500       OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
 501       OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
 502       OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
 503       ADVANCE_BATCH();
 504    }
 505
 506    if (dirty & I830_UPLOAD_STIPPLE) {
 507       DBG("I830_UPLOAD_STIPPLE:\n");
 508       emit(i830, state->Stipple, sizeof(state->Stipple));
 509    }
 510
 511    for (i = 0; i < I830_TEX_UNITS; i++) {
 512       if ((dirty & I830_UPLOAD_TEX(i))) {
 513          DBG("I830_UPLOAD_TEX(%d):\n", i);
 514
 515          BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, 0);
 516          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
 517
 518          if (state->tex_buffer[i]) {
 519             OUT_RELOC(state->tex_buffer[i],
 520                       DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
 521                       state->tex_offset[i] | TM0S0_USE_FENCE);
 522          }
 523          else if (state == &i830->meta) {
 524             assert(i == 0);
 525             OUT_BATCH(0);
 526          }
 527          else {
 528             OUT_BATCH(state->tex_offset[i]);
 529          }
 530
 531          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]);
 532          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]);
 533          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]);
 534          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]);
 535          OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]);
 536          OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]);
 537       }
 538
 539       if (dirty & I830_UPLOAD_TEXBLEND(i)) {
 540          DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
 541              state->TexBlendWordsUsed[i]);
 542          emit(i830, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
 543       }
 544    }
 545
 546    intel->batch->dirty_state &= ~dirty;
 547    assert(get_dirty(state) == 0);
 548 }
 549
 550 static void
 551 i830_emit_state(struct intel_context *intel)
 552 {
 553    struct i830_context *i830 = i830_context(&intel->ctx);
 554
 555    i830_do_emit_state( intel );
 556
 557    /* Second chance - catch batchbuffer wrap in the middle of state
 558     * emit.  This shouldn't happen but it has been observed in
 559     * testing.
 560     */
 561    if (get_dirty( i830->current )) {
 562       /* Force a full re-emit if this happens.
 563        */
 564       i830->current->emitted = 0;
 565       i830_do_emit_state( intel );
 566    }
 567
 568    assert(get_dirty(i830->current) == 0);
 569    assert((intel->batch->dirty_state & (1<<1)) == 0);
 570 }
 571
 572 static void
 573 i830_destroy_context(struct intel_context *intel)
 574 {
 575    GLuint i;
 576    struct i830_context *i830 = i830_context(&intel->ctx);
 577
 578    for (i = 0; i < I830_TEX_UNITS; i++) {
 579       if (i830->state.tex_buffer[i] != NULL) {
 580          dri_bo_unreference(i830->state.tex_buffer[i]);
 581          i830->state.tex_buffer[i] = NULL;
 582       }
 583    }
 584
 585    _tnl_free_vertices(&intel->ctx);
 586 }
 587
 588
 589 void
 590 i830_state_draw_region(struct intel_context *intel,
 591                        struct i830_hw_state *state,
 592                        struct intel_region *color_region,
 593                        struct intel_region *depth_region)
 594 {
 595    struct i830_context *i830 = i830_context(&intel->ctx);
 596    GLuint value;
 597
 598    ASSERT(state == &i830->state || state == &i830->meta);
 599
 600    if (state->draw_region != color_region) {
 601       intel_region_release(&state->draw_region);
 602       intel_region_reference(&state->draw_region, color_region);
 603    }
 604    if (state->depth_region != depth_region) {
 605       intel_region_release(&state->depth_region);
 606       intel_region_reference(&state->depth_region, depth_region);
 607    }
 608
 609    /*
 610     * Set stride/cpp values
 611     */
 612    if (color_region) {
 613       state->Buffer[I830_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 614       state->Buffer[I830_DESTREG_CBUFADDR1] =
 615          (BUF_3D_ID_COLOR_BACK |
 616           BUF_3D_PITCH(color_region->pitch * color_region->cpp) |
 617           BUF_3D_USE_FENCE);
 618    }
 619
 620    if (depth_region) {
 621       state->Buffer[I830_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 622       state->Buffer[I830_DESTREG_DBUFADDR1] =
 623          (BUF_3D_ID_DEPTH |
 624           BUF_3D_PITCH(depth_region->pitch * depth_region->cpp) |
 625           BUF_3D_USE_FENCE);
 626    }
 627
 628    /*
 629     * Compute/set I830_DESTREG_DV1 value
 630     */
 631    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 632             DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z);    /* .5 */
 633
 634    if (color_region && color_region->cpp == 4) {
 635       value |= DV_PF_8888;
 636    }
 637    else {
 638       value |= DV_PF_565;
 639    }
 640    if (depth_region && depth_region->cpp == 4) {
 641       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 642    }
 643    else {
 644       value |= DEPTH_FRMT_16_FIXED;
 645    }
 646    state->Buffer[I830_DESTREG_DV1] = value;
 647
 648    I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
 649
 650
 651 }
 652
 653
 654 static void
 655 i830_set_draw_region(struct intel_context *intel,
 656                      struct intel_region *color_region,
 657                      struct intel_region *depth_region)
 658 {
 659    struct i830_context *i830 = i830_context(&intel->ctx);
 660    i830_state_draw_region(intel, &i830->state, color_region, depth_region);
 661 }
 662
 663 #if 0
 664 static void
 665 i830_update_color_z_regions(intelContextPtr intel,
 666                             const intelRegion * colorRegion,
 667                             const intelRegion * depthRegion)
 668 {
 669    i830ContextPtr i830 = I830_CONTEXT(intel);
 670
 671    i830->state.Buffer[I830_DESTREG_CBUFADDR1] =
 672       (BUF_3D_ID_COLOR_BACK | BUF_3D_PITCH(colorRegion->pitch) |
 673        BUF_3D_USE_FENCE);
 674    i830->state.Buffer[I830_DESTREG_CBUFADDR2] = colorRegion->offset;
 675
 676    i830->state.Buffer[I830_DESTREG_DBUFADDR1] =
 677       (BUF_3D_ID_DEPTH | BUF_3D_PITCH(depthRegion->pitch) | BUF_3D_USE_FENCE);
 678    i830->state.Buffer[I830_DESTREG_DBUFADDR2] = depthRegion->offset;
 679 }
 680 #endif
 681
 682
 683 /* This isn't really handled at the moment.
 684  */
 685 static void
 686 i830_lost_hardware(struct intel_context *intel)
 687 {
 688    struct i830_context *i830 = i830_context(&intel->ctx);
 689    i830->state.emitted = 0;
 690 }
 691
 692
 693
 694 static GLuint
 695 i830_flush_cmd(void)
 696 {
 697    return MI_FLUSH | FLUSH_MAP_CACHE;
 698 }
 699
 700
 701 static void
 702 i830_assert_not_dirty( struct intel_context *intel )
 703 {
 704    struct i830_context *i830 = i830_context(&intel->ctx);
 705    struct i830_hw_state *state = i830->current;
 706    assert(!get_dirty(state));
 707 }
 708
 709
 710 void
 711 i830InitVtbl(struct i830_context *i830)
 712 {
 713    i830->intel.vtbl.check_vertex_size = i830_check_vertex_size;
 714    i830->intel.vtbl.destroy = i830_destroy_context;
 715    i830->intel.vtbl.emit_state = i830_emit_state;
 716    i830->intel.vtbl.lost_hardware = i830_lost_hardware;
 717    i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state;
 718    i830->intel.vtbl.set_draw_region = i830_set_draw_region;
 719    i830->intel.vtbl.update_texture_state = i830UpdateTextureState;
 720    i830->intel.vtbl.flush_cmd = i830_flush_cmd;
 721    i830->intel.vtbl.render_start = i830_render_start;
 722    i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
 723    i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
 724 }