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c5a85fe03527f4f642dea0506c422e944999abb2
[mesa.git] / src / mesa / drivers / dri / i915 / i830_vtbl.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "glapi.h"
29
30 #include "i830_context.h"
31 #include "i830_reg.h"
32 #include "intel_batchbuffer.h"
33 #include "intel_regions.h"
34 #include "tnl/t_context.h"
35 #include "tnl/t_vertex.h"
36
37 #define FILE_DEBUG_FLAG DEBUG_STATE
38
39 static GLboolean i830_check_vertex_size(struct intel_context *intel,
40 GLuint expected);
41
42 #define SZ_TO_HW(sz) ((sz-2)&0x3)
43 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
44 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
45 do { \
46 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
47 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
48 intel->vertex_attr_count++; \
49 v0 |= V0; \
50 } while (0)
51
52 #define EMIT_PAD( N ) \
53 do { \
54 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
55 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
56 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
57 intel->vertex_attr_count++; \
58 } while (0)
59
60
61 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
62 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
63
64 static void
65 i830_render_prevalidate(struct intel_context *intel)
66 {
67 }
68
69 static void
70 i830_render_start(struct intel_context *intel)
71 {
72 GLcontext *ctx = &intel->ctx;
73 struct i830_context *i830 = i830_context(ctx);
74 TNLcontext *tnl = TNL_CONTEXT(ctx);
75 struct vertex_buffer *VB = &tnl->vb;
76 DECLARE_RENDERINPUTS(index_bitset);
77 GLuint v0 = _3DSTATE_VFT0_CMD;
78 GLuint v2 = _3DSTATE_VFT1_CMD;
79 GLuint mcsb1 = 0;
80
81 RENDERINPUTS_COPY(index_bitset, tnl->render_inputs_bitset);
82
83 /* Important:
84 */
85 VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
86 intel->vertex_attr_count = 0;
87
88 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
89 * build up a hardware vertex.
90 */
91 if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
92 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW);
93 intel->coloroffset = 4;
94 }
95 else {
96 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ);
97 intel->coloroffset = 3;
98 }
99
100 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_POINTSIZE)) {
101 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH);
102 }
103
104 EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE);
105
106 intel->specoffset = 0;
107 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1) ||
108 RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) {
109 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1)) {
110 intel->specoffset = intel->coloroffset + 1;
111 EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC);
112 }
113 else
114 EMIT_PAD(3);
115
116 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG))
117 EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC);
118 else
119 EMIT_PAD(1);
120 }
121
122 if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
123 int i, count = 0;
124
125 for (i = 0; i < I830_TEX_UNITS; i++) {
126 if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) {
127 GLuint sz = VB->TexCoordPtr[i]->size;
128 GLuint emit;
129 GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
130 ~TEXCOORDTYPE_MASK);
131
132 switch (sz) {
133 case 1:
134 case 2:
135 emit = EMIT_2F;
136 sz = 2;
137 mcs |= TEXCOORDTYPE_CARTESIAN;
138 break;
139 case 3:
140 emit = EMIT_3F;
141 sz = 3;
142 mcs |= TEXCOORDTYPE_VECTOR;
143 break;
144 case 4:
145 emit = EMIT_3F_XYW;
146 sz = 3;
147 mcs |= TEXCOORDTYPE_HOMOGENEOUS;
148 break;
149 default:
150 continue;
151 };
152
153
154 EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
155 v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
156 mcsb1 |= (count + 8) << (i * 4);
157
158 if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) {
159 I830_STATECHANGE(i830, I830_UPLOAD_TEX(i));
160 i830->state.Tex[i][I830_TEXREG_MCS] = mcs;
161 }
162
163 count++;
164 }
165 }
166
167 v0 |= VFT0_TEX_COUNT(count);
168 }
169
170 /* Only need to change the vertex emit code if there has been a
171 * statechange to a new hardware vertex format:
172 */
173 if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
174 v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
175 mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
176 !RENDERINPUTS_EQUAL(index_bitset, i830->last_index_bitset)) {
177 int k;
178
179 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
180
181 /* Must do this *after* statechange, so as not to affect
182 * buffered vertices reliant on the old state:
183 */
184 intel->vertex_size =
185 _tnl_install_attrs(ctx,
186 intel->vertex_attrs,
187 intel->vertex_attr_count,
188 intel->ViewportMatrix.m, 0);
189
190 intel->vertex_size >>= 2;
191
192 i830->state.Ctx[I830_CTXREG_VF] = v0;
193 i830->state.Ctx[I830_CTXREG_VF2] = v2;
194 i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
195 RENDERINPUTS_COPY(i830->last_index_bitset, index_bitset);
196
197 k = i830_check_vertex_size(intel, intel->vertex_size);
198 assert(k);
199 }
200 }
201
202 static void
203 i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
204 {
205 struct i830_context *i830 = i830_context(&intel->ctx);
206 GLuint st1 = i830->state.Stipple[I830_STPREG_ST1];
207
208 st1 &= ~ST1_ENABLE;
209
210 switch (rprim) {
211 case GL_TRIANGLES:
212 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
213 st1 |= ST1_ENABLE;
214 break;
215 case GL_LINES:
216 case GL_POINTS:
217 default:
218 break;
219 }
220
221 i830->intel.reduced_primitive = rprim;
222
223 if (st1 != i830->state.Stipple[I830_STPREG_ST1]) {
224 INTEL_FIREVERTICES(intel);
225
226 I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
227 i830->state.Stipple[I830_STPREG_ST1] = st1;
228 }
229 }
230
231 /* Pull apart the vertex format registers and figure out how large a
232 * vertex is supposed to be.
233 */
234 static GLboolean
235 i830_check_vertex_size(struct intel_context *intel, GLuint expected)
236 {
237 struct i830_context *i830 = i830_context(&intel->ctx);
238 int vft0 = i830->current->Ctx[I830_CTXREG_VF];
239 int vft1 = i830->current->Ctx[I830_CTXREG_VF2];
240 int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT;
241 int i, sz = 0;
242
243 switch (vft0 & VFT0_XYZW_MASK) {
244 case VFT0_XY:
245 sz = 2;
246 break;
247 case VFT0_XYZ:
248 sz = 3;
249 break;
250 case VFT0_XYW:
251 sz = 3;
252 break;
253 case VFT0_XYZW:
254 sz = 4;
255 break;
256 default:
257 fprintf(stderr, "no xyzw specified\n");
258 return 0;
259 }
260
261 if (vft0 & VFT0_SPEC)
262 sz++;
263 if (vft0 & VFT0_DIFFUSE)
264 sz++;
265 if (vft0 & VFT0_DEPTH_OFFSET)
266 sz++;
267 if (vft0 & VFT0_POINT_WIDTH)
268 sz++;
269
270 for (i = 0; i < nrtex; i++) {
271 switch (vft1 & VFT1_TEX0_MASK) {
272 case TEXCOORDFMT_2D:
273 sz += 2;
274 break;
275 case TEXCOORDFMT_3D:
276 sz += 3;
277 break;
278 case TEXCOORDFMT_4D:
279 sz += 4;
280 break;
281 case TEXCOORDFMT_1D:
282 sz += 1;
283 break;
284 }
285 vft1 >>= VFT1_TEX1_SHIFT;
286 }
287
288 if (sz != expected)
289 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
290
291 return sz == expected;
292 }
293
294 static void
295 i830_emit_invarient_state(struct intel_context *intel)
296 {
297 BATCH_LOCALS;
298
299 BEGIN_BATCH(40, IGNORE_CLIPRECTS);
300
301 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
302 OUT_BATCH(0);
303
304 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
305 OUT_BATCH(0);
306
307 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
308 OUT_BATCH(0);
309
310 OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
311 OUT_BATCH(FOGFUNC_ENABLE |
312 FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
313 OUT_BATCH(0);
314 OUT_BATCH(0);
315
316
317 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
318 MAP_UNIT(0) |
319 DISABLE_TEX_STREAM_BUMP |
320 ENABLE_TEX_STREAM_COORD_SET |
321 TEX_STREAM_COORD_SET(0) |
322 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
323 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
324 MAP_UNIT(1) |
325 DISABLE_TEX_STREAM_BUMP |
326 ENABLE_TEX_STREAM_COORD_SET |
327 TEX_STREAM_COORD_SET(1) |
328 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
329 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
330 MAP_UNIT(2) |
331 DISABLE_TEX_STREAM_BUMP |
332 ENABLE_TEX_STREAM_COORD_SET |
333 TEX_STREAM_COORD_SET(2) |
334 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
335 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
336 MAP_UNIT(3) |
337 DISABLE_TEX_STREAM_BUMP |
338 ENABLE_TEX_STREAM_COORD_SET |
339 TEX_STREAM_COORD_SET(3) |
340 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
341
342 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
343 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
344 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
345 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
346 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
347 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
348 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
349 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
350
351 OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
352 ENABLE_POINT_RASTER_RULE |
353 OGL_POINT_RASTER_RULE |
354 ENABLE_LINE_STRIP_PROVOKE_VRTX |
355 ENABLE_TRI_FAN_PROVOKE_VRTX |
356 ENABLE_TRI_STRIP_PROVOKE_VRTX |
357 LINE_STRIP_PROVOKE_VRTX(1) |
358 TRI_FAN_PROVOKE_VRTX(2) | TRI_STRIP_PROVOKE_VRTX(2));
359
360 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
361 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
362
363 OUT_BATCH(_3DSTATE_W_STATE_CMD);
364 OUT_BATCH(MAGIC_W_STATE_DWORD1);
365 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
366
367
368 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
369 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
370
371 ADVANCE_BATCH();
372 }
373
374
375 #define emit( intel, state, size ) \
376 intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
377
378 static GLuint
379 get_dirty(struct i830_hw_state *state)
380 {
381 return state->active & ~state->emitted;
382 }
383
384 static GLuint
385 get_state_size(struct i830_hw_state *state)
386 {
387 GLuint dirty = get_dirty(state);
388 GLuint sz = 0;
389 GLuint i;
390
391 if (dirty & I830_UPLOAD_INVARIENT)
392 sz += 40 * sizeof(int);
393
394 if (dirty & I830_UPLOAD_CTX)
395 sz += sizeof(state->Ctx);
396
397 if (dirty & I830_UPLOAD_BUFFERS)
398 sz += sizeof(state->Buffer);
399
400 if (dirty & I830_UPLOAD_STIPPLE)
401 sz += sizeof(state->Stipple);
402
403 for (i = 0; i < I830_TEX_UNITS; i++) {
404 if ((dirty & I830_UPLOAD_TEX(i)))
405 sz += sizeof(state->Tex[i]);
406
407 if (dirty & I830_UPLOAD_TEXBLEND(i))
408 sz += state->TexBlendWordsUsed[i] * 4;
409 }
410
411 return sz;
412 }
413
414
415 /* Push the state into the sarea and/or texture memory.
416 */
417 static void
418 i830_emit_state(struct intel_context *intel)
419 {
420 struct i830_context *i830 = i830_context(&intel->ctx);
421 struct i830_hw_state *state = i830->current;
422 int i, ret, count;
423 GLuint dirty;
424 GET_CURRENT_CONTEXT(ctx);
425 BATCH_LOCALS;
426
427 /* We don't hold the lock at this point, so want to make sure that
428 * there won't be a buffer wrap between the state emits and the primitive
429 * emit header.
430 *
431 * It might be better to talk about explicit places where
432 * scheduling is allowed, rather than assume that it is whenever a
433 * batchbuffer fills up.
434 *
435 * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
436 * will be emitted under.
437 */
438 intel_batchbuffer_require_space(intel->batch, get_state_size(state) + 8,
439 LOOP_CLIPRECTS);
440 count = 0;
441 again:
442 dirty = get_dirty(state);
443
444 ret = 0;
445 if (dirty & I830_UPLOAD_BUFFERS) {
446 ret |= dri_bufmgr_check_aperture_space(state->draw_region->buffer);
447 ret |= dri_bufmgr_check_aperture_space(state->depth_region->buffer);
448 }
449
450 for (i = 0; i < I830_TEX_UNITS; i++)
451 if (dirty & I830_UPLOAD_TEX(i)) {
452 if (state->tex_buffer[i]) {
453 ret |= dri_bufmgr_check_aperture_space(state->tex_buffer[i]);
454 }
455 }
456
457 if (ret) {
458 if (count == 0) {
459 count++;
460 intel_batchbuffer_flush(intel->batch);
461 goto again;
462 } else {
463 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state");
464 assert(0);
465 }
466 }
467
468
469 /* Do this here as we may have flushed the batchbuffer above,
470 * causing more state to be dirty!
471 */
472 dirty = get_dirty(state);
473 state->emitted |= dirty;
474 assert(get_dirty(state) == 0);
475
476 if (dirty & I830_UPLOAD_INVARIENT) {
477 DBG("I830_UPLOAD_INVARIENT:\n");
478 i830_emit_invarient_state(intel);
479 }
480
481 if (dirty & I830_UPLOAD_CTX) {
482 DBG("I830_UPLOAD_CTX:\n");
483 emit(intel, state->Ctx, sizeof(state->Ctx));
484
485 }
486
487 if (dirty & I830_UPLOAD_BUFFERS) {
488 DBG("I830_UPLOAD_BUFFERS:\n");
489 BEGIN_BATCH(I830_DEST_SETUP_SIZE + 2, IGNORE_CLIPRECTS);
490 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
491 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
492 OUT_RELOC(state->draw_region->buffer,
493 DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
494 state->draw_region->draw_offset);
495
496 if (state->depth_region) {
497 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
498 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
499 OUT_RELOC(state->depth_region->buffer,
500 DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
501 state->depth_region->draw_offset);
502 }
503
504 OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
505 OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
506 OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
507 OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
508 OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
509 OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
510 ADVANCE_BATCH();
511 }
512
513 if (dirty & I830_UPLOAD_STIPPLE) {
514 DBG("I830_UPLOAD_STIPPLE:\n");
515 emit(intel, state->Stipple, sizeof(state->Stipple));
516 }
517
518 for (i = 0; i < I830_TEX_UNITS; i++) {
519 if ((dirty & I830_UPLOAD_TEX(i))) {
520 DBG("I830_UPLOAD_TEX(%d):\n", i);
521
522 BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, IGNORE_CLIPRECTS);
523 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
524
525 if (state->tex_buffer[i]) {
526 OUT_RELOC(state->tex_buffer[i],
527 DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
528 state->tex_offset[i] | TM0S0_USE_FENCE);
529 }
530 else if (state == &i830->meta) {
531 assert(i == 0);
532 OUT_BATCH(0);
533 }
534 else {
535 OUT_BATCH(state->tex_offset[i]);
536 }
537
538 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]);
539 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]);
540 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]);
541 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]);
542 OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]);
543 OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]);
544 }
545
546 if (dirty & I830_UPLOAD_TEXBLEND(i)) {
547 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
548 state->TexBlendWordsUsed[i]);
549 emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
550 }
551 }
552
553 intel->batch->dirty_state &= ~dirty;
554 assert(get_dirty(state) == 0);
555 assert((intel->batch->dirty_state & (1<<1)) == 0);
556 }
557
558 static void
559 i830_destroy_context(struct intel_context *intel)
560 {
561 GLuint i;
562 struct i830_context *i830 = i830_context(&intel->ctx);
563
564 for (i = 0; i < I830_TEX_UNITS; i++) {
565 if (i830->state.tex_buffer[i] != NULL) {
566 dri_bo_unreference(i830->state.tex_buffer[i]);
567 i830->state.tex_buffer[i] = NULL;
568 }
569 }
570
571 _tnl_free_vertices(&intel->ctx);
572 }
573
574
575 void
576 i830_state_draw_region(struct intel_context *intel,
577 struct i830_hw_state *state,
578 struct intel_region *color_region,
579 struct intel_region *depth_region)
580 {
581 struct i830_context *i830 = i830_context(&intel->ctx);
582 GLuint value;
583
584 ASSERT(state == &i830->state || state == &i830->meta);
585
586 if (state->draw_region != color_region) {
587 intel_region_release(&state->draw_region);
588 intel_region_reference(&state->draw_region, color_region);
589 }
590 if (state->depth_region != depth_region) {
591 intel_region_release(&state->depth_region);
592 intel_region_reference(&state->depth_region, depth_region);
593 }
594
595 /*
596 * Set stride/cpp values
597 */
598 if (color_region) {
599 state->Buffer[I830_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
600 state->Buffer[I830_DESTREG_CBUFADDR1] =
601 (BUF_3D_ID_COLOR_BACK |
602 BUF_3D_PITCH(color_region->pitch * color_region->cpp) |
603 BUF_3D_USE_FENCE);
604 }
605
606 if (depth_region) {
607 state->Buffer[I830_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
608 state->Buffer[I830_DESTREG_DBUFADDR1] =
609 (BUF_3D_ID_DEPTH |
610 BUF_3D_PITCH(depth_region->pitch * depth_region->cpp) |
611 BUF_3D_USE_FENCE);
612 }
613
614 /*
615 * Compute/set I830_DESTREG_DV1 value
616 */
617 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
618 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */
619
620 if (color_region && color_region->cpp == 4) {
621 value |= DV_PF_8888;
622 }
623 else {
624 value |= DV_PF_565;
625 }
626 if (depth_region && depth_region->cpp == 4) {
627 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
628 }
629 else {
630 value |= DEPTH_FRMT_16_FIXED;
631 }
632 state->Buffer[I830_DESTREG_DV1] = value;
633
634 I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
635
636
637 }
638
639
640 static void
641 i830_set_draw_region(struct intel_context *intel,
642 struct intel_region *color_regions[],
643 struct intel_region *depth_region,
644 GLuint num_regions)
645 {
646 struct i830_context *i830 = i830_context(&intel->ctx);
647 i830_state_draw_region(intel, &i830->state, color_regions[0], depth_region);
648 }
649
650 #if 0
651 static void
652 i830_update_color_z_regions(intelContextPtr intel,
653 const intelRegion * colorRegion,
654 const intelRegion * depthRegion)
655 {
656 i830ContextPtr i830 = I830_CONTEXT(intel);
657
658 i830->state.Buffer[I830_DESTREG_CBUFADDR1] =
659 (BUF_3D_ID_COLOR_BACK | BUF_3D_PITCH(colorRegion->pitch) |
660 BUF_3D_USE_FENCE);
661 i830->state.Buffer[I830_DESTREG_CBUFADDR2] = colorRegion->offset;
662
663 i830->state.Buffer[I830_DESTREG_DBUFADDR1] =
664 (BUF_3D_ID_DEPTH | BUF_3D_PITCH(depthRegion->pitch) | BUF_3D_USE_FENCE);
665 i830->state.Buffer[I830_DESTREG_DBUFADDR2] = depthRegion->offset;
666 }
667 #endif
668
669
670 /* This isn't really handled at the moment.
671 */
672 static void
673 i830_new_batch(struct intel_context *intel)
674 {
675 struct i830_context *i830 = i830_context(&intel->ctx);
676 i830->state.emitted = 0;
677
678 /* Check that we didn't just wrap our batchbuffer at a bad time. */
679 assert(!intel->no_batch_wrap);
680 }
681
682
683
684 static GLuint
685 i830_flush_cmd(void)
686 {
687 return MI_FLUSH | FLUSH_MAP_CACHE;
688 }
689
690
691 static void
692 i830_assert_not_dirty( struct intel_context *intel )
693 {
694 struct i830_context *i830 = i830_context(&intel->ctx);
695 struct i830_hw_state *state = i830->current;
696 assert(!get_dirty(state));
697 }
698
699 static void
700 i830_note_unlock( struct intel_context *intel )
701 {
702 /* nothing */
703 }
704
705 void
706 i830InitVtbl(struct i830_context *i830)
707 {
708 i830->intel.vtbl.check_vertex_size = i830_check_vertex_size;
709 i830->intel.vtbl.destroy = i830_destroy_context;
710 i830->intel.vtbl.emit_state = i830_emit_state;
711 i830->intel.vtbl.new_batch = i830_new_batch;
712 i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state;
713 i830->intel.vtbl.set_draw_region = i830_set_draw_region;
714 i830->intel.vtbl.update_texture_state = i830UpdateTextureState;
715 i830->intel.vtbl.flush_cmd = i830_flush_cmd;
716 i830->intel.vtbl.render_start = i830_render_start;
717 i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
718 i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
719 i830->intel.vtbl.note_unlock = i830_note_unlock;
720 }