1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "i830_context.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_regions.h"
32 #include "intel_tris.h"
33 #include "intel_fbo.h"
35 #include "tnl/t_context.h"
36 #include "tnl/t_vertex.h"
37 #include "swrast_setup/swrast_setup.h"
39 #define FILE_DEBUG_FLAG DEBUG_STATE
41 static GLboolean
i830_check_vertex_size(struct intel_context
*intel
,
44 #define SZ_TO_HW(sz) ((sz-2)&0x3)
45 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
46 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
48 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
49 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
50 intel->vertex_attr_count++; \
54 #define EMIT_PAD( N ) \
56 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
57 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
58 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
59 intel->vertex_attr_count++; \
63 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
64 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
67 i830_render_prevalidate(struct intel_context
*intel
)
72 i830_render_start(struct intel_context
*intel
)
74 struct gl_context
*ctx
= &intel
->ctx
;
75 struct i830_context
*i830
= i830_context(ctx
);
76 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
77 struct vertex_buffer
*VB
= &tnl
->vb
;
78 DECLARE_RENDERINPUTS(index_bitset
);
79 GLuint v0
= _3DSTATE_VFT0_CMD
;
80 GLuint v2
= _3DSTATE_VFT1_CMD
;
83 RENDERINPUTS_COPY(index_bitset
, tnl
->render_inputs_bitset
);
87 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
88 intel
->vertex_attr_count
= 0;
90 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
91 * build up a hardware vertex.
93 if (RENDERINPUTS_TEST_RANGE(index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
94 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_4F_VIEWPORT
, VFT0_XYZW
);
95 intel
->coloroffset
= 4;
98 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_3F_VIEWPORT
, VFT0_XYZ
);
99 intel
->coloroffset
= 3;
102 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_POINTSIZE
)) {
103 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE
, EMIT_1F
, VFT0_POINT_WIDTH
);
106 EMIT_ATTR(_TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_BGRA
, VFT0_DIFFUSE
);
108 intel
->specoffset
= 0;
109 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_COLOR1
) ||
110 RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_FOG
)) {
111 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_COLOR1
)) {
112 intel
->specoffset
= intel
->coloroffset
+ 1;
113 EMIT_ATTR(_TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
, VFT0_SPEC
);
118 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_FOG
))
119 EMIT_ATTR(_TNL_ATTRIB_FOG
, EMIT_1UB_1F
, VFT0_SPEC
);
124 if (RENDERINPUTS_TEST_RANGE(index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
127 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
128 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_TEX(i
))) {
129 GLuint sz
= VB
->AttribPtr
[_TNL_ATTRIB_TEX0
+ i
]->size
;
131 GLuint mcs
= (i830
->state
.Tex
[i
][I830_TEXREG_MCS
] &
139 mcs
|= TEXCOORDTYPE_CARTESIAN
;
144 mcs
|= TEXCOORDTYPE_VECTOR
;
149 mcs
|= TEXCOORDTYPE_HOMOGENEOUS
;
156 EMIT_ATTR(_TNL_ATTRIB_TEX0
+ i
, emit
, 0);
157 v2
|= VRTX_TEX_SET_FMT(count
, SZ_TO_HW(sz
));
158 mcsb1
|= (count
+ 8) << (i
* 4);
160 if (mcs
!= i830
->state
.Tex
[i
][I830_TEXREG_MCS
]) {
161 I830_STATECHANGE(i830
, I830_UPLOAD_TEX(i
));
162 i830
->state
.Tex
[i
][I830_TEXREG_MCS
] = mcs
;
169 v0
|= VFT0_TEX_COUNT(count
);
172 /* Only need to change the vertex emit code if there has been a
173 * statechange to a new hardware vertex format:
175 if (v0
!= i830
->state
.Ctx
[I830_CTXREG_VF
] ||
176 v2
!= i830
->state
.Ctx
[I830_CTXREG_VF2
] ||
177 mcsb1
!= i830
->state
.Ctx
[I830_CTXREG_MCSB1
] ||
178 !RENDERINPUTS_EQUAL(index_bitset
, i830
->last_index_bitset
)) {
181 I830_STATECHANGE(i830
, I830_UPLOAD_CTX
);
183 /* Must do this *after* statechange, so as not to affect
184 * buffered vertices reliant on the old state:
187 _tnl_install_attrs(ctx
,
189 intel
->vertex_attr_count
,
190 intel
->ViewportMatrix
.m
, 0);
192 intel
->vertex_size
>>= 2;
194 i830
->state
.Ctx
[I830_CTXREG_VF
] = v0
;
195 i830
->state
.Ctx
[I830_CTXREG_VF2
] = v2
;
196 i830
->state
.Ctx
[I830_CTXREG_MCSB1
] = mcsb1
;
197 RENDERINPUTS_COPY(i830
->last_index_bitset
, index_bitset
);
199 k
= i830_check_vertex_size(intel
, intel
->vertex_size
);
205 i830_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
207 struct i830_context
*i830
= i830_context(&intel
->ctx
);
208 GLuint st1
= i830
->state
.Stipple
[I830_STPREG_ST1
];
214 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
223 i830
->intel
.reduced_primitive
= rprim
;
225 if (st1
!= i830
->state
.Stipple
[I830_STPREG_ST1
]) {
226 INTEL_FIREVERTICES(intel
);
228 I830_STATECHANGE(i830
, I830_UPLOAD_STIPPLE
);
229 i830
->state
.Stipple
[I830_STPREG_ST1
] = st1
;
233 /* Pull apart the vertex format registers and figure out how large a
234 * vertex is supposed to be.
237 i830_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
239 struct i830_context
*i830
= i830_context(&intel
->ctx
);
240 int vft0
= i830
->state
.Ctx
[I830_CTXREG_VF
];
241 int vft1
= i830
->state
.Ctx
[I830_CTXREG_VF2
];
242 int nrtex
= (vft0
& VFT0_TEX_COUNT_MASK
) >> VFT0_TEX_COUNT_SHIFT
;
245 switch (vft0
& VFT0_XYZW_MASK
) {
259 fprintf(stderr
, "no xyzw specified\n");
263 if (vft0
& VFT0_SPEC
)
265 if (vft0
& VFT0_DIFFUSE
)
267 if (vft0
& VFT0_DEPTH_OFFSET
)
269 if (vft0
& VFT0_POINT_WIDTH
)
272 for (i
= 0; i
< nrtex
; i
++) {
273 switch (vft1
& VFT1_TEX0_MASK
) {
287 vft1
>>= VFT1_TEX1_SHIFT
;
291 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
293 return sz
== expected
;
297 i830_emit_invarient_state(struct intel_context
*intel
)
303 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
306 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
309 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
312 OUT_BATCH(_3DSTATE_FOG_MODE_CMD
);
313 OUT_BATCH(FOGFUNC_ENABLE
|
314 FOG_LINEAR_CONST
| FOGSRC_INDEX_Z
| ENABLE_FOG_DENSITY
);
319 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
321 DISABLE_TEX_STREAM_BUMP
|
322 ENABLE_TEX_STREAM_COORD_SET
|
323 TEX_STREAM_COORD_SET(0) |
324 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(0));
325 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
327 DISABLE_TEX_STREAM_BUMP
|
328 ENABLE_TEX_STREAM_COORD_SET
|
329 TEX_STREAM_COORD_SET(1) |
330 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(1));
331 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
333 DISABLE_TEX_STREAM_BUMP
|
334 ENABLE_TEX_STREAM_COORD_SET
|
335 TEX_STREAM_COORD_SET(2) |
336 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(2));
337 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
339 DISABLE_TEX_STREAM_BUMP
|
340 ENABLE_TEX_STREAM_COORD_SET
|
341 TEX_STREAM_COORD_SET(3) |
342 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(3));
344 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
345 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(0));
346 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
347 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(1));
348 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
349 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(2));
350 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
351 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(3));
353 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM
);
354 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM
| DISABLE_PERSPECTIVE_DIVIDE
);
356 OUT_BATCH(_3DSTATE_W_STATE_CMD
);
357 OUT_BATCH(MAGIC_W_STATE_DWORD1
);
358 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
361 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD
);
362 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
368 #define emit( intel, state, size ) \
369 intel_batchbuffer_data(intel, state, size, false)
372 get_dirty(struct i830_hw_state
*state
)
374 return state
->active
& ~state
->emitted
;
378 get_state_size(struct i830_hw_state
*state
)
380 GLuint dirty
= get_dirty(state
);
384 if (dirty
& I830_UPLOAD_INVARIENT
)
385 sz
+= 40 * sizeof(int);
387 if (dirty
& I830_UPLOAD_RASTER_RULES
)
388 sz
+= sizeof(state
->RasterRules
);
390 if (dirty
& I830_UPLOAD_CTX
)
391 sz
+= sizeof(state
->Ctx
);
393 if (dirty
& I830_UPLOAD_BUFFERS
)
394 sz
+= sizeof(state
->Buffer
);
396 if (dirty
& I830_UPLOAD_STIPPLE
)
397 sz
+= sizeof(state
->Stipple
);
399 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
400 if ((dirty
& I830_UPLOAD_TEX(i
)))
401 sz
+= sizeof(state
->Tex
[i
]);
403 if (dirty
& I830_UPLOAD_TEXBLEND(i
))
404 sz
+= state
->TexBlendWordsUsed
[i
] * 4;
411 /* Push the state into the sarea and/or texture memory.
414 i830_emit_state(struct intel_context
*intel
)
416 struct i830_context
*i830
= i830_context(&intel
->ctx
);
417 struct i830_hw_state
*state
= &i830
->state
;
420 drm_intel_bo
*aper_array
[3 + I830_TEX_UNITS
];
422 GET_CURRENT_CONTEXT(ctx
);
425 /* We don't hold the lock at this point, so want to make sure that
426 * there won't be a buffer wrap between the state emits and the primitive
429 * It might be better to talk about explicit places where
430 * scheduling is allowed, rather than assume that it is whenever a
431 * batchbuffer fills up.
433 intel_batchbuffer_require_space(intel
,
434 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
439 dirty
= get_dirty(state
);
441 aper_array
[aper_count
++] = intel
->batch
.bo
;
442 if (dirty
& I830_UPLOAD_BUFFERS
) {
443 aper_array
[aper_count
++] = state
->draw_region
->buffer
;
444 if (state
->depth_region
)
445 aper_array
[aper_count
++] = state
->depth_region
->buffer
;
448 for (i
= 0; i
< I830_TEX_UNITS
; i
++)
449 if (dirty
& I830_UPLOAD_TEX(i
)) {
450 if (state
->tex_buffer
[i
]) {
451 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
455 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
458 intel_batchbuffer_flush(intel
);
461 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i830 emit state");
467 /* Do this here as we may have flushed the batchbuffer above,
468 * causing more state to be dirty!
470 dirty
= get_dirty(state
);
471 state
->emitted
|= dirty
;
472 assert(get_dirty(state
) == 0);
474 if (dirty
& I830_UPLOAD_INVARIENT
) {
475 DBG("I830_UPLOAD_INVARIENT:\n");
476 i830_emit_invarient_state(intel
);
479 if (dirty
& I830_UPLOAD_RASTER_RULES
) {
480 DBG("I830_UPLOAD_RASTER_RULES:\n");
481 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
484 if (dirty
& I830_UPLOAD_CTX
) {
485 DBG("I830_UPLOAD_CTX:\n");
486 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
490 if (dirty
& I830_UPLOAD_BUFFERS
) {
493 DBG("I830_UPLOAD_BUFFERS:\n");
495 if (state
->depth_region
)
499 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR0
]);
500 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR1
]);
501 OUT_RELOC(state
->draw_region
->buffer
,
502 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
504 if (state
->depth_region
) {
505 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR0
]);
506 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR1
]);
507 OUT_RELOC(state
->depth_region
->buffer
,
508 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
511 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV0
]);
512 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV1
]);
513 OUT_BATCH(state
->Buffer
[I830_DESTREG_SENABLE
]);
514 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR0
]);
515 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR1
]);
516 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR2
]);
518 assert(state
->Buffer
[I830_DESTREG_DRAWRECT0
] != MI_NOOP
);
519 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT0
]);
520 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT1
]);
521 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT2
]);
522 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT3
]);
523 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT4
]);
524 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT5
]);
528 if (dirty
& I830_UPLOAD_STIPPLE
) {
529 DBG("I830_UPLOAD_STIPPLE:\n");
530 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
533 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
534 if ((dirty
& I830_UPLOAD_TEX(i
))) {
535 DBG("I830_UPLOAD_TEX(%d):\n", i
);
537 BEGIN_BATCH(I830_TEX_SETUP_SIZE
+ 1);
538 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0LI
]);
540 OUT_RELOC(state
->tex_buffer
[i
],
541 I915_GEM_DOMAIN_SAMPLER
, 0,
542 state
->tex_offset
[i
]);
544 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S1
]);
545 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S2
]);
546 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S3
]);
547 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S4
]);
548 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_MCS
]);
549 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_CUBE
]);
554 if (dirty
& I830_UPLOAD_TEXBLEND(i
)) {
555 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i
,
556 state
->TexBlendWordsUsed
[i
]);
557 emit(intel
, state
->TexBlend
[i
], state
->TexBlendWordsUsed
[i
] * 4);
561 assert(get_dirty(state
) == 0);
565 i830_destroy_context(struct intel_context
*intel
)
568 struct i830_context
*i830
= i830_context(&intel
->ctx
);
570 intel_region_release(&i830
->state
.draw_region
);
571 intel_region_release(&i830
->state
.depth_region
);
573 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
574 if (i830
->state
.tex_buffer
[i
] != NULL
) {
575 drm_intel_bo_unreference(i830
->state
.tex_buffer
[i
]);
576 i830
->state
.tex_buffer
[i
] = NULL
;
580 _tnl_free_vertices(&intel
->ctx
);
583 static uint32_t i830_render_target_format_for_mesa_format
[MESA_FORMAT_COUNT
] =
585 [MESA_FORMAT_ARGB8888
] = DV_PF_8888
,
586 [MESA_FORMAT_XRGB8888
] = DV_PF_8888
,
587 [MESA_FORMAT_RGB565
] = DV_PF_565
,
588 [MESA_FORMAT_ARGB1555
] = DV_PF_1555
,
589 [MESA_FORMAT_ARGB4444
] = DV_PF_4444
,
593 i830_render_target_supported(gl_format format
)
595 if (format
== MESA_FORMAT_S8_Z24
||
596 format
== MESA_FORMAT_X8_Z24
||
597 format
== MESA_FORMAT_Z16
) {
601 return i830_render_target_format_for_mesa_format
[format
] != 0;
605 i830_set_draw_region(struct intel_context
*intel
,
606 struct intel_region
*color_regions
[],
607 struct intel_region
*depth_region
,
610 struct i830_context
*i830
= i830_context(&intel
->ctx
);
611 struct gl_context
*ctx
= &intel
->ctx
;
612 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
613 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
614 struct gl_renderbuffer
*drb
;
615 struct intel_renderbuffer
*idrb
= NULL
;
617 struct i830_hw_state
*state
= &i830
->state
;
618 uint32_t draw_x
, draw_y
;
620 if (state
->draw_region
!= color_regions
[0]) {
621 intel_region_release(&state
->draw_region
);
622 intel_region_reference(&state
->draw_region
, color_regions
[0]);
624 if (state
->depth_region
!= depth_region
) {
625 intel_region_release(&state
->depth_region
);
626 intel_region_reference(&state
->depth_region
, depth_region
);
630 * Set stride/cpp values
632 i915_set_buf_info_for_region(&state
->Buffer
[I830_DESTREG_CBUFADDR0
],
633 color_regions
[0], BUF_3D_ID_COLOR_BACK
);
635 i915_set_buf_info_for_region(&state
->Buffer
[I830_DESTREG_DBUFADDR0
],
636 depth_region
, BUF_3D_ID_DEPTH
);
639 * Compute/set I830_DESTREG_DV1 value
641 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
642 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z
); /* .5 */
645 value
|= i830_render_target_format_for_mesa_format
[irb
->Base
.Format
];
648 if (depth_region
&& depth_region
->cpp
== 4) {
649 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
652 value
|= DEPTH_FRMT_16_FIXED
;
654 state
->Buffer
[I830_DESTREG_DV1
] = value
;
656 drb
= ctx
->DrawBuffer
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
658 drb
= ctx
->DrawBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
661 idrb
= intel_renderbuffer(drb
);
663 /* We set up the drawing rectangle to be offset into the color
664 * region's location in the miptree. If it doesn't match with
665 * depth's offsets, we can't render to it.
667 * (Well, not actually true -- the hw grew a bit to let depth's
668 * offset get forced to 0,0. We may want to use that if people are
669 * hitting that case. Also, some configurations may be supportable
670 * by tweaking the start offset of the buffers around, which we
671 * can't do in general due to tiling)
673 FALLBACK(intel
, I830_FALLBACK_DRAW_OFFSET
,
674 idrb
&& irb
&& (idrb
->draw_x
!= irb
->draw_x
||
675 idrb
->draw_y
!= irb
->draw_y
));
678 draw_x
= irb
->draw_x
;
679 draw_y
= irb
->draw_y
;
681 draw_x
= idrb
->draw_x
;
682 draw_y
= idrb
->draw_y
;
688 state
->Buffer
[I830_DESTREG_DRAWRECT0
] = _3DSTATE_DRAWRECT_INFO
;
689 state
->Buffer
[I830_DESTREG_DRAWRECT1
] = 0;
690 state
->Buffer
[I830_DESTREG_DRAWRECT2
] = (draw_y
<< 16) | draw_x
;
691 state
->Buffer
[I830_DESTREG_DRAWRECT3
] =
692 ((ctx
->DrawBuffer
->Width
+ draw_x
) & 0xffff) |
693 ((ctx
->DrawBuffer
->Height
+ draw_y
) << 16);
694 state
->Buffer
[I830_DESTREG_DRAWRECT4
] = (draw_y
<< 16) | draw_x
;
695 state
->Buffer
[I830_DESTREG_DRAWRECT5
] = MI_NOOP
;
697 I830_STATECHANGE(i830
, I830_UPLOAD_BUFFERS
);
700 /* This isn't really handled at the moment.
703 i830_new_batch(struct intel_context
*intel
)
705 struct i830_context
*i830
= i830_context(&intel
->ctx
);
706 i830
->state
.emitted
= 0;
710 i830_assert_not_dirty( struct intel_context
*intel
)
712 struct i830_context
*i830
= i830_context(&intel
->ctx
);
713 assert(!get_dirty(&i830
->state
));
718 i830_invalidate_state(struct intel_context
*intel
, GLuint new_state
)
720 struct gl_context
*ctx
= &intel
->ctx
;
722 _swsetup_InvalidateState(ctx
, new_state
);
723 _tnl_InvalidateState(ctx
, new_state
);
724 _tnl_invalidate_vertex_state(ctx
, new_state
);
726 if (new_state
& _NEW_LIGHT
)
727 i830_update_provoking_vertex(&intel
->ctx
);
731 i830InitVtbl(struct i830_context
*i830
)
733 i830
->intel
.vtbl
.check_vertex_size
= i830_check_vertex_size
;
734 i830
->intel
.vtbl
.destroy
= i830_destroy_context
;
735 i830
->intel
.vtbl
.emit_state
= i830_emit_state
;
736 i830
->intel
.vtbl
.new_batch
= i830_new_batch
;
737 i830
->intel
.vtbl
.reduced_primitive_state
= i830_reduced_primitive_state
;
738 i830
->intel
.vtbl
.set_draw_region
= i830_set_draw_region
;
739 i830
->intel
.vtbl
.update_texture_state
= i830UpdateTextureState
;
740 i830
->intel
.vtbl
.render_start
= i830_render_start
;
741 i830
->intel
.vtbl
.render_prevalidate
= i830_render_prevalidate
;
742 i830
->intel
.vtbl
.assert_not_dirty
= i830_assert_not_dirty
;
743 i830
->intel
.vtbl
.finish_batch
= intel_finish_vb
;
744 i830
->intel
.vtbl
.invalidate_state
= i830_invalidate_state
;
745 i830
->intel
.vtbl
.render_target_supported
= i830_render_target_supported
;