1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "glapi/glapi.h"
29 #include "main/texformat.h"
31 #include "i830_context.h"
33 #include "intel_batchbuffer.h"
34 #include "intel_regions.h"
35 #include "intel_tris.h"
36 #include "intel_fbo.h"
37 #include "tnl/t_context.h"
38 #include "tnl/t_vertex.h"
40 #define FILE_DEBUG_FLAG DEBUG_STATE
42 static GLboolean
i830_check_vertex_size(struct intel_context
*intel
,
45 #define SZ_TO_HW(sz) ((sz-2)&0x3)
46 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
47 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
49 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
50 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
51 intel->vertex_attr_count++; \
55 #define EMIT_PAD( N ) \
57 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
58 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
59 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
60 intel->vertex_attr_count++; \
64 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
65 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
68 i830_render_prevalidate(struct intel_context
*intel
)
73 i830_render_start(struct intel_context
*intel
)
75 GLcontext
*ctx
= &intel
->ctx
;
76 struct i830_context
*i830
= i830_context(ctx
);
77 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
78 struct vertex_buffer
*VB
= &tnl
->vb
;
79 DECLARE_RENDERINPUTS(index_bitset
);
80 GLuint v0
= _3DSTATE_VFT0_CMD
;
81 GLuint v2
= _3DSTATE_VFT1_CMD
;
84 RENDERINPUTS_COPY(index_bitset
, tnl
->render_inputs_bitset
);
88 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
89 intel
->vertex_attr_count
= 0;
91 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
92 * build up a hardware vertex.
94 if (RENDERINPUTS_TEST_RANGE(index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
95 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_4F_VIEWPORT
, VFT0_XYZW
);
96 intel
->coloroffset
= 4;
99 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_3F_VIEWPORT
, VFT0_XYZ
);
100 intel
->coloroffset
= 3;
103 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_POINTSIZE
)) {
104 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE
, EMIT_1F
, VFT0_POINT_WIDTH
);
107 EMIT_ATTR(_TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_BGRA
, VFT0_DIFFUSE
);
109 intel
->specoffset
= 0;
110 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_COLOR1
) ||
111 RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_FOG
)) {
112 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_COLOR1
)) {
113 intel
->specoffset
= intel
->coloroffset
+ 1;
114 EMIT_ATTR(_TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
, VFT0_SPEC
);
119 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_FOG
))
120 EMIT_ATTR(_TNL_ATTRIB_FOG
, EMIT_1UB_1F
, VFT0_SPEC
);
125 if (RENDERINPUTS_TEST_RANGE(index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
128 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
129 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_TEX(i
))) {
130 GLuint sz
= VB
->TexCoordPtr
[i
]->size
;
132 GLuint mcs
= (i830
->state
.Tex
[i
][I830_TEXREG_MCS
] &
140 mcs
|= TEXCOORDTYPE_CARTESIAN
;
145 mcs
|= TEXCOORDTYPE_VECTOR
;
150 mcs
|= TEXCOORDTYPE_HOMOGENEOUS
;
157 EMIT_ATTR(_TNL_ATTRIB_TEX0
+ i
, emit
, 0);
158 v2
|= VRTX_TEX_SET_FMT(count
, SZ_TO_HW(sz
));
159 mcsb1
|= (count
+ 8) << (i
* 4);
161 if (mcs
!= i830
->state
.Tex
[i
][I830_TEXREG_MCS
]) {
162 I830_STATECHANGE(i830
, I830_UPLOAD_TEX(i
));
163 i830
->state
.Tex
[i
][I830_TEXREG_MCS
] = mcs
;
170 v0
|= VFT0_TEX_COUNT(count
);
173 /* Only need to change the vertex emit code if there has been a
174 * statechange to a new hardware vertex format:
176 if (v0
!= i830
->state
.Ctx
[I830_CTXREG_VF
] ||
177 v2
!= i830
->state
.Ctx
[I830_CTXREG_VF2
] ||
178 mcsb1
!= i830
->state
.Ctx
[I830_CTXREG_MCSB1
] ||
179 !RENDERINPUTS_EQUAL(index_bitset
, i830
->last_index_bitset
)) {
182 I830_STATECHANGE(i830
, I830_UPLOAD_CTX
);
184 /* Must do this *after* statechange, so as not to affect
185 * buffered vertices reliant on the old state:
188 _tnl_install_attrs(ctx
,
190 intel
->vertex_attr_count
,
191 intel
->ViewportMatrix
.m
, 0);
193 intel
->vertex_size
>>= 2;
195 i830
->state
.Ctx
[I830_CTXREG_VF
] = v0
;
196 i830
->state
.Ctx
[I830_CTXREG_VF2
] = v2
;
197 i830
->state
.Ctx
[I830_CTXREG_MCSB1
] = mcsb1
;
198 RENDERINPUTS_COPY(i830
->last_index_bitset
, index_bitset
);
200 k
= i830_check_vertex_size(intel
, intel
->vertex_size
);
206 i830_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
208 struct i830_context
*i830
= i830_context(&intel
->ctx
);
209 GLuint st1
= i830
->state
.Stipple
[I830_STPREG_ST1
];
215 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
224 i830
->intel
.reduced_primitive
= rprim
;
226 if (st1
!= i830
->state
.Stipple
[I830_STPREG_ST1
]) {
227 INTEL_FIREVERTICES(intel
);
229 I830_STATECHANGE(i830
, I830_UPLOAD_STIPPLE
);
230 i830
->state
.Stipple
[I830_STPREG_ST1
] = st1
;
234 /* Pull apart the vertex format registers and figure out how large a
235 * vertex is supposed to be.
238 i830_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
240 struct i830_context
*i830
= i830_context(&intel
->ctx
);
241 int vft0
= i830
->current
->Ctx
[I830_CTXREG_VF
];
242 int vft1
= i830
->current
->Ctx
[I830_CTXREG_VF2
];
243 int nrtex
= (vft0
& VFT0_TEX_COUNT_MASK
) >> VFT0_TEX_COUNT_SHIFT
;
246 switch (vft0
& VFT0_XYZW_MASK
) {
260 fprintf(stderr
, "no xyzw specified\n");
264 if (vft0
& VFT0_SPEC
)
266 if (vft0
& VFT0_DIFFUSE
)
268 if (vft0
& VFT0_DEPTH_OFFSET
)
270 if (vft0
& VFT0_POINT_WIDTH
)
273 for (i
= 0; i
< nrtex
; i
++) {
274 switch (vft1
& VFT1_TEX0_MASK
) {
288 vft1
>>= VFT1_TEX1_SHIFT
;
292 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
294 return sz
== expected
;
298 i830_emit_invarient_state(struct intel_context
*intel
)
302 BEGIN_BATCH(29, IGNORE_CLIPRECTS
);
304 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
307 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
310 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
313 OUT_BATCH(_3DSTATE_FOG_MODE_CMD
);
314 OUT_BATCH(FOGFUNC_ENABLE
|
315 FOG_LINEAR_CONST
| FOGSRC_INDEX_Z
| ENABLE_FOG_DENSITY
);
320 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
322 DISABLE_TEX_STREAM_BUMP
|
323 ENABLE_TEX_STREAM_COORD_SET
|
324 TEX_STREAM_COORD_SET(0) |
325 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(0));
326 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
328 DISABLE_TEX_STREAM_BUMP
|
329 ENABLE_TEX_STREAM_COORD_SET
|
330 TEX_STREAM_COORD_SET(1) |
331 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(1));
332 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
334 DISABLE_TEX_STREAM_BUMP
|
335 ENABLE_TEX_STREAM_COORD_SET
|
336 TEX_STREAM_COORD_SET(2) |
337 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(2));
338 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
340 DISABLE_TEX_STREAM_BUMP
|
341 ENABLE_TEX_STREAM_COORD_SET
|
342 TEX_STREAM_COORD_SET(3) |
343 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(3));
345 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
346 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(0));
347 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
348 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(1));
349 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
350 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(2));
351 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
352 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(3));
354 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM
);
355 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM
| DISABLE_PERSPECTIVE_DIVIDE
);
357 OUT_BATCH(_3DSTATE_W_STATE_CMD
);
358 OUT_BATCH(MAGIC_W_STATE_DWORD1
);
359 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
362 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD
);
363 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
369 #define emit( intel, state, size ) \
370 intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
373 get_dirty(struct i830_hw_state
*state
)
375 return state
->active
& ~state
->emitted
;
379 get_state_size(struct i830_hw_state
*state
)
381 GLuint dirty
= get_dirty(state
);
385 if (dirty
& I830_UPLOAD_INVARIENT
)
386 sz
+= 40 * sizeof(int);
388 if (dirty
& I830_UPLOAD_RASTER_RULES
)
389 sz
+= sizeof(state
->RasterRules
);
391 if (dirty
& I830_UPLOAD_CTX
)
392 sz
+= sizeof(state
->Ctx
);
394 if (dirty
& I830_UPLOAD_BUFFERS
)
395 sz
+= sizeof(state
->Buffer
);
397 if (dirty
& I830_UPLOAD_STIPPLE
)
398 sz
+= sizeof(state
->Stipple
);
400 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
401 if ((dirty
& I830_UPLOAD_TEX(i
)))
402 sz
+= sizeof(state
->Tex
[i
]);
404 if (dirty
& I830_UPLOAD_TEXBLEND(i
))
405 sz
+= state
->TexBlendWordsUsed
[i
] * 4;
412 /* Push the state into the sarea and/or texture memory.
415 i830_emit_state(struct intel_context
*intel
)
417 struct i830_context
*i830
= i830_context(&intel
->ctx
);
418 struct i830_hw_state
*state
= i830
->current
;
421 dri_bo
*aper_array
[3 + I830_TEX_UNITS
];
423 GET_CURRENT_CONTEXT(ctx
);
426 /* We don't hold the lock at this point, so want to make sure that
427 * there won't be a buffer wrap between the state emits and the primitive
430 * It might be better to talk about explicit places where
431 * scheduling is allowed, rather than assume that it is whenever a
432 * batchbuffer fills up.
434 * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
435 * will be emitted under.
437 intel_batchbuffer_require_space(intel
->batch
,
438 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
443 dirty
= get_dirty(state
);
445 aper_array
[aper_count
++] = intel
->batch
->buf
;
446 if (dirty
& I830_UPLOAD_BUFFERS
) {
447 aper_array
[aper_count
++] = state
->draw_region
->buffer
;
448 if (state
->depth_region
)
449 aper_array
[aper_count
++] = state
->depth_region
->buffer
;
452 for (i
= 0; i
< I830_TEX_UNITS
; i
++)
453 if (dirty
& I830_UPLOAD_TEX(i
)) {
454 if (state
->tex_buffer
[i
]) {
455 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
459 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
462 intel_batchbuffer_flush(intel
->batch
);
465 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i830 emit state");
471 /* Do this here as we may have flushed the batchbuffer above,
472 * causing more state to be dirty!
474 dirty
= get_dirty(state
);
475 state
->emitted
|= dirty
;
476 assert(get_dirty(state
) == 0);
478 if (dirty
& I830_UPLOAD_INVARIENT
) {
479 DBG("I830_UPLOAD_INVARIENT:\n");
480 i830_emit_invarient_state(intel
);
483 if (dirty
& I830_UPLOAD_RASTER_RULES
) {
484 DBG("I830_UPLOAD_RASTER_RULES:\n");
485 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
488 if (dirty
& I830_UPLOAD_CTX
) {
489 DBG("I830_UPLOAD_CTX:\n");
490 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
494 if (dirty
& I830_UPLOAD_BUFFERS
) {
497 DBG("I830_UPLOAD_BUFFERS:\n");
499 if (state
->depth_region
)
502 if (intel
->constant_cliprect
)
505 BEGIN_BATCH(count
, IGNORE_CLIPRECTS
);
506 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR0
]);
507 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR1
]);
508 OUT_RELOC(state
->draw_region
->buffer
,
509 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
510 state
->draw_region
->draw_offset
);
512 if (state
->depth_region
) {
513 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR0
]);
514 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR1
]);
515 OUT_RELOC(state
->depth_region
->buffer
,
516 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
517 state
->depth_region
->draw_offset
);
520 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV0
]);
521 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV1
]);
522 OUT_BATCH(state
->Buffer
[I830_DESTREG_SENABLE
]);
523 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR0
]);
524 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR1
]);
525 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR2
]);
527 if (intel
->constant_cliprect
) {
528 assert(state
->Buffer
[I830_DESTREG_DRAWRECT0
] != MI_NOOP
);
529 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT0
]);
530 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT1
]);
531 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT2
]);
532 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT3
]);
533 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT4
]);
534 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT5
]);
539 if (dirty
& I830_UPLOAD_STIPPLE
) {
540 DBG("I830_UPLOAD_STIPPLE:\n");
541 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
544 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
545 if ((dirty
& I830_UPLOAD_TEX(i
))) {
546 DBG("I830_UPLOAD_TEX(%d):\n", i
);
548 BEGIN_BATCH(I830_TEX_SETUP_SIZE
+ 1, IGNORE_CLIPRECTS
);
549 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0LI
]);
551 if (state
->tex_buffer
[i
]) {
552 OUT_RELOC(state
->tex_buffer
[i
],
553 I915_GEM_DOMAIN_SAMPLER
, 0,
554 state
->tex_offset
[i
]);
556 else if (state
== &i830
->meta
) {
561 OUT_BATCH(state
->tex_offset
[i
]);
564 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S1
]);
565 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S2
]);
566 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S3
]);
567 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S4
]);
568 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_MCS
]);
569 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_CUBE
]);
574 if (dirty
& I830_UPLOAD_TEXBLEND(i
)) {
575 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i
,
576 state
->TexBlendWordsUsed
[i
]);
577 emit(intel
, state
->TexBlend
[i
], state
->TexBlendWordsUsed
[i
] * 4);
581 intel
->batch
->dirty_state
&= ~dirty
;
582 assert(get_dirty(state
) == 0);
583 assert((intel
->batch
->dirty_state
& (1<<1)) == 0);
587 i830_destroy_context(struct intel_context
*intel
)
590 struct i830_context
*i830
= i830_context(&intel
->ctx
);
592 intel_region_release(&i830
->state
.draw_region
);
593 intel_region_release(&i830
->state
.depth_region
);
594 intel_region_release(&i830
->meta
.draw_region
);
595 intel_region_release(&i830
->meta
.depth_region
);
596 intel_region_release(&i830
->initial
.draw_region
);
597 intel_region_release(&i830
->initial
.depth_region
);
599 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
600 if (i830
->state
.tex_buffer
[i
] != NULL
) {
601 dri_bo_unreference(i830
->state
.tex_buffer
[i
]);
602 i830
->state
.tex_buffer
[i
] = NULL
;
606 _tnl_free_vertices(&intel
->ctx
);
611 i830_state_draw_region(struct intel_context
*intel
,
612 struct i830_hw_state
*state
,
613 struct intel_region
*color_region
,
614 struct intel_region
*depth_region
)
616 struct i830_context
*i830
= i830_context(&intel
->ctx
);
617 GLcontext
*ctx
= &intel
->ctx
;
618 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
619 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
622 ASSERT(state
== &i830
->state
|| state
== &i830
->meta
);
624 if (state
->draw_region
!= color_region
) {
625 intel_region_release(&state
->draw_region
);
626 intel_region_reference(&state
->draw_region
, color_region
);
628 if (state
->depth_region
!= depth_region
) {
629 intel_region_release(&state
->depth_region
);
630 intel_region_reference(&state
->depth_region
, depth_region
);
634 * Set stride/cpp values
636 i915_set_buf_info_for_region(&state
->Buffer
[I830_DESTREG_CBUFADDR0
],
637 color_region
, BUF_3D_ID_COLOR_BACK
);
639 i915_set_buf_info_for_region(&state
->Buffer
[I830_DESTREG_DBUFADDR0
],
640 depth_region
, BUF_3D_ID_DEPTH
);
643 * Compute/set I830_DESTREG_DV1 value
645 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
646 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z
); /* .5 */
649 switch (irb
->texformat
->MesaFormat
) {
650 case MESA_FORMAT_ARGB8888
:
653 case MESA_FORMAT_RGB565
:
656 case MESA_FORMAT_ARGB1555
:
659 case MESA_FORMAT_ARGB4444
:
663 _mesa_problem(ctx
, "Bad renderbuffer format: %d\n",
664 irb
->texformat
->MesaFormat
);
668 if (depth_region
&& depth_region
->cpp
== 4) {
669 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
672 value
|= DEPTH_FRMT_16_FIXED
;
674 state
->Buffer
[I830_DESTREG_DV1
] = value
;
676 if (intel
->constant_cliprect
) {
677 state
->Buffer
[I830_DESTREG_DRAWRECT0
] = _3DSTATE_DRAWRECT_INFO
;
678 state
->Buffer
[I830_DESTREG_DRAWRECT1
] = 0;
679 state
->Buffer
[I830_DESTREG_DRAWRECT2
] = 0; /* xmin, ymin */
680 state
->Buffer
[I830_DESTREG_DRAWRECT3
] =
681 (ctx
->DrawBuffer
->Width
& 0xffff) |
682 (ctx
->DrawBuffer
->Height
<< 16);
683 state
->Buffer
[I830_DESTREG_DRAWRECT4
] = 0; /* xoff, yoff */
684 state
->Buffer
[I830_DESTREG_DRAWRECT5
] = 0;
686 state
->Buffer
[I830_DESTREG_DRAWRECT0
] = MI_NOOP
;
687 state
->Buffer
[I830_DESTREG_DRAWRECT1
] = MI_NOOP
;
688 state
->Buffer
[I830_DESTREG_DRAWRECT2
] = MI_NOOP
;
689 state
->Buffer
[I830_DESTREG_DRAWRECT3
] = MI_NOOP
;
690 state
->Buffer
[I830_DESTREG_DRAWRECT4
] = MI_NOOP
;
691 state
->Buffer
[I830_DESTREG_DRAWRECT5
] = MI_NOOP
;
694 I830_STATECHANGE(i830
, I830_UPLOAD_BUFFERS
);
701 i830_set_draw_region(struct intel_context
*intel
,
702 struct intel_region
*color_regions
[],
703 struct intel_region
*depth_region
,
706 struct i830_context
*i830
= i830_context(&intel
->ctx
);
707 i830_state_draw_region(intel
, &i830
->state
, color_regions
[0], depth_region
);
710 /* This isn't really handled at the moment.
713 i830_new_batch(struct intel_context
*intel
)
715 struct i830_context
*i830
= i830_context(&intel
->ctx
);
716 i830
->state
.emitted
= 0;
718 /* Check that we didn't just wrap our batchbuffer at a bad time. */
719 assert(!intel
->no_batch_wrap
);
727 return MI_FLUSH
| FLUSH_MAP_CACHE
;
732 i830_assert_not_dirty( struct intel_context
*intel
)
734 struct i830_context
*i830
= i830_context(&intel
->ctx
);
735 struct i830_hw_state
*state
= i830
->current
;
736 assert(!get_dirty(state
));
740 i830_invalidate_state(struct intel_context
*intel
, GLuint new_state
)
742 if (new_state
& _NEW_LIGHT
)
743 i830_update_provoking_vertex(&intel
->ctx
);
747 i830InitVtbl(struct i830_context
*i830
)
749 i830
->intel
.vtbl
.check_vertex_size
= i830_check_vertex_size
;
750 i830
->intel
.vtbl
.destroy
= i830_destroy_context
;
751 i830
->intel
.vtbl
.emit_state
= i830_emit_state
;
752 i830
->intel
.vtbl
.new_batch
= i830_new_batch
;
753 i830
->intel
.vtbl
.reduced_primitive_state
= i830_reduced_primitive_state
;
754 i830
->intel
.vtbl
.set_draw_region
= i830_set_draw_region
;
755 i830
->intel
.vtbl
.update_texture_state
= i830UpdateTextureState
;
756 i830
->intel
.vtbl
.flush_cmd
= i830_flush_cmd
;
757 i830
->intel
.vtbl
.render_start
= i830_render_start
;
758 i830
->intel
.vtbl
.render_prevalidate
= i830_render_prevalidate
;
759 i830
->intel
.vtbl
.assert_not_dirty
= i830_assert_not_dirty
;
760 i830
->intel
.vtbl
.finish_batch
= intel_finish_vb
;
761 i830
->intel
.vtbl
.invalidate_state
= i830_invalidate_state
;