1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "glapi/glapi.h"
30 #include "i830_context.h"
32 #include "intel_batchbuffer.h"
33 #include "intel_regions.h"
34 #include "intel_tris.h"
35 #include "tnl/t_context.h"
36 #include "tnl/t_vertex.h"
38 #define FILE_DEBUG_FLAG DEBUG_STATE
40 static GLboolean
i830_check_vertex_size(struct intel_context
*intel
,
43 #define SZ_TO_HW(sz) ((sz-2)&0x3)
44 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
45 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
47 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
48 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
49 intel->vertex_attr_count++; \
53 #define EMIT_PAD( N ) \
55 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
56 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
57 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
58 intel->vertex_attr_count++; \
62 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
63 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
66 i830_render_prevalidate(struct intel_context
*intel
)
71 i830_render_start(struct intel_context
*intel
)
73 GLcontext
*ctx
= &intel
->ctx
;
74 struct i830_context
*i830
= i830_context(ctx
);
75 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
76 struct vertex_buffer
*VB
= &tnl
->vb
;
77 DECLARE_RENDERINPUTS(index_bitset
);
78 GLuint v0
= _3DSTATE_VFT0_CMD
;
79 GLuint v2
= _3DSTATE_VFT1_CMD
;
82 RENDERINPUTS_COPY(index_bitset
, tnl
->render_inputs_bitset
);
86 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
87 intel
->vertex_attr_count
= 0;
89 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
90 * build up a hardware vertex.
92 if (RENDERINPUTS_TEST_RANGE(index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
93 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_4F_VIEWPORT
, VFT0_XYZW
);
94 intel
->coloroffset
= 4;
97 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_3F_VIEWPORT
, VFT0_XYZ
);
98 intel
->coloroffset
= 3;
101 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_POINTSIZE
)) {
102 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE
, EMIT_1F
, VFT0_POINT_WIDTH
);
105 EMIT_ATTR(_TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_BGRA
, VFT0_DIFFUSE
);
107 intel
->specoffset
= 0;
108 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_COLOR1
) ||
109 RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_FOG
)) {
110 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_COLOR1
)) {
111 intel
->specoffset
= intel
->coloroffset
+ 1;
112 EMIT_ATTR(_TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
, VFT0_SPEC
);
117 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_FOG
))
118 EMIT_ATTR(_TNL_ATTRIB_FOG
, EMIT_1UB_1F
, VFT0_SPEC
);
123 if (RENDERINPUTS_TEST_RANGE(index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
126 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
127 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_TEX(i
))) {
128 GLuint sz
= VB
->TexCoordPtr
[i
]->size
;
130 GLuint mcs
= (i830
->state
.Tex
[i
][I830_TEXREG_MCS
] &
138 mcs
|= TEXCOORDTYPE_CARTESIAN
;
143 mcs
|= TEXCOORDTYPE_VECTOR
;
148 mcs
|= TEXCOORDTYPE_HOMOGENEOUS
;
155 EMIT_ATTR(_TNL_ATTRIB_TEX0
+ i
, emit
, 0);
156 v2
|= VRTX_TEX_SET_FMT(count
, SZ_TO_HW(sz
));
157 mcsb1
|= (count
+ 8) << (i
* 4);
159 if (mcs
!= i830
->state
.Tex
[i
][I830_TEXREG_MCS
]) {
160 I830_STATECHANGE(i830
, I830_UPLOAD_TEX(i
));
161 i830
->state
.Tex
[i
][I830_TEXREG_MCS
] = mcs
;
168 v0
|= VFT0_TEX_COUNT(count
);
171 /* Only need to change the vertex emit code if there has been a
172 * statechange to a new hardware vertex format:
174 if (v0
!= i830
->state
.Ctx
[I830_CTXREG_VF
] ||
175 v2
!= i830
->state
.Ctx
[I830_CTXREG_VF2
] ||
176 mcsb1
!= i830
->state
.Ctx
[I830_CTXREG_MCSB1
] ||
177 !RENDERINPUTS_EQUAL(index_bitset
, i830
->last_index_bitset
)) {
180 I830_STATECHANGE(i830
, I830_UPLOAD_CTX
);
182 /* Must do this *after* statechange, so as not to affect
183 * buffered vertices reliant on the old state:
186 _tnl_install_attrs(ctx
,
188 intel
->vertex_attr_count
,
189 intel
->ViewportMatrix
.m
, 0);
191 intel
->vertex_size
>>= 2;
193 i830
->state
.Ctx
[I830_CTXREG_VF
] = v0
;
194 i830
->state
.Ctx
[I830_CTXREG_VF2
] = v2
;
195 i830
->state
.Ctx
[I830_CTXREG_MCSB1
] = mcsb1
;
196 RENDERINPUTS_COPY(i830
->last_index_bitset
, index_bitset
);
198 k
= i830_check_vertex_size(intel
, intel
->vertex_size
);
204 i830_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
206 struct i830_context
*i830
= i830_context(&intel
->ctx
);
207 GLuint st1
= i830
->state
.Stipple
[I830_STPREG_ST1
];
213 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
222 i830
->intel
.reduced_primitive
= rprim
;
224 if (st1
!= i830
->state
.Stipple
[I830_STPREG_ST1
]) {
225 INTEL_FIREVERTICES(intel
);
227 I830_STATECHANGE(i830
, I830_UPLOAD_STIPPLE
);
228 i830
->state
.Stipple
[I830_STPREG_ST1
] = st1
;
232 /* Pull apart the vertex format registers and figure out how large a
233 * vertex is supposed to be.
236 i830_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
238 struct i830_context
*i830
= i830_context(&intel
->ctx
);
239 int vft0
= i830
->current
->Ctx
[I830_CTXREG_VF
];
240 int vft1
= i830
->current
->Ctx
[I830_CTXREG_VF2
];
241 int nrtex
= (vft0
& VFT0_TEX_COUNT_MASK
) >> VFT0_TEX_COUNT_SHIFT
;
244 switch (vft0
& VFT0_XYZW_MASK
) {
258 fprintf(stderr
, "no xyzw specified\n");
262 if (vft0
& VFT0_SPEC
)
264 if (vft0
& VFT0_DIFFUSE
)
266 if (vft0
& VFT0_DEPTH_OFFSET
)
268 if (vft0
& VFT0_POINT_WIDTH
)
271 for (i
= 0; i
< nrtex
; i
++) {
272 switch (vft1
& VFT1_TEX0_MASK
) {
286 vft1
>>= VFT1_TEX1_SHIFT
;
290 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
292 return sz
== expected
;
296 i830_emit_invarient_state(struct intel_context
*intel
)
300 BEGIN_BATCH(40, IGNORE_CLIPRECTS
);
302 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
305 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
308 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
311 OUT_BATCH(_3DSTATE_FOG_MODE_CMD
);
312 OUT_BATCH(FOGFUNC_ENABLE
|
313 FOG_LINEAR_CONST
| FOGSRC_INDEX_Z
| ENABLE_FOG_DENSITY
);
318 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
320 DISABLE_TEX_STREAM_BUMP
|
321 ENABLE_TEX_STREAM_COORD_SET
|
322 TEX_STREAM_COORD_SET(0) |
323 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(0));
324 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
326 DISABLE_TEX_STREAM_BUMP
|
327 ENABLE_TEX_STREAM_COORD_SET
|
328 TEX_STREAM_COORD_SET(1) |
329 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(1));
330 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
332 DISABLE_TEX_STREAM_BUMP
|
333 ENABLE_TEX_STREAM_COORD_SET
|
334 TEX_STREAM_COORD_SET(2) |
335 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(2));
336 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
338 DISABLE_TEX_STREAM_BUMP
|
339 ENABLE_TEX_STREAM_COORD_SET
|
340 TEX_STREAM_COORD_SET(3) |
341 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(3));
343 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
344 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(0));
345 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
346 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(1));
347 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
348 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(2));
349 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
350 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(3));
352 OUT_BATCH(_3DSTATE_RASTER_RULES_CMD
|
353 ENABLE_POINT_RASTER_RULE
|
354 OGL_POINT_RASTER_RULE
|
355 ENABLE_LINE_STRIP_PROVOKE_VRTX
|
356 ENABLE_TRI_FAN_PROVOKE_VRTX
|
357 ENABLE_TRI_STRIP_PROVOKE_VRTX
|
358 LINE_STRIP_PROVOKE_VRTX(1) |
359 TRI_FAN_PROVOKE_VRTX(2) | TRI_STRIP_PROVOKE_VRTX(2));
361 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM
);
362 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM
| DISABLE_PERSPECTIVE_DIVIDE
);
364 OUT_BATCH(_3DSTATE_W_STATE_CMD
);
365 OUT_BATCH(MAGIC_W_STATE_DWORD1
);
366 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
369 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD
);
370 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
376 #define emit( intel, state, size ) \
377 intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
380 get_dirty(struct i830_hw_state
*state
)
382 return state
->active
& ~state
->emitted
;
386 get_state_size(struct i830_hw_state
*state
)
388 GLuint dirty
= get_dirty(state
);
392 if (dirty
& I830_UPLOAD_INVARIENT
)
393 sz
+= 40 * sizeof(int);
395 if (dirty
& I830_UPLOAD_CTX
)
396 sz
+= sizeof(state
->Ctx
);
398 if (dirty
& I830_UPLOAD_BUFFERS
)
399 sz
+= sizeof(state
->Buffer
);
401 if (dirty
& I830_UPLOAD_STIPPLE
)
402 sz
+= sizeof(state
->Stipple
);
404 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
405 if ((dirty
& I830_UPLOAD_TEX(i
)))
406 sz
+= sizeof(state
->Tex
[i
]);
408 if (dirty
& I830_UPLOAD_TEXBLEND(i
))
409 sz
+= state
->TexBlendWordsUsed
[i
] * 4;
416 /* Push the state into the sarea and/or texture memory.
419 i830_emit_state(struct intel_context
*intel
)
421 struct i830_context
*i830
= i830_context(&intel
->ctx
);
422 struct i830_hw_state
*state
= i830
->current
;
425 GET_CURRENT_CONTEXT(ctx
);
427 dri_bo
*aper_array
[3 + I830_TEX_UNITS
];
430 /* We don't hold the lock at this point, so want to make sure that
431 * there won't be a buffer wrap between the state emits and the primitive
434 * It might be better to talk about explicit places where
435 * scheduling is allowed, rather than assume that it is whenever a
436 * batchbuffer fills up.
438 * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
439 * will be emitted under.
441 intel_batchbuffer_require_space(intel
->batch
,
442 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
447 dirty
= get_dirty(state
);
449 aper_array
[aper_count
++] = intel
->batch
->buf
;
450 if (dirty
& I830_UPLOAD_BUFFERS
) {
451 aper_array
[aper_count
++] = state
->draw_region
->buffer
;
452 aper_array
[aper_count
++] = state
->depth_region
->buffer
;
455 for (i
= 0; i
< I830_TEX_UNITS
; i
++)
456 if (dirty
& I830_UPLOAD_TEX(i
)) {
457 if (state
->tex_buffer
[i
]) {
458 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
462 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
465 intel_batchbuffer_flush(intel
->batch
);
468 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i830 emit state");
474 /* Do this here as we may have flushed the batchbuffer above,
475 * causing more state to be dirty!
477 dirty
= get_dirty(state
);
478 state
->emitted
|= dirty
;
479 assert(get_dirty(state
) == 0);
481 if (dirty
& I830_UPLOAD_INVARIENT
) {
482 DBG("I830_UPLOAD_INVARIENT:\n");
483 i830_emit_invarient_state(intel
);
486 if (dirty
& I830_UPLOAD_CTX
) {
487 DBG("I830_UPLOAD_CTX:\n");
488 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
492 if (dirty
& I830_UPLOAD_BUFFERS
) {
493 DBG("I830_UPLOAD_BUFFERS:\n");
494 BEGIN_BATCH(I830_DEST_SETUP_SIZE
+ 2, IGNORE_CLIPRECTS
);
495 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR0
]);
496 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR1
]);
497 OUT_RELOC(state
->draw_region
->buffer
,
498 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
499 state
->draw_region
->draw_offset
);
501 if (state
->depth_region
) {
502 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR0
]);
503 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR1
]);
504 OUT_RELOC(state
->depth_region
->buffer
,
505 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
506 state
->depth_region
->draw_offset
);
509 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV0
]);
510 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV1
]);
511 OUT_BATCH(state
->Buffer
[I830_DESTREG_SENABLE
]);
512 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR0
]);
513 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR1
]);
514 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR2
]);
518 if (dirty
& I830_UPLOAD_STIPPLE
) {
519 DBG("I830_UPLOAD_STIPPLE:\n");
520 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
523 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
524 if ((dirty
& I830_UPLOAD_TEX(i
))) {
525 DBG("I830_UPLOAD_TEX(%d):\n", i
);
527 BEGIN_BATCH(I830_TEX_SETUP_SIZE
+ 1, IGNORE_CLIPRECTS
);
528 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0LI
]);
530 if (state
->tex_buffer
[i
]) {
531 OUT_RELOC(state
->tex_buffer
[i
],
532 I915_GEM_DOMAIN_SAMPLER
, 0,
533 state
->tex_offset
[i
] | TM0S0_USE_FENCE
);
535 else if (state
== &i830
->meta
) {
540 OUT_BATCH(state
->tex_offset
[i
]);
543 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S1
]);
544 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S2
]);
545 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S3
]);
546 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S4
]);
547 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_MCS
]);
548 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_CUBE
]);
551 if (dirty
& I830_UPLOAD_TEXBLEND(i
)) {
552 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i
,
553 state
->TexBlendWordsUsed
[i
]);
554 emit(intel
, state
->TexBlend
[i
], state
->TexBlendWordsUsed
[i
] * 4);
558 intel
->batch
->dirty_state
&= ~dirty
;
559 assert(get_dirty(state
) == 0);
560 assert((intel
->batch
->dirty_state
& (1<<1)) == 0);
564 i830_destroy_context(struct intel_context
*intel
)
567 struct i830_context
*i830
= i830_context(&intel
->ctx
);
569 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
570 if (i830
->state
.tex_buffer
[i
] != NULL
) {
571 dri_bo_unreference(i830
->state
.tex_buffer
[i
]);
572 i830
->state
.tex_buffer
[i
] = NULL
;
576 _tnl_free_vertices(&intel
->ctx
);
581 i830_state_draw_region(struct intel_context
*intel
,
582 struct i830_hw_state
*state
,
583 struct intel_region
*color_region
,
584 struct intel_region
*depth_region
)
586 struct i830_context
*i830
= i830_context(&intel
->ctx
);
589 ASSERT(state
== &i830
->state
|| state
== &i830
->meta
);
591 if (state
->draw_region
!= color_region
) {
592 intel_region_release(&state
->draw_region
);
593 intel_region_reference(&state
->draw_region
, color_region
);
595 if (state
->depth_region
!= depth_region
) {
596 intel_region_release(&state
->depth_region
);
597 intel_region_reference(&state
->depth_region
, depth_region
);
601 * Set stride/cpp values
604 state
->Buffer
[I830_DESTREG_CBUFADDR0
] = _3DSTATE_BUF_INFO_CMD
;
605 state
->Buffer
[I830_DESTREG_CBUFADDR1
] =
606 (BUF_3D_ID_COLOR_BACK
|
607 BUF_3D_PITCH(color_region
->pitch
* color_region
->cpp
) |
612 state
->Buffer
[I830_DESTREG_DBUFADDR0
] = _3DSTATE_BUF_INFO_CMD
;
613 state
->Buffer
[I830_DESTREG_DBUFADDR1
] =
615 BUF_3D_PITCH(depth_region
->pitch
* depth_region
->cpp
) |
620 * Compute/set I830_DESTREG_DV1 value
622 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
623 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z
); /* .5 */
625 if (color_region
&& color_region
->cpp
== 4) {
631 if (depth_region
&& depth_region
->cpp
== 4) {
632 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
635 value
|= DEPTH_FRMT_16_FIXED
;
637 state
->Buffer
[I830_DESTREG_DV1
] = value
;
639 I830_STATECHANGE(i830
, I830_UPLOAD_BUFFERS
);
646 i830_set_draw_region(struct intel_context
*intel
,
647 struct intel_region
*color_regions
[],
648 struct intel_region
*depth_region
,
651 struct i830_context
*i830
= i830_context(&intel
->ctx
);
652 i830_state_draw_region(intel
, &i830
->state
, color_regions
[0], depth_region
);
657 i830_update_color_z_regions(intelContextPtr intel
,
658 const intelRegion
* colorRegion
,
659 const intelRegion
* depthRegion
)
661 i830ContextPtr i830
= I830_CONTEXT(intel
);
663 i830
->state
.Buffer
[I830_DESTREG_CBUFADDR1
] =
664 (BUF_3D_ID_COLOR_BACK
| BUF_3D_PITCH(colorRegion
->pitch
) |
666 i830
->state
.Buffer
[I830_DESTREG_CBUFADDR2
] = colorRegion
->offset
;
668 i830
->state
.Buffer
[I830_DESTREG_DBUFADDR1
] =
669 (BUF_3D_ID_DEPTH
| BUF_3D_PITCH(depthRegion
->pitch
) | BUF_3D_USE_FENCE
);
670 i830
->state
.Buffer
[I830_DESTREG_DBUFADDR2
] = depthRegion
->offset
;
675 /* This isn't really handled at the moment.
678 i830_new_batch(struct intel_context
*intel
)
680 struct i830_context
*i830
= i830_context(&intel
->ctx
);
681 i830
->state
.emitted
= 0;
683 /* Check that we didn't just wrap our batchbuffer at a bad time. */
684 assert(!intel
->no_batch_wrap
);
692 return MI_FLUSH
| FLUSH_MAP_CACHE
;
697 i830_assert_not_dirty( struct intel_context
*intel
)
699 struct i830_context
*i830
= i830_context(&intel
->ctx
);
700 struct i830_hw_state
*state
= i830
->current
;
701 assert(!get_dirty(state
));
705 i830_note_unlock( struct intel_context
*intel
)
711 i830InitVtbl(struct i830_context
*i830
)
713 i830
->intel
.vtbl
.check_vertex_size
= i830_check_vertex_size
;
714 i830
->intel
.vtbl
.destroy
= i830_destroy_context
;
715 i830
->intel
.vtbl
.emit_state
= i830_emit_state
;
716 i830
->intel
.vtbl
.new_batch
= i830_new_batch
;
717 i830
->intel
.vtbl
.reduced_primitive_state
= i830_reduced_primitive_state
;
718 i830
->intel
.vtbl
.set_draw_region
= i830_set_draw_region
;
719 i830
->intel
.vtbl
.update_texture_state
= i830UpdateTextureState
;
720 i830
->intel
.vtbl
.flush_cmd
= i830_flush_cmd
;
721 i830
->intel
.vtbl
.render_start
= i830_render_start
;
722 i830
->intel
.vtbl
.render_prevalidate
= i830_render_prevalidate
;
723 i830
->intel
.vtbl
.assert_not_dirty
= i830_assert_not_dirty
;
724 i830
->intel
.vtbl
.note_unlock
= i830_note_unlock
;
725 i830
->intel
.vtbl
.finish_batch
= intel_finish_vb
;