1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "i830_context.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_regions.h"
32 #include "intel_tris.h"
33 #include "intel_fbo.h"
34 #include "tnl/t_context.h"
35 #include "tnl/t_vertex.h"
37 #define FILE_DEBUG_FLAG DEBUG_STATE
39 static GLboolean
i830_check_vertex_size(struct intel_context
*intel
,
42 #define SZ_TO_HW(sz) ((sz-2)&0x3)
43 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
44 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
46 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
47 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
48 intel->vertex_attr_count++; \
52 #define EMIT_PAD( N ) \
54 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
55 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
56 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
57 intel->vertex_attr_count++; \
61 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
62 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
65 i830_render_prevalidate(struct intel_context
*intel
)
70 i830_render_start(struct intel_context
*intel
)
72 struct gl_context
*ctx
= &intel
->ctx
;
73 struct i830_context
*i830
= i830_context(ctx
);
74 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
75 struct vertex_buffer
*VB
= &tnl
->vb
;
76 DECLARE_RENDERINPUTS(index_bitset
);
77 GLuint v0
= _3DSTATE_VFT0_CMD
;
78 GLuint v2
= _3DSTATE_VFT1_CMD
;
81 RENDERINPUTS_COPY(index_bitset
, tnl
->render_inputs_bitset
);
85 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
86 intel
->vertex_attr_count
= 0;
88 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
89 * build up a hardware vertex.
91 if (RENDERINPUTS_TEST_RANGE(index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
92 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_4F_VIEWPORT
, VFT0_XYZW
);
93 intel
->coloroffset
= 4;
96 EMIT_ATTR(_TNL_ATTRIB_POS
, EMIT_3F_VIEWPORT
, VFT0_XYZ
);
97 intel
->coloroffset
= 3;
100 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_POINTSIZE
)) {
101 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE
, EMIT_1F
, VFT0_POINT_WIDTH
);
104 EMIT_ATTR(_TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_BGRA
, VFT0_DIFFUSE
);
106 intel
->specoffset
= 0;
107 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_COLOR1
) ||
108 RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_FOG
)) {
109 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_COLOR1
)) {
110 intel
->specoffset
= intel
->coloroffset
+ 1;
111 EMIT_ATTR(_TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
, VFT0_SPEC
);
116 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_FOG
))
117 EMIT_ATTR(_TNL_ATTRIB_FOG
, EMIT_1UB_1F
, VFT0_SPEC
);
122 if (RENDERINPUTS_TEST_RANGE(index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
125 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
126 if (RENDERINPUTS_TEST(index_bitset
, _TNL_ATTRIB_TEX(i
))) {
127 GLuint sz
= VB
->AttribPtr
[_TNL_ATTRIB_TEX0
+ i
]->size
;
129 GLuint mcs
= (i830
->state
.Tex
[i
][I830_TEXREG_MCS
] &
137 mcs
|= TEXCOORDTYPE_CARTESIAN
;
142 mcs
|= TEXCOORDTYPE_VECTOR
;
147 mcs
|= TEXCOORDTYPE_HOMOGENEOUS
;
154 EMIT_ATTR(_TNL_ATTRIB_TEX0
+ i
, emit
, 0);
155 v2
|= VRTX_TEX_SET_FMT(count
, SZ_TO_HW(sz
));
156 mcsb1
|= (count
+ 8) << (i
* 4);
158 if (mcs
!= i830
->state
.Tex
[i
][I830_TEXREG_MCS
]) {
159 I830_STATECHANGE(i830
, I830_UPLOAD_TEX(i
));
160 i830
->state
.Tex
[i
][I830_TEXREG_MCS
] = mcs
;
167 v0
|= VFT0_TEX_COUNT(count
);
170 /* Only need to change the vertex emit code if there has been a
171 * statechange to a new hardware vertex format:
173 if (v0
!= i830
->state
.Ctx
[I830_CTXREG_VF
] ||
174 v2
!= i830
->state
.Ctx
[I830_CTXREG_VF2
] ||
175 mcsb1
!= i830
->state
.Ctx
[I830_CTXREG_MCSB1
] ||
176 !RENDERINPUTS_EQUAL(index_bitset
, i830
->last_index_bitset
)) {
179 I830_STATECHANGE(i830
, I830_UPLOAD_CTX
);
181 /* Must do this *after* statechange, so as not to affect
182 * buffered vertices reliant on the old state:
185 _tnl_install_attrs(ctx
,
187 intel
->vertex_attr_count
,
188 intel
->ViewportMatrix
.m
, 0);
190 intel
->vertex_size
>>= 2;
192 i830
->state
.Ctx
[I830_CTXREG_VF
] = v0
;
193 i830
->state
.Ctx
[I830_CTXREG_VF2
] = v2
;
194 i830
->state
.Ctx
[I830_CTXREG_MCSB1
] = mcsb1
;
195 RENDERINPUTS_COPY(i830
->last_index_bitset
, index_bitset
);
197 k
= i830_check_vertex_size(intel
, intel
->vertex_size
);
203 i830_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
205 struct i830_context
*i830
= i830_context(&intel
->ctx
);
206 GLuint st1
= i830
->state
.Stipple
[I830_STPREG_ST1
];
212 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
221 i830
->intel
.reduced_primitive
= rprim
;
223 if (st1
!= i830
->state
.Stipple
[I830_STPREG_ST1
]) {
224 INTEL_FIREVERTICES(intel
);
226 I830_STATECHANGE(i830
, I830_UPLOAD_STIPPLE
);
227 i830
->state
.Stipple
[I830_STPREG_ST1
] = st1
;
231 /* Pull apart the vertex format registers and figure out how large a
232 * vertex is supposed to be.
235 i830_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
237 struct i830_context
*i830
= i830_context(&intel
->ctx
);
238 int vft0
= i830
->state
.Ctx
[I830_CTXREG_VF
];
239 int vft1
= i830
->state
.Ctx
[I830_CTXREG_VF2
];
240 int nrtex
= (vft0
& VFT0_TEX_COUNT_MASK
) >> VFT0_TEX_COUNT_SHIFT
;
243 switch (vft0
& VFT0_XYZW_MASK
) {
257 fprintf(stderr
, "no xyzw specified\n");
261 if (vft0
& VFT0_SPEC
)
263 if (vft0
& VFT0_DIFFUSE
)
265 if (vft0
& VFT0_DEPTH_OFFSET
)
267 if (vft0
& VFT0_POINT_WIDTH
)
270 for (i
= 0; i
< nrtex
; i
++) {
271 switch (vft1
& VFT1_TEX0_MASK
) {
285 vft1
>>= VFT1_TEX1_SHIFT
;
289 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
291 return sz
== expected
;
295 i830_emit_invarient_state(struct intel_context
*intel
)
301 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
304 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
307 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
310 OUT_BATCH(_3DSTATE_FOG_MODE_CMD
);
311 OUT_BATCH(FOGFUNC_ENABLE
|
312 FOG_LINEAR_CONST
| FOGSRC_INDEX_Z
| ENABLE_FOG_DENSITY
);
317 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
319 DISABLE_TEX_STREAM_BUMP
|
320 ENABLE_TEX_STREAM_COORD_SET
|
321 TEX_STREAM_COORD_SET(0) |
322 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(0));
323 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
325 DISABLE_TEX_STREAM_BUMP
|
326 ENABLE_TEX_STREAM_COORD_SET
|
327 TEX_STREAM_COORD_SET(1) |
328 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(1));
329 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
331 DISABLE_TEX_STREAM_BUMP
|
332 ENABLE_TEX_STREAM_COORD_SET
|
333 TEX_STREAM_COORD_SET(2) |
334 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(2));
335 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD
|
337 DISABLE_TEX_STREAM_BUMP
|
338 ENABLE_TEX_STREAM_COORD_SET
|
339 TEX_STREAM_COORD_SET(3) |
340 ENABLE_TEX_STREAM_MAP_IDX
| TEX_STREAM_MAP_IDX(3));
342 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
343 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(0));
344 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
345 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(1));
346 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
347 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(2));
348 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM
);
349 OUT_BATCH(DISABLE_TEX_TRANSFORM
| TEXTURE_SET(3));
351 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM
);
352 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM
| DISABLE_PERSPECTIVE_DIVIDE
);
354 OUT_BATCH(_3DSTATE_W_STATE_CMD
);
355 OUT_BATCH(MAGIC_W_STATE_DWORD1
);
356 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
359 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD
);
360 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
366 #define emit( intel, state, size ) \
367 intel_batchbuffer_data(intel->batch, state, size, false)
370 get_dirty(struct i830_hw_state
*state
)
372 return state
->active
& ~state
->emitted
;
376 get_state_size(struct i830_hw_state
*state
)
378 GLuint dirty
= get_dirty(state
);
382 if (dirty
& I830_UPLOAD_INVARIENT
)
383 sz
+= 40 * sizeof(int);
385 if (dirty
& I830_UPLOAD_RASTER_RULES
)
386 sz
+= sizeof(state
->RasterRules
);
388 if (dirty
& I830_UPLOAD_CTX
)
389 sz
+= sizeof(state
->Ctx
);
391 if (dirty
& I830_UPLOAD_BUFFERS
)
392 sz
+= sizeof(state
->Buffer
);
394 if (dirty
& I830_UPLOAD_STIPPLE
)
395 sz
+= sizeof(state
->Stipple
);
397 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
398 if ((dirty
& I830_UPLOAD_TEX(i
)))
399 sz
+= sizeof(state
->Tex
[i
]);
401 if (dirty
& I830_UPLOAD_TEXBLEND(i
))
402 sz
+= state
->TexBlendWordsUsed
[i
] * 4;
409 /* Push the state into the sarea and/or texture memory.
412 i830_emit_state(struct intel_context
*intel
)
414 struct i830_context
*i830
= i830_context(&intel
->ctx
);
415 struct i830_hw_state
*state
= &i830
->state
;
418 drm_intel_bo
*aper_array
[3 + I830_TEX_UNITS
];
420 GET_CURRENT_CONTEXT(ctx
);
423 /* We don't hold the lock at this point, so want to make sure that
424 * there won't be a buffer wrap between the state emits and the primitive
427 * It might be better to talk about explicit places where
428 * scheduling is allowed, rather than assume that it is whenever a
429 * batchbuffer fills up.
431 intel_batchbuffer_require_space(intel
->batch
,
432 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
437 dirty
= get_dirty(state
);
439 aper_array
[aper_count
++] = intel
->batch
->buf
;
440 if (dirty
& I830_UPLOAD_BUFFERS
) {
441 aper_array
[aper_count
++] = state
->draw_region
->buffer
;
442 if (state
->depth_region
)
443 aper_array
[aper_count
++] = state
->depth_region
->buffer
;
446 for (i
= 0; i
< I830_TEX_UNITS
; i
++)
447 if (dirty
& I830_UPLOAD_TEX(i
)) {
448 if (state
->tex_buffer
[i
]) {
449 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
453 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
456 intel_batchbuffer_flush(intel
->batch
);
459 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i830 emit state");
465 /* Do this here as we may have flushed the batchbuffer above,
466 * causing more state to be dirty!
468 dirty
= get_dirty(state
);
469 state
->emitted
|= dirty
;
470 assert(get_dirty(state
) == 0);
472 if (dirty
& I830_UPLOAD_INVARIENT
) {
473 DBG("I830_UPLOAD_INVARIENT:\n");
474 i830_emit_invarient_state(intel
);
477 if (dirty
& I830_UPLOAD_RASTER_RULES
) {
478 DBG("I830_UPLOAD_RASTER_RULES:\n");
479 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
482 if (dirty
& I830_UPLOAD_CTX
) {
483 DBG("I830_UPLOAD_CTX:\n");
484 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
488 if (dirty
& I830_UPLOAD_BUFFERS
) {
491 DBG("I830_UPLOAD_BUFFERS:\n");
493 if (state
->depth_region
)
497 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR0
]);
498 OUT_BATCH(state
->Buffer
[I830_DESTREG_CBUFADDR1
]);
499 OUT_RELOC(state
->draw_region
->buffer
,
500 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
502 if (state
->depth_region
) {
503 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR0
]);
504 OUT_BATCH(state
->Buffer
[I830_DESTREG_DBUFADDR1
]);
505 OUT_RELOC(state
->depth_region
->buffer
,
506 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
509 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV0
]);
510 OUT_BATCH(state
->Buffer
[I830_DESTREG_DV1
]);
511 OUT_BATCH(state
->Buffer
[I830_DESTREG_SENABLE
]);
512 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR0
]);
513 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR1
]);
514 OUT_BATCH(state
->Buffer
[I830_DESTREG_SR2
]);
516 assert(state
->Buffer
[I830_DESTREG_DRAWRECT0
] != MI_NOOP
);
517 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT0
]);
518 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT1
]);
519 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT2
]);
520 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT3
]);
521 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT4
]);
522 OUT_BATCH(state
->Buffer
[I830_DESTREG_DRAWRECT5
]);
526 if (dirty
& I830_UPLOAD_STIPPLE
) {
527 DBG("I830_UPLOAD_STIPPLE:\n");
528 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
531 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
532 if ((dirty
& I830_UPLOAD_TEX(i
))) {
533 DBG("I830_UPLOAD_TEX(%d):\n", i
);
535 BEGIN_BATCH(I830_TEX_SETUP_SIZE
+ 1);
536 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0LI
]);
538 OUT_RELOC(state
->tex_buffer
[i
],
539 I915_GEM_DOMAIN_SAMPLER
, 0,
540 state
->tex_offset
[i
]);
542 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S1
]);
543 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S2
]);
544 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S3
]);
545 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_TM0S4
]);
546 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_MCS
]);
547 OUT_BATCH(state
->Tex
[i
][I830_TEXREG_CUBE
]);
552 if (dirty
& I830_UPLOAD_TEXBLEND(i
)) {
553 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i
,
554 state
->TexBlendWordsUsed
[i
]);
555 emit(intel
, state
->TexBlend
[i
], state
->TexBlendWordsUsed
[i
] * 4);
559 intel
->batch
->dirty_state
&= ~dirty
;
560 assert(get_dirty(state
) == 0);
561 assert((intel
->batch
->dirty_state
& (1<<1)) == 0);
565 i830_destroy_context(struct intel_context
*intel
)
568 struct i830_context
*i830
= i830_context(&intel
->ctx
);
570 intel_region_release(&i830
->state
.draw_region
);
571 intel_region_release(&i830
->state
.depth_region
);
573 for (i
= 0; i
< I830_TEX_UNITS
; i
++) {
574 if (i830
->state
.tex_buffer
[i
] != NULL
) {
575 drm_intel_bo_unreference(i830
->state
.tex_buffer
[i
]);
576 i830
->state
.tex_buffer
[i
] = NULL
;
580 _tnl_free_vertices(&intel
->ctx
);
583 static uint32_t i830_render_target_format_for_mesa_format
[MESA_FORMAT_COUNT
] =
585 [MESA_FORMAT_ARGB8888
] = DV_PF_8888
,
586 [MESA_FORMAT_XRGB8888
] = DV_PF_8888
,
587 [MESA_FORMAT_RGB565
] = DV_PF_565
,
588 [MESA_FORMAT_ARGB1555
] = DV_PF_1555
,
589 [MESA_FORMAT_ARGB4444
] = DV_PF_4444
,
593 i830_render_target_supported(gl_format format
)
595 if (format
== MESA_FORMAT_S8_Z24
||
596 format
== MESA_FORMAT_X8_Z24
||
597 format
== MESA_FORMAT_Z16
) {
601 return i830_render_target_format_for_mesa_format
[format
] != 0;
605 i830_set_draw_region(struct intel_context
*intel
,
606 struct intel_region
*color_regions
[],
607 struct intel_region
*depth_region
,
610 struct i830_context
*i830
= i830_context(&intel
->ctx
);
611 struct gl_context
*ctx
= &intel
->ctx
;
612 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
613 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
615 struct i830_hw_state
*state
= &i830
->state
;
616 uint32_t draw_x
, draw_y
;
618 if (state
->draw_region
!= color_regions
[0]) {
619 intel_region_release(&state
->draw_region
);
620 intel_region_reference(&state
->draw_region
, color_regions
[0]);
622 if (state
->depth_region
!= depth_region
) {
623 intel_region_release(&state
->depth_region
);
624 intel_region_reference(&state
->depth_region
, depth_region
);
628 * Set stride/cpp values
630 i915_set_buf_info_for_region(&state
->Buffer
[I830_DESTREG_CBUFADDR0
],
631 color_regions
[0], BUF_3D_ID_COLOR_BACK
);
633 i915_set_buf_info_for_region(&state
->Buffer
[I830_DESTREG_DBUFADDR0
],
634 depth_region
, BUF_3D_ID_DEPTH
);
637 * Compute/set I830_DESTREG_DV1 value
639 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
640 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z
); /* .5 */
643 value
|= i830_render_target_format_for_mesa_format
[irb
->Base
.Format
];
646 if (depth_region
&& depth_region
->cpp
== 4) {
647 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
650 value
|= DEPTH_FRMT_16_FIXED
;
652 state
->Buffer
[I830_DESTREG_DV1
] = value
;
654 /* We set up the drawing rectangle to be offset into the color
655 * region's location in the miptree. If it doesn't match with
656 * depth's offsets, we can't render to it.
658 * (Well, not actually true -- the hw grew a bit to let depth's
659 * offset get forced to 0,0. We may want to use that if people are
660 * hitting that case. Also, some configurations may be supportable
661 * by tweaking the start offset of the buffers around, which we
662 * can't do in general due to tiling)
664 FALLBACK(intel
, I830_FALLBACK_DRAW_OFFSET
,
665 (depth_region
&& color_regions
[0]) &&
666 (depth_region
->draw_x
!= color_regions
[0]->draw_x
||
667 depth_region
->draw_y
!= color_regions
[0]->draw_y
));
669 if (color_regions
[0]) {
670 draw_x
= color_regions
[0]->draw_x
;
671 draw_y
= color_regions
[0]->draw_y
;
672 } else if (depth_region
) {
673 draw_x
= depth_region
->draw_x
;
674 draw_y
= depth_region
->draw_y
;
680 state
->Buffer
[I830_DESTREG_DRAWRECT0
] = _3DSTATE_DRAWRECT_INFO
;
681 state
->Buffer
[I830_DESTREG_DRAWRECT1
] = 0;
682 state
->Buffer
[I830_DESTREG_DRAWRECT2
] = (draw_y
<< 16) | draw_x
;
683 state
->Buffer
[I830_DESTREG_DRAWRECT3
] =
684 ((ctx
->DrawBuffer
->Width
+ draw_x
) & 0xffff) |
685 ((ctx
->DrawBuffer
->Height
+ draw_y
) << 16);
686 state
->Buffer
[I830_DESTREG_DRAWRECT4
] = (draw_y
<< 16) | draw_x
;
687 state
->Buffer
[I830_DESTREG_DRAWRECT5
] = MI_NOOP
;
689 I830_STATECHANGE(i830
, I830_UPLOAD_BUFFERS
);
692 /* This isn't really handled at the moment.
695 i830_new_batch(struct intel_context
*intel
)
697 struct i830_context
*i830
= i830_context(&intel
->ctx
);
698 i830
->state
.emitted
= 0;
702 i830_assert_not_dirty( struct intel_context
*intel
)
704 struct i830_context
*i830
= i830_context(&intel
->ctx
);
705 assert(!get_dirty(&i830
->state
));
710 i830_invalidate_state(struct intel_context
*intel
, GLuint new_state
)
712 if (new_state
& _NEW_LIGHT
)
713 i830_update_provoking_vertex(&intel
->ctx
);
717 i830InitVtbl(struct i830_context
*i830
)
719 i830
->intel
.vtbl
.check_vertex_size
= i830_check_vertex_size
;
720 i830
->intel
.vtbl
.destroy
= i830_destroy_context
;
721 i830
->intel
.vtbl
.emit_state
= i830_emit_state
;
722 i830
->intel
.vtbl
.new_batch
= i830_new_batch
;
723 i830
->intel
.vtbl
.reduced_primitive_state
= i830_reduced_primitive_state
;
724 i830
->intel
.vtbl
.set_draw_region
= i830_set_draw_region
;
725 i830
->intel
.vtbl
.update_texture_state
= i830UpdateTextureState
;
726 i830
->intel
.vtbl
.render_start
= i830_render_start
;
727 i830
->intel
.vtbl
.render_prevalidate
= i830_render_prevalidate
;
728 i830
->intel
.vtbl
.assert_not_dirty
= i830_assert_not_dirty
;
729 i830
->intel
.vtbl
.finish_batch
= intel_finish_vb
;
730 i830
->intel
.vtbl
.invalidate_state
= i830_invalidate_state
;
731 i830
->intel
.vtbl
.render_target_supported
= i830_render_target_supported
;