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i915: Convert to use GLbitfield64 directly.
[mesa.git] / src / mesa / drivers / dri / i915 / i830_vtbl.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "i830_context.h"
29 #include "i830_reg.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_regions.h"
33 #include "intel_tris.h"
34 #include "intel_fbo.h"
35 #include "intel_buffers.h"
36 #include "tnl/tnl.h"
37 #include "tnl/t_context.h"
38 #include "tnl/t_vertex.h"
39 #include "swrast_setup/swrast_setup.h"
40 #include "main/renderbuffer.h"
41 #include "main/framebuffer.h"
42
43 #define FILE_DEBUG_FLAG DEBUG_STATE
44
45 static bool i830_check_vertex_size(struct intel_context *intel,
46 GLuint expected);
47
48 #define SZ_TO_HW(sz) ((sz-2)&0x3)
49 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
50 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
51 do { \
52 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
53 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
54 intel->vertex_attr_count++; \
55 v0 |= V0; \
56 } while (0)
57
58 #define EMIT_PAD( N ) \
59 do { \
60 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
61 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
62 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
63 intel->vertex_attr_count++; \
64 } while (0)
65
66
67 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
68 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
69
70 static void
71 i830_render_prevalidate(struct intel_context *intel)
72 {
73 }
74
75 static void
76 i830_render_start(struct intel_context *intel)
77 {
78 struct gl_context *ctx = &intel->ctx;
79 struct i830_context *i830 = i830_context(ctx);
80 TNLcontext *tnl = TNL_CONTEXT(ctx);
81 struct vertex_buffer *VB = &tnl->vb;
82 GLbitfield64 index_bitset = tnl->render_inputs_bitset;
83 GLuint v0 = _3DSTATE_VFT0_CMD;
84 GLuint v2 = _3DSTATE_VFT1_CMD;
85 GLuint mcsb1 = 0;
86
87 /* Important:
88 */
89 VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
90 intel->vertex_attr_count = 0;
91
92 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
93 * build up a hardware vertex.
94 */
95 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
96 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW);
97 intel->coloroffset = 4;
98 }
99 else {
100 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ);
101 intel->coloroffset = 3;
102 }
103
104 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE)) {
105 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH);
106 }
107
108 EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE);
109
110 intel->specoffset = 0;
111 if (index_bitset & (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) |
112 BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
113 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
114 intel->specoffset = intel->coloroffset + 1;
115 EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC);
116 }
117 else
118 EMIT_PAD(3);
119
120 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG))
121 EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC);
122 else
123 EMIT_PAD(1);
124 }
125
126 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
127 int i, count = 0;
128
129 for (i = 0; i < I830_TEX_UNITS; i++) {
130 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
131 GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
132 GLuint emit;
133 GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
134 ~TEXCOORDTYPE_MASK);
135
136 switch (sz) {
137 case 1:
138 case 2:
139 emit = EMIT_2F;
140 sz = 2;
141 mcs |= TEXCOORDTYPE_CARTESIAN;
142 break;
143 case 3:
144 emit = EMIT_3F;
145 sz = 3;
146 mcs |= TEXCOORDTYPE_VECTOR;
147 break;
148 case 4:
149 emit = EMIT_3F_XYW;
150 sz = 3;
151 mcs |= TEXCOORDTYPE_HOMOGENEOUS;
152 break;
153 default:
154 continue;
155 };
156
157
158 EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
159 v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
160 mcsb1 |= (count + 8) << (i * 4);
161
162 if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) {
163 I830_STATECHANGE(i830, I830_UPLOAD_TEX(i));
164 i830->state.Tex[i][I830_TEXREG_MCS] = mcs;
165 }
166
167 count++;
168 }
169 }
170
171 v0 |= VFT0_TEX_COUNT(count);
172 }
173
174 /* Only need to change the vertex emit code if there has been a
175 * statechange to a new hardware vertex format:
176 */
177 if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
178 v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
179 mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
180 index_bitset != i830->last_index_bitset) {
181 int k;
182
183 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
184
185 /* Must do this *after* statechange, so as not to affect
186 * buffered vertices reliant on the old state:
187 */
188 intel->vertex_size =
189 _tnl_install_attrs(ctx,
190 intel->vertex_attrs,
191 intel->vertex_attr_count,
192 intel->ViewportMatrix.m, 0);
193
194 intel->vertex_size >>= 2;
195
196 i830->state.Ctx[I830_CTXREG_VF] = v0;
197 i830->state.Ctx[I830_CTXREG_VF2] = v2;
198 i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
199 i830->last_index_bitset = index_bitset;
200
201 k = i830_check_vertex_size(intel, intel->vertex_size);
202 assert(k);
203 }
204 }
205
206 static void
207 i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
208 {
209 struct i830_context *i830 = i830_context(&intel->ctx);
210 GLuint st1 = i830->state.Stipple[I830_STPREG_ST1];
211
212 st1 &= ~ST1_ENABLE;
213
214 switch (rprim) {
215 case GL_TRIANGLES:
216 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
217 st1 |= ST1_ENABLE;
218 break;
219 case GL_LINES:
220 case GL_POINTS:
221 default:
222 break;
223 }
224
225 i830->intel.reduced_primitive = rprim;
226
227 if (st1 != i830->state.Stipple[I830_STPREG_ST1]) {
228 INTEL_FIREVERTICES(intel);
229
230 I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
231 i830->state.Stipple[I830_STPREG_ST1] = st1;
232 }
233 }
234
235 /* Pull apart the vertex format registers and figure out how large a
236 * vertex is supposed to be.
237 */
238 static bool
239 i830_check_vertex_size(struct intel_context *intel, GLuint expected)
240 {
241 struct i830_context *i830 = i830_context(&intel->ctx);
242 int vft0 = i830->state.Ctx[I830_CTXREG_VF];
243 int vft1 = i830->state.Ctx[I830_CTXREG_VF2];
244 int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT;
245 int i, sz = 0;
246
247 switch (vft0 & VFT0_XYZW_MASK) {
248 case VFT0_XY:
249 sz = 2;
250 break;
251 case VFT0_XYZ:
252 sz = 3;
253 break;
254 case VFT0_XYW:
255 sz = 3;
256 break;
257 case VFT0_XYZW:
258 sz = 4;
259 break;
260 default:
261 fprintf(stderr, "no xyzw specified\n");
262 return 0;
263 }
264
265 if (vft0 & VFT0_SPEC)
266 sz++;
267 if (vft0 & VFT0_DIFFUSE)
268 sz++;
269 if (vft0 & VFT0_DEPTH_OFFSET)
270 sz++;
271 if (vft0 & VFT0_POINT_WIDTH)
272 sz++;
273
274 for (i = 0; i < nrtex; i++) {
275 switch (vft1 & VFT1_TEX0_MASK) {
276 case TEXCOORDFMT_2D:
277 sz += 2;
278 break;
279 case TEXCOORDFMT_3D:
280 sz += 3;
281 break;
282 case TEXCOORDFMT_4D:
283 sz += 4;
284 break;
285 case TEXCOORDFMT_1D:
286 sz += 1;
287 break;
288 }
289 vft1 >>= VFT1_TEX1_SHIFT;
290 }
291
292 if (sz != expected)
293 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
294
295 return sz == expected;
296 }
297
298 static void
299 i830_emit_invarient_state(struct intel_context *intel)
300 {
301 BATCH_LOCALS;
302
303 BEGIN_BATCH(29);
304
305 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
306 OUT_BATCH(0);
307
308 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
309 OUT_BATCH(0);
310
311 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
312 OUT_BATCH(0);
313
314 OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
315 OUT_BATCH(FOGFUNC_ENABLE |
316 FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
317 OUT_BATCH(0);
318 OUT_BATCH(0);
319
320
321 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
322 MAP_UNIT(0) |
323 DISABLE_TEX_STREAM_BUMP |
324 ENABLE_TEX_STREAM_COORD_SET |
325 TEX_STREAM_COORD_SET(0) |
326 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
327 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
328 MAP_UNIT(1) |
329 DISABLE_TEX_STREAM_BUMP |
330 ENABLE_TEX_STREAM_COORD_SET |
331 TEX_STREAM_COORD_SET(1) |
332 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
333 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
334 MAP_UNIT(2) |
335 DISABLE_TEX_STREAM_BUMP |
336 ENABLE_TEX_STREAM_COORD_SET |
337 TEX_STREAM_COORD_SET(2) |
338 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
339 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
340 MAP_UNIT(3) |
341 DISABLE_TEX_STREAM_BUMP |
342 ENABLE_TEX_STREAM_COORD_SET |
343 TEX_STREAM_COORD_SET(3) |
344 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
345
346 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
347 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
348 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
349 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
350 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
351 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
352 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
353 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
354
355 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
356 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
357
358 OUT_BATCH(_3DSTATE_W_STATE_CMD);
359 OUT_BATCH(MAGIC_W_STATE_DWORD1);
360 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
361
362
363 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
364 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
365
366 ADVANCE_BATCH();
367 }
368
369
370 #define emit( intel, state, size ) \
371 intel_batchbuffer_data(intel, state, size, false)
372
373 static GLuint
374 get_dirty(struct i830_hw_state *state)
375 {
376 return state->active & ~state->emitted;
377 }
378
379 static GLuint
380 get_state_size(struct i830_hw_state *state)
381 {
382 GLuint dirty = get_dirty(state);
383 GLuint sz = 0;
384 GLuint i;
385
386 if (dirty & I830_UPLOAD_INVARIENT)
387 sz += 40 * sizeof(int);
388
389 if (dirty & I830_UPLOAD_RASTER_RULES)
390 sz += sizeof(state->RasterRules);
391
392 if (dirty & I830_UPLOAD_CTX)
393 sz += sizeof(state->Ctx);
394
395 if (dirty & I830_UPLOAD_BUFFERS)
396 sz += sizeof(state->Buffer);
397
398 if (dirty & I830_UPLOAD_STIPPLE)
399 sz += sizeof(state->Stipple);
400
401 for (i = 0; i < I830_TEX_UNITS; i++) {
402 if ((dirty & I830_UPLOAD_TEX(i)))
403 sz += sizeof(state->Tex[i]);
404
405 if (dirty & I830_UPLOAD_TEXBLEND(i))
406 sz += state->TexBlendWordsUsed[i] * 4;
407 }
408
409 return sz;
410 }
411
412
413 /* Push the state into the sarea and/or texture memory.
414 */
415 static void
416 i830_emit_state(struct intel_context *intel)
417 {
418 struct i830_context *i830 = i830_context(&intel->ctx);
419 struct i830_hw_state *state = &i830->state;
420 int i, count;
421 GLuint dirty;
422 drm_intel_bo *aper_array[3 + I830_TEX_UNITS];
423 int aper_count;
424 GET_CURRENT_CONTEXT(ctx);
425 BATCH_LOCALS;
426
427 /* We don't hold the lock at this point, so want to make sure that
428 * there won't be a buffer wrap between the state emits and the primitive
429 * emit header.
430 *
431 * It might be better to talk about explicit places where
432 * scheduling is allowed, rather than assume that it is whenever a
433 * batchbuffer fills up.
434 */
435 intel_batchbuffer_require_space(intel,
436 get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
437 false);
438 count = 0;
439 again:
440 aper_count = 0;
441 dirty = get_dirty(state);
442
443 aper_array[aper_count++] = intel->batch.bo;
444 if (dirty & I830_UPLOAD_BUFFERS) {
445 aper_array[aper_count++] = state->draw_region->bo;
446 if (state->depth_region)
447 aper_array[aper_count++] = state->depth_region->bo;
448 }
449
450 for (i = 0; i < I830_TEX_UNITS; i++)
451 if (dirty & I830_UPLOAD_TEX(i)) {
452 if (state->tex_buffer[i]) {
453 aper_array[aper_count++] = state->tex_buffer[i];
454 }
455 }
456
457 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
458 if (count == 0) {
459 count++;
460 intel_batchbuffer_flush(intel);
461 goto again;
462 } else {
463 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state");
464 assert(0);
465 }
466 }
467
468
469 /* Do this here as we may have flushed the batchbuffer above,
470 * causing more state to be dirty!
471 */
472 dirty = get_dirty(state);
473 state->emitted |= dirty;
474 assert(get_dirty(state) == 0);
475
476 if (dirty & I830_UPLOAD_INVARIENT) {
477 DBG("I830_UPLOAD_INVARIENT:\n");
478 i830_emit_invarient_state(intel);
479 }
480
481 if (dirty & I830_UPLOAD_RASTER_RULES) {
482 DBG("I830_UPLOAD_RASTER_RULES:\n");
483 emit(intel, state->RasterRules, sizeof(state->RasterRules));
484 }
485
486 if (dirty & I830_UPLOAD_CTX) {
487 DBG("I830_UPLOAD_CTX:\n");
488 emit(intel, state->Ctx, sizeof(state->Ctx));
489
490 }
491
492 if (dirty & I830_UPLOAD_BUFFERS) {
493 GLuint count = 15;
494
495 DBG("I830_UPLOAD_BUFFERS:\n");
496
497 if (state->depth_region)
498 count += 3;
499
500 BEGIN_BATCH(count);
501 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
502 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
503 OUT_RELOC(state->draw_region->bo,
504 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
505
506 if (state->depth_region) {
507 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
508 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
509 OUT_RELOC(state->depth_region->bo,
510 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
511 }
512
513 OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
514 OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
515 OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
516 OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
517 OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
518 OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
519
520 assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
521 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
522 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
523 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
524 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
525 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
526 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
527 ADVANCE_BATCH();
528 }
529
530 if (dirty & I830_UPLOAD_STIPPLE) {
531 DBG("I830_UPLOAD_STIPPLE:\n");
532 emit(intel, state->Stipple, sizeof(state->Stipple));
533 }
534
535 for (i = 0; i < I830_TEX_UNITS; i++) {
536 if ((dirty & I830_UPLOAD_TEX(i))) {
537 DBG("I830_UPLOAD_TEX(%d):\n", i);
538
539 BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1);
540 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
541
542 OUT_RELOC(state->tex_buffer[i],
543 I915_GEM_DOMAIN_SAMPLER, 0,
544 state->tex_offset[i]);
545
546 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]);
547 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]);
548 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]);
549 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]);
550 OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]);
551 OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]);
552
553 ADVANCE_BATCH();
554 }
555
556 if (dirty & I830_UPLOAD_TEXBLEND(i)) {
557 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
558 state->TexBlendWordsUsed[i]);
559 emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
560 }
561 }
562
563 assert(get_dirty(state) == 0);
564 }
565
566 static void
567 i830_destroy_context(struct intel_context *intel)
568 {
569 GLuint i;
570 struct i830_context *i830 = i830_context(&intel->ctx);
571
572 intel_region_release(&i830->state.draw_region);
573 intel_region_release(&i830->state.depth_region);
574
575 for (i = 0; i < I830_TEX_UNITS; i++) {
576 if (i830->state.tex_buffer[i] != NULL) {
577 drm_intel_bo_unreference(i830->state.tex_buffer[i]);
578 i830->state.tex_buffer[i] = NULL;
579 }
580 }
581
582 _tnl_free_vertices(&intel->ctx);
583 }
584
585 static uint32_t i830_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
586 {
587 [MESA_FORMAT_ARGB8888] = DV_PF_8888,
588 [MESA_FORMAT_XRGB8888] = DV_PF_8888,
589 [MESA_FORMAT_RGB565] = DV_PF_565,
590 [MESA_FORMAT_ARGB1555] = DV_PF_1555,
591 [MESA_FORMAT_ARGB4444] = DV_PF_4444,
592 };
593
594 static bool
595 i830_render_target_supported(struct intel_context *intel, gl_format format)
596 {
597 if (format == MESA_FORMAT_S8_Z24 ||
598 format == MESA_FORMAT_X8_Z24 ||
599 format == MESA_FORMAT_Z16) {
600 return true;
601 }
602
603 return i830_render_target_format_for_mesa_format[format] != 0;
604 }
605
606 static void
607 i830_set_draw_region(struct intel_context *intel,
608 struct intel_region *color_regions[],
609 struct intel_region *depth_region,
610 GLuint num_regions)
611 {
612 struct i830_context *i830 = i830_context(&intel->ctx);
613 struct gl_context *ctx = &intel->ctx;
614 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
615 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
616 struct gl_renderbuffer *drb;
617 struct intel_renderbuffer *idrb = NULL;
618 GLuint value;
619 struct i830_hw_state *state = &i830->state;
620 uint32_t draw_x, draw_y;
621
622 if (state->draw_region != color_regions[0]) {
623 intel_region_reference(&state->draw_region, color_regions[0]);
624 }
625 if (state->depth_region != depth_region) {
626 intel_region_reference(&state->depth_region, depth_region);
627 }
628
629 /*
630 * Set stride/cpp values
631 */
632 i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_CBUFADDR0],
633 color_regions[0], BUF_3D_ID_COLOR_BACK);
634
635 i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_DBUFADDR0],
636 depth_region, BUF_3D_ID_DEPTH);
637
638 /*
639 * Compute/set I830_DESTREG_DV1 value
640 */
641 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
642 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */
643
644 if (irb != NULL) {
645 value |= i830_render_target_format_for_mesa_format[irb->Base.Format];
646 }
647
648 if (depth_region && depth_region->cpp == 4) {
649 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
650 }
651 else {
652 value |= DEPTH_FRMT_16_FIXED;
653 }
654 state->Buffer[I830_DESTREG_DV1] = value;
655
656 drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
657 if (!drb)
658 drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
659
660 if (drb)
661 idrb = intel_renderbuffer(drb);
662
663 /* We set up the drawing rectangle to be offset into the color
664 * region's location in the miptree. If it doesn't match with
665 * depth's offsets, we can't render to it.
666 *
667 * (Well, not actually true -- the hw grew a bit to let depth's
668 * offset get forced to 0,0. We may want to use that if people are
669 * hitting that case. Also, some configurations may be supportable
670 * by tweaking the start offset of the buffers around, which we
671 * can't do in general due to tiling)
672 */
673 FALLBACK(intel, I830_FALLBACK_DRAW_OFFSET,
674 idrb && irb && (idrb->draw_x != irb->draw_x ||
675 idrb->draw_y != irb->draw_y));
676
677 if (irb) {
678 draw_x = irb->draw_x;
679 draw_y = irb->draw_y;
680 } else if (idrb) {
681 draw_x = idrb->draw_x;
682 draw_y = idrb->draw_y;
683 } else {
684 draw_x = 0;
685 draw_y = 0;
686 }
687
688 state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
689 state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
690 state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x;
691 state->Buffer[I830_DESTREG_DRAWRECT3] =
692 ((ctx->DrawBuffer->Width + draw_x) & 0xffff) |
693 ((ctx->DrawBuffer->Height + draw_y) << 16);
694 state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x;
695 state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
696
697 I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
698 }
699
700 /**
701 * Update the hardware state for drawing into a window or framebuffer object.
702 *
703 * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
704 * places within the driver.
705 *
706 * Basically, this needs to be called any time the current framebuffer
707 * changes, the renderbuffers change, or we need to draw into different
708 * color buffers.
709 */
710 static void
711 i830_update_draw_buffer(struct intel_context *intel)
712 {
713 struct gl_context *ctx = &intel->ctx;
714 struct gl_framebuffer *fb = ctx->DrawBuffer;
715 struct intel_region *colorRegions[MAX_DRAW_BUFFERS], *depthRegion = NULL;
716 struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
717
718 if (!fb) {
719 /* this can happen during the initial context initialization */
720 return;
721 }
722
723 irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
724 irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
725
726 /* Do this here, not core Mesa, since this function is called from
727 * many places within the driver.
728 */
729 if (ctx->NewState & _NEW_BUFFERS) {
730 /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
731 _mesa_update_framebuffer(ctx);
732 /* this updates the DrawBuffer's Width/Height if it's a FBO */
733 _mesa_update_draw_buffer_bounds(ctx);
734 }
735
736 if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
737 /* this may occur when we're called by glBindFrameBuffer() during
738 * the process of someone setting up renderbuffers, etc.
739 */
740 /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
741 return;
742 }
743
744 /* How many color buffers are we drawing into?
745 *
746 * If there are zero buffers or the buffer is too big, don't configure any
747 * regions for hardware drawing. We'll fallback to software below. Not
748 * having regions set makes some of the software fallback paths faster.
749 */
750 if ((fb->Width > ctx->Const.MaxRenderbufferSize)
751 || (fb->Height > ctx->Const.MaxRenderbufferSize)
752 || (fb->_NumColorDrawBuffers == 0)) {
753 /* writing to 0 */
754 colorRegions[0] = NULL;
755 }
756 else if (fb->_NumColorDrawBuffers > 1) {
757 int i;
758 struct intel_renderbuffer *irb;
759
760 for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
761 irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]);
762 colorRegions[i] = (irb && irb->mt) ? irb->mt->region : NULL;
763 }
764 }
765 else {
766 /* Get the intel_renderbuffer for the single colorbuffer we're drawing
767 * into.
768 */
769 if (fb->Name == 0) {
770 /* drawing to window system buffer */
771 if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT)
772 colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT);
773 else
774 colorRegions[0] = intel_get_rb_region(fb, BUFFER_BACK_LEFT);
775 }
776 else {
777 /* drawing to user-created FBO */
778 struct intel_renderbuffer *irb;
779 irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
780 colorRegions[0] = (irb && irb->mt->region) ? irb->mt->region : NULL;
781 }
782 }
783
784 if (!colorRegions[0]) {
785 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
786 }
787 else {
788 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false);
789 }
790
791 /* Check for depth fallback. */
792 if (irbDepth && irbDepth->mt) {
793 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
794 depthRegion = irbDepth->mt->region;
795 } else if (irbDepth && !irbDepth->mt) {
796 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true);
797 depthRegion = NULL;
798 } else { /* !irbDepth */
799 /* No fallback is needed because there is no depth buffer. */
800 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
801 depthRegion = NULL;
802 }
803
804 /* Check for stencil fallback. */
805 if (irbStencil && irbStencil->mt) {
806 assert(irbStencil->Base.Format == MESA_FORMAT_S8_Z24);
807 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
808 } else if (irbStencil && !irbStencil->mt) {
809 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
810 } else { /* !irbStencil */
811 /* No fallback is needed because there is no stencil buffer. */
812 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
813 }
814
815 /* If we have a (packed) stencil buffer attached but no depth buffer,
816 * we still need to set up the shared depth/stencil state so we can use it.
817 */
818 if (depthRegion == NULL && irbStencil && irbStencil->mt
819 && irbStencil->Base.Format == MESA_FORMAT_S8_Z24) {
820 depthRegion = irbStencil->mt->region;
821 }
822
823 /*
824 * Update depth and stencil test state
825 */
826 ctx->Driver.Enable(ctx, GL_DEPTH_TEST,
827 (ctx->Depth.Test && fb->Visual.depthBits > 0));
828 ctx->Driver.Enable(ctx, GL_STENCIL_TEST,
829 (ctx->Stencil.Enabled && fb->Visual.stencilBits > 0));
830
831 intel->vtbl.set_draw_region(intel, colorRegions, depthRegion,
832 fb->_NumColorDrawBuffers);
833 intel->NewGLState |= _NEW_BUFFERS;
834
835 /* update viewport since it depends on window size */
836 intelCalcViewport(ctx);
837
838 /* Set state we know depends on drawable parameters:
839 */
840 ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
841 ctx->Scissor.Width, ctx->Scissor.Height);
842
843 ctx->Driver.DepthRange(ctx, ctx->Viewport.Near, ctx->Viewport.Far);
844
845 /* Update culling direction which changes depending on the
846 * orientation of the buffer:
847 */
848 ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
849 }
850
851 /* This isn't really handled at the moment.
852 */
853 static void
854 i830_new_batch(struct intel_context *intel)
855 {
856 struct i830_context *i830 = i830_context(&intel->ctx);
857 i830->state.emitted = 0;
858 }
859
860 static void
861 i830_assert_not_dirty( struct intel_context *intel )
862 {
863 struct i830_context *i830 = i830_context(&intel->ctx);
864 assert(!get_dirty(&i830->state));
865 (void) i830;
866 }
867
868 static void
869 i830_invalidate_state(struct intel_context *intel, GLuint new_state)
870 {
871 struct gl_context *ctx = &intel->ctx;
872
873 _swsetup_InvalidateState(ctx, new_state);
874 _tnl_InvalidateState(ctx, new_state);
875 _tnl_invalidate_vertex_state(ctx, new_state);
876
877 if (new_state & _NEW_LIGHT)
878 i830_update_provoking_vertex(&intel->ctx);
879 }
880
881 static bool
882 i830_is_hiz_depth_format(struct intel_context *intel, gl_format format)
883 {
884 return false;
885 }
886
887 void
888 i830InitVtbl(struct i830_context *i830)
889 {
890 i830->intel.vtbl.check_vertex_size = i830_check_vertex_size;
891 i830->intel.vtbl.destroy = i830_destroy_context;
892 i830->intel.vtbl.emit_state = i830_emit_state;
893 i830->intel.vtbl.new_batch = i830_new_batch;
894 i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state;
895 i830->intel.vtbl.set_draw_region = i830_set_draw_region;
896 i830->intel.vtbl.update_draw_buffer = i830_update_draw_buffer;
897 i830->intel.vtbl.update_texture_state = i830UpdateTextureState;
898 i830->intel.vtbl.render_start = i830_render_start;
899 i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
900 i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
901 i830->intel.vtbl.finish_batch = intel_finish_vb;
902 i830->intel.vtbl.invalidate_state = i830_invalidate_state;
903 i830->intel.vtbl.render_target_supported = i830_render_target_supported;
904 i830->intel.vtbl.is_hiz_depth_format = i830_is_hiz_depth_format;
905 }