src/mesa/drivers/dri/i915/i915_metaops.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "glheader.h"
  29 #include "enums.h"
  30 #include "mtypes.h"
  31 #include "macros.h"
  32 #include "utils.h"
  33
  34 #include "intel_screen.h"
  35 #include "intel_batchbuffer.h"
  36 #include "intel_ioctl.h"
  37 #include "intel_regions.h"
  38
  39 #include "i915_context.h"
  40 #include "i915_reg.h"
  41
  42 /* We touch almost everything:
  43  */
  44 #define ACTIVE (I915_UPLOAD_INVARIENT |         \
  45                 I915_UPLOAD_CTX |               \
  46                 I915_UPLOAD_BUFFERS |           \
  47                 I915_UPLOAD_STIPPLE |           \
  48                 I915_UPLOAD_PROGRAM |           \
  49                 I915_UPLOAD_FOG |               \
  50                 I915_UPLOAD_TEX(0))
  51
  52 #define SET_STATE( i915, STATE )                \
  53 do {                                            \
  54    i915->current->emitted &= ~ACTIVE;           \
  55    i915->current = &i915->STATE;                \
  56    i915->current->emitted &= ~ACTIVE;           \
  57 } while (0)
  58
  59
  60 static void
  61 meta_no_stencil_write(struct intel_context *intel)
  62 {
  63    struct i915_context *i915 = i915_context(&intel->ctx);
  64
  65    /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_FALSE )
  66     */
  67    i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_TEST_ENABLE |
  68                                          S5_STENCIL_WRITE_ENABLE);
  69
  70    i915->meta.emitted &= ~I915_UPLOAD_CTX;
  71 }
  72
  73 static void
  74 meta_no_depth_write(struct intel_context *intel)
  75 {
  76    struct i915_context *i915 = i915_context(&intel->ctx);
  77
  78    /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE )
  79     */
  80    i915->meta.Ctx[I915_CTXREG_LIS6] &= ~(S6_DEPTH_TEST_ENABLE |
  81                                          S6_DEPTH_WRITE_ENABLE);
  82
  83    i915->meta.emitted &= ~I915_UPLOAD_CTX;
  84 }
  85
  86 static void
  87 meta_depth_replace(struct intel_context *intel)
  88 {
  89    struct i915_context *i915 = i915_context(&intel->ctx);
  90
  91    /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_TRUE )
  92     * ctx->Driver.DepthMask( ctx, GL_TRUE )
  93     */
  94    i915->meta.Ctx[I915_CTXREG_LIS6] |= (S6_DEPTH_TEST_ENABLE |
  95                                         S6_DEPTH_WRITE_ENABLE);
  96
  97    /* ctx->Driver.DepthFunc( ctx, GL_ALWAYS )
  98     */
  99    i915->meta.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_TEST_FUNC_MASK;
 100    i915->meta.Ctx[I915_CTXREG_LIS6] |=
 101       COMPAREFUNC_ALWAYS << S6_DEPTH_TEST_FUNC_SHIFT;
 102
 103    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 104 }
 105
 106
 107 /* Set stencil unit to replace always with the reference value.
 108  */
 109 static void
 110 meta_stencil_replace(struct intel_context *intel,
 111                      GLuint s_mask, GLuint s_clear)
 112 {
 113    struct i915_context *i915 = i915_context(&intel->ctx);
 114    GLuint op = STENCILOP_REPLACE;
 115    GLuint func = COMPAREFUNC_ALWAYS;
 116
 117    /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_TRUE )
 118     */
 119    i915->meta.Ctx[I915_CTXREG_LIS5] |= (S5_STENCIL_TEST_ENABLE |
 120                                         S5_STENCIL_WRITE_ENABLE);
 121
 122    /* ctx->Driver.StencilMask( ctx, s_mask )
 123     */
 124    i915->meta.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
 125
 126    i915->meta.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK |
 127                                           STENCIL_WRITE_MASK(s_mask));
 128
 129    /* ctx->Driver.StencilOp( ctx, GL_REPLACE, GL_REPLACE, GL_REPLACE )
 130     */
 131    i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_FAIL_MASK |
 132                                          S5_STENCIL_PASS_Z_FAIL_MASK |
 133                                          S5_STENCIL_PASS_Z_PASS_MASK);
 134
 135    i915->meta.Ctx[I915_CTXREG_LIS5] |= ((op << S5_STENCIL_FAIL_SHIFT) |
 136                                         (op << S5_STENCIL_PASS_Z_FAIL_SHIFT) |
 137                                         (op << S5_STENCIL_PASS_Z_PASS_SHIFT));
 138
 139
 140    /* ctx->Driver.StencilFunc( ctx, GL_ALWAYS, s_ref, ~0 )
 141     */
 142    i915->meta.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK;
 143    i915->meta.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
 144                                           STENCIL_TEST_MASK(0xff));
 145
 146    i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_REF_MASK |
 147                                          S5_STENCIL_TEST_FUNC_MASK);
 148
 149    i915->meta.Ctx[I915_CTXREG_LIS5] |= ((s_clear << S5_STENCIL_REF_SHIFT) |
 150                                         (func << S5_STENCIL_TEST_FUNC_SHIFT));
 151
 152
 153    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 154 }
 155
 156
 157 static void
 158 meta_color_mask(struct intel_context *intel, GLboolean state)
 159 {
 160    struct i915_context *i915 = i915_context(&intel->ctx);
 161    const GLuint mask = (S5_WRITEDISABLE_RED |
 162                         S5_WRITEDISABLE_GREEN |
 163                         S5_WRITEDISABLE_BLUE | S5_WRITEDISABLE_ALPHA);
 164
 165    /* Copy colormask state from "regular" hw context.
 166     */
 167    if (state) {
 168       i915->meta.Ctx[I915_CTXREG_LIS5] &= ~mask;
 169       i915->meta.Ctx[I915_CTXREG_LIS5] |=
 170          (i915->state.Ctx[I915_CTXREG_LIS5] & mask);
 171    }
 172    else
 173       i915->meta.Ctx[I915_CTXREG_LIS5] |= mask;
 174
 175    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 176 }
 177
 178
 179
 180 static void
 181 meta_import_pixel_state(struct intel_context *intel)
 182 {
 183    struct i915_context *i915 = i915_context(&intel->ctx);
 184    memcpy(i915->meta.Fog, i915->state.Fog, I915_FOG_SETUP_SIZE * 4);
 185
 186    i915->meta.Ctx[I915_CTXREG_LIS5] = i915->state.Ctx[I915_CTXREG_LIS5];
 187    i915->meta.Ctx[I915_CTXREG_LIS6] = i915->state.Ctx[I915_CTXREG_LIS6];
 188    i915->meta.Ctx[I915_CTXREG_STATE4] = i915->state.Ctx[I915_CTXREG_STATE4];
 189    i915->meta.Ctx[I915_CTXREG_BLENDCOLOR1] =
 190       i915->state.Ctx[I915_CTXREG_BLENDCOLOR1];
 191    i915->meta.Ctx[I915_CTXREG_IAB] = i915->state.Ctx[I915_CTXREG_IAB];
 192
 193    i915->meta.Buffer[I915_DESTREG_SENABLE] =
 194       i915->state.Buffer[I915_DESTREG_SENABLE];
 195    i915->meta.Buffer[I915_DESTREG_SR1] = i915->state.Buffer[I915_DESTREG_SR1];
 196    i915->meta.Buffer[I915_DESTREG_SR2] = i915->state.Buffer[I915_DESTREG_SR2];
 197
 198    i915->meta.emitted &= ~I915_UPLOAD_FOG;
 199    i915->meta.emitted &= ~I915_UPLOAD_BUFFERS;
 200    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 201 }
 202
 203
 204
 205
 206 #define REG( type, nr ) (((type)<<5)|(nr))
 207
 208 #define REG_R(x)       REG(REG_TYPE_R, x)
 209 #define REG_T(x)       REG(REG_TYPE_T, x)
 210 #define REG_CONST(x)   REG(REG_TYPE_CONST, x)
 211 #define REG_S(x)       REG(REG_TYPE_S, x)
 212 #define REG_OC         REG(REG_TYPE_OC, 0)
 213 #define REG_OD         REG(REG_TYPE_OD, 0)
 214 #define REG_U(x)       REG(REG_TYPE_U, x)
 215
 216 #define REG_T_DIFFUSE  REG(REG_TYPE_T, T_DIFFUSE)
 217 #define REG_T_SPECULAR REG(REG_TYPE_T, T_SPECULAR)
 218 #define REG_T_FOG_W    REG(REG_TYPE_T, T_FOG_W)
 219 #define REG_T_TEX(x)   REG(REG_TYPE_T, x)
 220
 221
 222 #define A0_DEST_REG( reg ) ( (reg) << A0_DEST_NR_SHIFT )
 223 #define A0_SRC0_REG( reg ) ( (reg) << A0_SRC0_NR_SHIFT )
 224 #define A1_SRC1_REG( reg ) ( (reg) << A1_SRC1_NR_SHIFT )
 225 #define A1_SRC2_REG( reg ) ( (reg) << A1_SRC2_NR_SHIFT )
 226 #define A2_SRC2_REG( reg ) ( (reg) << A2_SRC2_NR_SHIFT )
 227 #define D0_DECL_REG( reg ) ( (reg) << D0_NR_SHIFT )
 228 #define T0_DEST_REG( reg ) ( (reg) << T0_DEST_NR_SHIFT )
 229
 230 #define T0_SAMPLER( unit )     ((unit)<<T0_SAMPLER_NR_SHIFT)
 231
 232 #define T1_ADDRESS_REG( type, nr ) (((type)<<T1_ADDRESS_REG_TYPE_SHIFT)| \
 233                                     ((nr)<<T1_ADDRESS_REG_NR_SHIFT))
 234
 235
 236 #define A1_SRC0_XYZW ((SRC_X << A1_SRC0_CHANNEL_X_SHIFT) |      \
 237                       (SRC_Y << A1_SRC0_CHANNEL_Y_SHIFT) |      \
 238                       (SRC_Z << A1_SRC0_CHANNEL_Z_SHIFT) |      \
 239                       (SRC_W << A1_SRC0_CHANNEL_W_SHIFT))
 240
 241 #define A1_SRC1_XY   ((SRC_X << A1_SRC1_CHANNEL_X_SHIFT) |      \
 242                       (SRC_Y << A1_SRC1_CHANNEL_Y_SHIFT))
 243
 244 #define A2_SRC1_ZW   ((SRC_Z << A2_SRC1_CHANNEL_Z_SHIFT) |      \
 245                       (SRC_W << A2_SRC1_CHANNEL_W_SHIFT))
 246
 247 #define A2_SRC2_XYZW ((SRC_X << A2_SRC2_CHANNEL_X_SHIFT) |      \
 248                       (SRC_Y << A2_SRC2_CHANNEL_Y_SHIFT) |      \
 249                       (SRC_Z << A2_SRC2_CHANNEL_Z_SHIFT) |      \
 250                       (SRC_W << A2_SRC2_CHANNEL_W_SHIFT))
 251
 252
 253
 254
 255
 256 static void
 257 meta_no_texture(struct intel_context *intel)
 258 {
 259    struct i915_context *i915 = i915_context(&intel->ctx);
 260
 261    static const GLuint prog[] = {
 262       _3DSTATE_PIXEL_SHADER_PROGRAM,
 263
 264       /* Declare incoming diffuse color:
 265        */
 266       (D0_DCL | D0_DECL_REG(REG_T_DIFFUSE) | D0_CHANNEL_ALL),
 267       D1_MBZ,
 268       D2_MBZ,
 269
 270       /* output-color = mov(t_diffuse)
 271        */
 272       (A0_MOV |
 273        A0_DEST_REG(REG_OC) |
 274        A0_DEST_CHANNEL_ALL | A0_SRC0_REG(REG_T_DIFFUSE)),
 275       (A1_SRC0_XYZW),
 276       0,
 277    };
 278
 279
 280    memcpy(i915->meta.Program, prog, sizeof(prog));
 281    i915->meta.ProgramSize = sizeof(prog) / sizeof(*prog);
 282    i915->meta.Program[0] |= i915->meta.ProgramSize - 2;
 283    i915->meta.emitted &= ~I915_UPLOAD_PROGRAM;
 284 }
 285
 286 static void
 287 meta_texture_blend_replace(struct intel_context *intel)
 288 {
 289    struct i915_context *i915 = i915_context(&intel->ctx);
 290
 291    static const GLuint prog[] = {
 292       _3DSTATE_PIXEL_SHADER_PROGRAM,
 293
 294       /* Declare the sampler:
 295        */
 296       (D0_DCL | D0_DECL_REG(REG_S(0)) | D0_SAMPLE_TYPE_2D | D0_CHANNEL_NONE),
 297       D1_MBZ,
 298       D2_MBZ,
 299
 300       /* Declare the interpolated texture coordinate:
 301        */
 302       (D0_DCL | D0_DECL_REG(REG_T_TEX(0)) | D0_CHANNEL_ALL),
 303       D1_MBZ,
 304       D2_MBZ,
 305
 306       /* output-color = texld(sample0, texcoord0)
 307        */
 308       (T0_TEXLD | T0_DEST_REG(REG_OC) | T0_SAMPLER(0)),
 309       T1_ADDRESS_REG(REG_TYPE_T, 0),
 310       T2_MBZ
 311    };
 312
 313    memcpy(i915->meta.Program, prog, sizeof(prog));
 314    i915->meta.ProgramSize = sizeof(prog) / sizeof(*prog);
 315    i915->meta.Program[0] |= i915->meta.ProgramSize - 2;
 316    i915->meta.emitted &= ~I915_UPLOAD_PROGRAM;
 317 }
 318
 319
 320
 321
 322
 323 /* Set up an arbitary piece of memory as a rectangular texture
 324  * (including the front or back buffer).
 325  */
 326 static GLboolean
 327 meta_tex_rect_source(struct intel_context *intel,
 328                      dri_bo *buffer,
 329                      GLuint offset,
 330                      GLuint pitch, GLuint height, GLenum format, GLenum type)
 331 {
 332    struct i915_context *i915 = i915_context(&intel->ctx);
 333    GLuint unit = 0;
 334    GLint numLevels = 1;
 335    GLuint *state = i915->meta.Tex[0];
 336    GLuint textureFormat;
 337    GLuint cpp;
 338
 339    /* A full implementation of this would do the upload through
 340     * glTexImage2d, and get all the conversion operations at that
 341     * point.  We are restricted, but still at least have access to the
 342     * fragment program swizzle.
 343     */
 344    switch (format) {
 345    case GL_BGRA:
 346       switch (type) {
 347       case GL_UNSIGNED_INT_8_8_8_8_REV:
 348       case GL_UNSIGNED_BYTE:
 349          textureFormat = (MAPSURF_32BIT | MT_32BIT_ARGB8888);
 350          cpp = 4;
 351          break;
 352       default:
 353          return GL_FALSE;
 354       }
 355       break;
 356    case GL_RGBA:
 357       switch (type) {
 358       case GL_UNSIGNED_INT_8_8_8_8_REV:
 359       case GL_UNSIGNED_BYTE:
 360          textureFormat = (MAPSURF_32BIT | MT_32BIT_ABGR8888);
 361          cpp = 4;
 362          break;
 363       default:
 364          return GL_FALSE;
 365       }
 366       break;
 367    case GL_BGR:
 368       switch (type) {
 369       case GL_UNSIGNED_SHORT_5_6_5_REV:
 370          textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565);
 371          cpp = 2;
 372          break;
 373       default:
 374          return GL_FALSE;
 375       }
 376       break;
 377    case GL_RGB:
 378       switch (type) {
 379       case GL_UNSIGNED_SHORT_5_6_5:
 380          textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565);
 381          cpp = 2;
 382          break;
 383       default:
 384          return GL_FALSE;
 385       }
 386       break;
 387
 388    default:
 389       return GL_FALSE;
 390    }
 391
 392
 393    if ((pitch * cpp) & 3) {
 394       _mesa_printf("%s: texture is not dword pitch\n", __FUNCTION__);
 395       return GL_FALSE;
 396    }
 397
 398 /*    intel_region_release(&i915->meta.tex_region[0]); */
 399 /*    intel_region_reference(&i915->meta.tex_region[0], region); */
 400    i915->meta.tex_buffer[0] = buffer;
 401    i915->meta.tex_offset[0] = offset;
 402
 403    state[I915_TEXREG_MS3] = (((height - 1) << MS3_HEIGHT_SHIFT) |
 404                              ((pitch - 1) << MS3_WIDTH_SHIFT) |
 405                              textureFormat | MS3_USE_FENCE_REGS);
 406
 407    state[I915_TEXREG_MS4] = (((((pitch * cpp) / 4) - 1) << MS4_PITCH_SHIFT) |
 408                              MS4_CUBE_FACE_ENA_MASK |
 409                              ((((numLevels - 1) * 4)) << MS4_MAX_LOD_SHIFT));
 410
 411    state[I915_TEXREG_SS2] = ((FILTER_NEAREST << SS2_MIN_FILTER_SHIFT) |
 412                              (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT) |
 413                              (FILTER_NEAREST << SS2_MAG_FILTER_SHIFT));
 414
 415    state[I915_TEXREG_SS3] = ((TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT) |
 416                              (TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT) |
 417                              (TEXCOORDMODE_WRAP << SS3_TCZ_ADDR_MODE_SHIFT) |
 418                              (unit << SS3_TEXTUREMAP_INDEX_SHIFT));
 419
 420    state[I915_TEXREG_SS4] = 0;
 421
 422    i915->meta.emitted &= ~I915_UPLOAD_TEX(0);
 423    return GL_TRUE;
 424 }
 425
 426
 427 /**
 428  * Set the color and depth drawing region for meta ops.
 429  */
 430 static void
 431 meta_draw_region(struct intel_context *intel,
 432                  struct intel_region *color_region,
 433                  struct intel_region *depth_region)
 434 {
 435    struct i915_context *i915 = i915_context(&intel->ctx);
 436    i915_state_draw_region(intel, &i915->meta, color_region, depth_region);
 437 }
 438
 439
 440 static void
 441 set_vertex_format(struct intel_context *intel)
 442 {
 443    struct i915_context *i915 = i915_context(&intel->ctx);
 444
 445    i915->meta.Ctx[I915_CTXREG_LIS2] =
 446       (S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) |
 447        S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT) |
 448        S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) |
 449        S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) |
 450        S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) |
 451        S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) |
 452        S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) |
 453        S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT));
 454
 455    i915->meta.Ctx[I915_CTXREG_LIS4] &= ~S4_VFMT_MASK;
 456
 457    i915->meta.Ctx[I915_CTXREG_LIS4] |= (S4_VFMT_COLOR | S4_VFMT_XYZ);
 458
 459    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 460 }
 461
 462
 463
 464 /* Operations where the 3D engine is decoupled temporarily from the
 465  * current GL state and used for other purposes than simply rendering
 466  * incoming triangles.
 467  */
 468 static void
 469 install_meta_state(struct intel_context *intel)
 470 {
 471    struct i915_context *i915 = i915_context(&intel->ctx);
 472    memcpy(&i915->meta, &i915->initial, sizeof(i915->meta));
 473    i915->meta.active = ACTIVE;
 474    i915->meta.emitted = 0;
 475
 476    SET_STATE(i915, meta);
 477    set_vertex_format(intel);
 478    meta_no_texture(intel);
 479 }
 480
 481 static void
 482 leave_meta_state(struct intel_context *intel)
 483 {
 484    struct i915_context *i915 = i915_context(&intel->ctx);
 485    intel_region_release(&i915->meta.draw_region);
 486    intel_region_release(&i915->meta.depth_region);
 487 /*    intel_region_release(&i915->meta.tex_region[0]); */
 488    SET_STATE(i915, state);
 489 }
 490
 491
 492
 493 void
 494 i915InitMetaFuncs(struct i915_context *i915)
 495 {
 496    i915->intel.vtbl.install_meta_state = install_meta_state;
 497    i915->intel.vtbl.leave_meta_state = leave_meta_state;
 498    i915->intel.vtbl.meta_no_depth_write = meta_no_depth_write;
 499    i915->intel.vtbl.meta_no_stencil_write = meta_no_stencil_write;
 500    i915->intel.vtbl.meta_stencil_replace = meta_stencil_replace;
 501    i915->intel.vtbl.meta_depth_replace = meta_depth_replace;
 502    i915->intel.vtbl.meta_color_mask = meta_color_mask;
 503    i915->intel.vtbl.meta_no_texture = meta_no_texture;
 504    i915->intel.vtbl.meta_texture_blend_replace = meta_texture_blend_replace;
 505    i915->intel.vtbl.meta_tex_rect_source = meta_tex_rect_source;
 506    i915->intel.vtbl.meta_draw_region = meta_draw_region;
 507    i915->intel.vtbl.meta_import_pixel_state = meta_import_pixel_state;
 508 }