src/mesa/drivers/dri/i915/i915_metaops.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "glheader.h"
  29 #include "enums.h"
  30 #include "mtypes.h"
  31 #include "macros.h"
  32 #include "utils.h"
  33
  34 #include "intel_screen.h"
  35 #include "intel_batchbuffer.h"
  36 #include "intel_regions.h"
  37
  38 #include "i915_context.h"
  39 #include "i915_reg.h"
  40
  41 /* We touch almost everything:
  42  */
  43 #define ACTIVE (I915_UPLOAD_INVARIENT |         \
  44                 I915_UPLOAD_CTX |               \
  45                 I915_UPLOAD_BUFFERS |           \
  46                 I915_UPLOAD_STIPPLE |           \
  47                 I915_UPLOAD_PROGRAM |           \
  48                 I915_UPLOAD_FOG |               \
  49                 I915_UPLOAD_TEX(0))
  50
  51 #define SET_STATE( i915, STATE )                \
  52 do {                                            \
  53    i915->current->emitted &= ~ACTIVE;           \
  54    i915->current = &i915->STATE;                \
  55    i915->current->emitted &= ~ACTIVE;           \
  56 } while (0)
  57
  58
  59 static void
  60 meta_no_stencil_write(struct intel_context *intel)
  61 {
  62    struct i915_context *i915 = i915_context(&intel->ctx);
  63
  64    /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_FALSE )
  65     */
  66    i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_TEST_ENABLE |
  67                                          S5_STENCIL_WRITE_ENABLE);
  68
  69    i915->meta.emitted &= ~I915_UPLOAD_CTX;
  70 }
  71
  72 static void
  73 meta_no_depth_write(struct intel_context *intel)
  74 {
  75    struct i915_context *i915 = i915_context(&intel->ctx);
  76
  77    /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE )
  78     */
  79    i915->meta.Ctx[I915_CTXREG_LIS6] &= ~(S6_DEPTH_TEST_ENABLE |
  80                                          S6_DEPTH_WRITE_ENABLE);
  81
  82    i915->meta.emitted &= ~I915_UPLOAD_CTX;
  83 }
  84
  85 static void
  86 meta_depth_replace(struct intel_context *intel)
  87 {
  88    struct i915_context *i915 = i915_context(&intel->ctx);
  89
  90    /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_TRUE )
  91     * ctx->Driver.DepthMask( ctx, GL_TRUE )
  92     */
  93    i915->meta.Ctx[I915_CTXREG_LIS6] |= (S6_DEPTH_TEST_ENABLE |
  94                                         S6_DEPTH_WRITE_ENABLE);
  95
  96    /* ctx->Driver.DepthFunc( ctx, GL_ALWAYS )
  97     */
  98    i915->meta.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_TEST_FUNC_MASK;
  99    i915->meta.Ctx[I915_CTXREG_LIS6] |=
 100       COMPAREFUNC_ALWAYS << S6_DEPTH_TEST_FUNC_SHIFT;
 101
 102    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 103 }
 104
 105
 106 /* Set stencil unit to replace always with the reference value.
 107  */
 108 static void
 109 meta_stencil_replace(struct intel_context *intel,
 110                      GLuint s_mask, GLuint s_clear)
 111 {
 112    struct i915_context *i915 = i915_context(&intel->ctx);
 113    GLuint op = STENCILOP_REPLACE;
 114    GLuint func = COMPAREFUNC_ALWAYS;
 115
 116    /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_TRUE )
 117     */
 118    i915->meta.Ctx[I915_CTXREG_LIS5] |= (S5_STENCIL_TEST_ENABLE |
 119                                         S5_STENCIL_WRITE_ENABLE);
 120
 121    /* ctx->Driver.StencilMask( ctx, s_mask )
 122     */
 123    i915->meta.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
 124
 125    i915->meta.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK |
 126                                           STENCIL_WRITE_MASK(s_mask));
 127
 128    /* ctx->Driver.StencilOp( ctx, GL_REPLACE, GL_REPLACE, GL_REPLACE )
 129     */
 130    i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_FAIL_MASK |
 131                                          S5_STENCIL_PASS_Z_FAIL_MASK |
 132                                          S5_STENCIL_PASS_Z_PASS_MASK);
 133
 134    i915->meta.Ctx[I915_CTXREG_LIS5] |= ((op << S5_STENCIL_FAIL_SHIFT) |
 135                                         (op << S5_STENCIL_PASS_Z_FAIL_SHIFT) |
 136                                         (op << S5_STENCIL_PASS_Z_PASS_SHIFT));
 137
 138
 139    /* ctx->Driver.StencilFunc( ctx, GL_ALWAYS, s_ref, ~0 )
 140     */
 141    i915->meta.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK;
 142    i915->meta.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
 143                                           STENCIL_TEST_MASK(0xff));
 144
 145    i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_REF_MASK |
 146                                          S5_STENCIL_TEST_FUNC_MASK);
 147
 148    i915->meta.Ctx[I915_CTXREG_LIS5] |= ((s_clear << S5_STENCIL_REF_SHIFT) |
 149                                         (func << S5_STENCIL_TEST_FUNC_SHIFT));
 150
 151
 152    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 153 }
 154
 155
 156 static void
 157 meta_color_mask(struct intel_context *intel, GLboolean state)
 158 {
 159    struct i915_context *i915 = i915_context(&intel->ctx);
 160    const GLuint mask = (S5_WRITEDISABLE_RED |
 161                         S5_WRITEDISABLE_GREEN |
 162                         S5_WRITEDISABLE_BLUE | S5_WRITEDISABLE_ALPHA);
 163
 164    /* Copy colormask state from "regular" hw context.
 165     */
 166    if (state) {
 167       i915->meta.Ctx[I915_CTXREG_LIS5] &= ~mask;
 168       i915->meta.Ctx[I915_CTXREG_LIS5] |=
 169          (i915->state.Ctx[I915_CTXREG_LIS5] & mask);
 170    }
 171    else
 172       i915->meta.Ctx[I915_CTXREG_LIS5] |= mask;
 173
 174    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 175 }
 176
 177
 178
 179 static void
 180 meta_import_pixel_state(struct intel_context *intel)
 181 {
 182    struct i915_context *i915 = i915_context(&intel->ctx);
 183    memcpy(i915->meta.Fog, i915->state.Fog, I915_FOG_SETUP_SIZE * 4);
 184
 185    i915->meta.Ctx[I915_CTXREG_LIS5] = i915->state.Ctx[I915_CTXREG_LIS5];
 186    i915->meta.Ctx[I915_CTXREG_LIS6] = i915->state.Ctx[I915_CTXREG_LIS6];
 187    i915->meta.Ctx[I915_CTXREG_STATE4] = i915->state.Ctx[I915_CTXREG_STATE4];
 188    i915->meta.Ctx[I915_CTXREG_BLENDCOLOR1] =
 189       i915->state.Ctx[I915_CTXREG_BLENDCOLOR1];
 190    i915->meta.Ctx[I915_CTXREG_IAB] = i915->state.Ctx[I915_CTXREG_IAB];
 191
 192    i915->meta.Buffer[I915_DESTREG_SENABLE] =
 193       i915->state.Buffer[I915_DESTREG_SENABLE];
 194    i915->meta.Buffer[I915_DESTREG_SR1] = i915->state.Buffer[I915_DESTREG_SR1];
 195    i915->meta.Buffer[I915_DESTREG_SR2] = i915->state.Buffer[I915_DESTREG_SR2];
 196
 197    i915->meta.emitted &= ~I915_UPLOAD_FOG;
 198    i915->meta.emitted &= ~I915_UPLOAD_BUFFERS;
 199    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 200 }
 201
 202
 203
 204
 205 #define REG( type, nr ) (((type)<<5)|(nr))
 206
 207 #define REG_R(x)       REG(REG_TYPE_R, x)
 208 #define REG_T(x)       REG(REG_TYPE_T, x)
 209 #define REG_CONST(x)   REG(REG_TYPE_CONST, x)
 210 #define REG_S(x)       REG(REG_TYPE_S, x)
 211 #define REG_OC         REG(REG_TYPE_OC, 0)
 212 #define REG_OD         REG(REG_TYPE_OD, 0)
 213 #define REG_U(x)       REG(REG_TYPE_U, x)
 214
 215 #define REG_T_DIFFUSE  REG(REG_TYPE_T, T_DIFFUSE)
 216 #define REG_T_SPECULAR REG(REG_TYPE_T, T_SPECULAR)
 217 #define REG_T_FOG_W    REG(REG_TYPE_T, T_FOG_W)
 218 #define REG_T_TEX(x)   REG(REG_TYPE_T, x)
 219
 220
 221 #define A0_DEST_REG( reg ) ( (reg) << A0_DEST_NR_SHIFT )
 222 #define A0_SRC0_REG( reg ) ( (reg) << A0_SRC0_NR_SHIFT )
 223 #define A1_SRC1_REG( reg ) ( (reg) << A1_SRC1_NR_SHIFT )
 224 #define A1_SRC2_REG( reg ) ( (reg) << A1_SRC2_NR_SHIFT )
 225 #define A2_SRC2_REG( reg ) ( (reg) << A2_SRC2_NR_SHIFT )
 226 #define D0_DECL_REG( reg ) ( (reg) << D0_NR_SHIFT )
 227 #define T0_DEST_REG( reg ) ( (reg) << T0_DEST_NR_SHIFT )
 228
 229 #define T0_SAMPLER( unit )     ((unit)<<T0_SAMPLER_NR_SHIFT)
 230
 231 #define T1_ADDRESS_REG( type, nr ) (((type)<<T1_ADDRESS_REG_TYPE_SHIFT)| \
 232                                     ((nr)<<T1_ADDRESS_REG_NR_SHIFT))
 233
 234
 235 #define A1_SRC0_XYZW ((SRC_X << A1_SRC0_CHANNEL_X_SHIFT) |      \
 236                       (SRC_Y << A1_SRC0_CHANNEL_Y_SHIFT) |      \
 237                       (SRC_Z << A1_SRC0_CHANNEL_Z_SHIFT) |      \
 238                       (SRC_W << A1_SRC0_CHANNEL_W_SHIFT))
 239
 240 #define A1_SRC1_XY   ((SRC_X << A1_SRC1_CHANNEL_X_SHIFT) |      \
 241                       (SRC_Y << A1_SRC1_CHANNEL_Y_SHIFT))
 242
 243 #define A2_SRC1_ZW   ((SRC_Z << A2_SRC1_CHANNEL_Z_SHIFT) |      \
 244                       (SRC_W << A2_SRC1_CHANNEL_W_SHIFT))
 245
 246 #define A2_SRC2_XYZW ((SRC_X << A2_SRC2_CHANNEL_X_SHIFT) |      \
 247                       (SRC_Y << A2_SRC2_CHANNEL_Y_SHIFT) |      \
 248                       (SRC_Z << A2_SRC2_CHANNEL_Z_SHIFT) |      \
 249                       (SRC_W << A2_SRC2_CHANNEL_W_SHIFT))
 250
 251
 252
 253
 254
 255 static void
 256 meta_no_texture(struct intel_context *intel)
 257 {
 258    struct i915_context *i915 = i915_context(&intel->ctx);
 259
 260    static const GLuint prog[] = {
 261       _3DSTATE_PIXEL_SHADER_PROGRAM,
 262
 263       /* Declare incoming diffuse color:
 264        */
 265       (D0_DCL | D0_DECL_REG(REG_T_DIFFUSE) | D0_CHANNEL_ALL),
 266       D1_MBZ,
 267       D2_MBZ,
 268
 269       /* output-color = mov(t_diffuse)
 270        */
 271       (A0_MOV |
 272        A0_DEST_REG(REG_OC) |
 273        A0_DEST_CHANNEL_ALL | A0_SRC0_REG(REG_T_DIFFUSE)),
 274       (A1_SRC0_XYZW),
 275       0,
 276    };
 277
 278
 279    memcpy(i915->meta.Program, prog, sizeof(prog));
 280    i915->meta.ProgramSize = sizeof(prog) / sizeof(*prog);
 281    i915->meta.Program[0] |= i915->meta.ProgramSize - 2;
 282    i915->meta.emitted &= ~I915_UPLOAD_PROGRAM;
 283 }
 284
 285 static void
 286 meta_texture_blend_replace(struct intel_context *intel)
 287 {
 288    struct i915_context *i915 = i915_context(&intel->ctx);
 289
 290    static const GLuint prog[] = {
 291       _3DSTATE_PIXEL_SHADER_PROGRAM,
 292
 293       /* Declare the sampler:
 294        */
 295       (D0_DCL | D0_DECL_REG(REG_S(0)) | D0_SAMPLE_TYPE_2D | D0_CHANNEL_NONE),
 296       D1_MBZ,
 297       D2_MBZ,
 298
 299       /* Declare the interpolated texture coordinate:
 300        */
 301       (D0_DCL | D0_DECL_REG(REG_T_TEX(0)) | D0_CHANNEL_ALL),
 302       D1_MBZ,
 303       D2_MBZ,
 304
 305       /* output-color = texld(sample0, texcoord0)
 306        */
 307       (T0_TEXLD | T0_DEST_REG(REG_OC) | T0_SAMPLER(0)),
 308       T1_ADDRESS_REG(REG_TYPE_T, 0),
 309       T2_MBZ
 310    };
 311
 312    memcpy(i915->meta.Program, prog, sizeof(prog));
 313    i915->meta.ProgramSize = sizeof(prog) / sizeof(*prog);
 314    i915->meta.Program[0] |= i915->meta.ProgramSize - 2;
 315    i915->meta.emitted &= ~I915_UPLOAD_PROGRAM;
 316 }
 317
 318
 319
 320
 321
 322 /* Set up an arbitary piece of memory as a rectangular texture
 323  * (including the front or back buffer).
 324  */
 325 static GLboolean
 326 meta_tex_rect_source(struct intel_context *intel,
 327                      dri_bo *buffer,
 328                      GLuint offset,
 329                      GLuint pitch, GLuint height, GLenum format, GLenum type)
 330 {
 331    struct i915_context *i915 = i915_context(&intel->ctx);
 332    GLuint unit = 0;
 333    GLint numLevels = 1;
 334    GLuint *state = i915->meta.Tex[0];
 335    GLuint textureFormat;
 336    GLuint cpp;
 337
 338    /* A full implementation of this would do the upload through
 339     * glTexImage2d, and get all the conversion operations at that
 340     * point.  We are restricted, but still at least have access to the
 341     * fragment program swizzle.
 342     */
 343    switch (format) {
 344    case GL_BGRA:
 345       switch (type) {
 346       case GL_UNSIGNED_INT_8_8_8_8_REV:
 347       case GL_UNSIGNED_BYTE:
 348          textureFormat = (MAPSURF_32BIT | MT_32BIT_ARGB8888);
 349          cpp = 4;
 350          break;
 351       default:
 352          return GL_FALSE;
 353       }
 354       break;
 355    case GL_RGBA:
 356       switch (type) {
 357       case GL_UNSIGNED_INT_8_8_8_8_REV:
 358       case GL_UNSIGNED_BYTE:
 359          textureFormat = (MAPSURF_32BIT | MT_32BIT_ABGR8888);
 360          cpp = 4;
 361          break;
 362       default:
 363          return GL_FALSE;
 364       }
 365       break;
 366    case GL_BGR:
 367       switch (type) {
 368       case GL_UNSIGNED_SHORT_5_6_5_REV:
 369          textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565);
 370          cpp = 2;
 371          break;
 372       default:
 373          return GL_FALSE;
 374       }
 375       break;
 376    case GL_RGB:
 377       switch (type) {
 378       case GL_UNSIGNED_SHORT_5_6_5:
 379          textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565);
 380          cpp = 2;
 381          break;
 382       default:
 383          return GL_FALSE;
 384       }
 385       break;
 386
 387    default:
 388       return GL_FALSE;
 389    }
 390
 391
 392    if ((pitch * cpp) & 3) {
 393       _mesa_printf("%s: texture is not dword pitch\n", __FUNCTION__);
 394       return GL_FALSE;
 395    }
 396
 397 /*    intel_region_release(&i915->meta.tex_region[0]); */
 398 /*    intel_region_reference(&i915->meta.tex_region[0], region); */
 399    i915->meta.tex_buffer[0] = buffer;
 400    i915->meta.tex_offset[0] = offset;
 401
 402    state[I915_TEXREG_MS3] = (((height - 1) << MS3_HEIGHT_SHIFT) |
 403                              ((pitch - 1) << MS3_WIDTH_SHIFT) |
 404                              textureFormat | MS3_USE_FENCE_REGS);
 405
 406    state[I915_TEXREG_MS4] = (((((pitch * cpp) / 4) - 1) << MS4_PITCH_SHIFT) |
 407                              MS4_CUBE_FACE_ENA_MASK |
 408                              ((((numLevels - 1) * 4)) << MS4_MAX_LOD_SHIFT));
 409
 410    state[I915_TEXREG_SS2] = ((FILTER_NEAREST << SS2_MIN_FILTER_SHIFT) |
 411                              (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT) |
 412                              (FILTER_NEAREST << SS2_MAG_FILTER_SHIFT));
 413
 414    state[I915_TEXREG_SS3] = ((TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT) |
 415                              (TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT) |
 416                              (TEXCOORDMODE_WRAP << SS3_TCZ_ADDR_MODE_SHIFT) |
 417                              (unit << SS3_TEXTUREMAP_INDEX_SHIFT));
 418
 419    state[I915_TEXREG_SS4] = 0;
 420
 421    i915->meta.emitted &= ~I915_UPLOAD_TEX(0);
 422    return GL_TRUE;
 423 }
 424
 425
 426 /**
 427  * Set the color and depth drawing region for meta ops.
 428  */
 429 static void
 430 meta_draw_region(struct intel_context *intel,
 431                  struct intel_region *color_region,
 432                  struct intel_region *depth_region)
 433 {
 434    struct i915_context *i915 = i915_context(&intel->ctx);
 435    i915_state_draw_region(intel, &i915->meta, color_region, depth_region);
 436 }
 437
 438
 439 static void
 440 set_vertex_format(struct intel_context *intel)
 441 {
 442    struct i915_context *i915 = i915_context(&intel->ctx);
 443
 444    i915->meta.Ctx[I915_CTXREG_LIS2] =
 445       (S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) |
 446        S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT) |
 447        S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) |
 448        S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) |
 449        S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) |
 450        S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) |
 451        S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) |
 452        S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT));
 453
 454    i915->meta.Ctx[I915_CTXREG_LIS4] &= ~S4_VFMT_MASK;
 455
 456    i915->meta.Ctx[I915_CTXREG_LIS4] |= (S4_VFMT_COLOR | S4_VFMT_XYZ);
 457
 458    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 459 }
 460
 461
 462
 463 /* Operations where the 3D engine is decoupled temporarily from the
 464  * current GL state and used for other purposes than simply rendering
 465  * incoming triangles.
 466  */
 467 static void
 468 install_meta_state(struct intel_context *intel)
 469 {
 470    struct i915_context *i915 = i915_context(&intel->ctx);
 471    memcpy(&i915->meta, &i915->initial, sizeof(i915->meta));
 472    i915->meta.active = ACTIVE;
 473    i915->meta.emitted = 0;
 474
 475    SET_STATE(i915, meta);
 476    set_vertex_format(intel);
 477    meta_no_texture(intel);
 478 }
 479
 480 static void
 481 leave_meta_state(struct intel_context *intel)
 482 {
 483    struct i915_context *i915 = i915_context(&intel->ctx);
 484    intel_region_release(&i915->meta.draw_region);
 485    intel_region_release(&i915->meta.depth_region);
 486 /*    intel_region_release(&i915->meta.tex_region[0]); */
 487    SET_STATE(i915, state);
 488 }
 489
 490
 491
 492 void
 493 i915InitMetaFuncs(struct i915_context *i915)
 494 {
 495    i915->intel.vtbl.install_meta_state = install_meta_state;
 496    i915->intel.vtbl.leave_meta_state = leave_meta_state;
 497    i915->intel.vtbl.meta_no_depth_write = meta_no_depth_write;
 498    i915->intel.vtbl.meta_no_stencil_write = meta_no_stencil_write;
 499    i915->intel.vtbl.meta_stencil_replace = meta_stencil_replace;
 500    i915->intel.vtbl.meta_depth_replace = meta_depth_replace;
 501    i915->intel.vtbl.meta_color_mask = meta_color_mask;
 502    i915->intel.vtbl.meta_no_texture = meta_no_texture;
 503    i915->intel.vtbl.meta_texture_blend_replace = meta_texture_blend_replace;
 504    i915->intel.vtbl.meta_tex_rect_source = meta_tex_rect_source;
 505    i915->intel.vtbl.meta_draw_region = meta_draw_region;
 506    i915->intel.vtbl.meta_import_pixel_state = meta_import_pixel_state;
 507 }