src/mesa/drivers/dri/i915/i915_metaops.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "glheader.h"
  29 #include "enums.h"
  30 #include "mtypes.h"
  31 #include "macros.h"
  32 #include "utils.h"
  33
  34 #include "intel_screen.h"
  35 #include "intel_batchbuffer.h"
  36 #include "intel_ioctl.h"
  37 #include "intel_regions.h"
  38 #include "intel_rotate.h"
  39
  40 #include "i915_context.h"
  41 #include "i915_reg.h"
  42
  43 /* We touch almost everything:
  44  */
  45 #define ACTIVE (I915_UPLOAD_INVARIENT |         \
  46                 I915_UPLOAD_CTX |               \
  47                 I915_UPLOAD_BUFFERS |           \
  48                 I915_UPLOAD_STIPPLE |           \
  49                 I915_UPLOAD_PROGRAM |           \
  50                 I915_UPLOAD_FOG |               \
  51                 I915_UPLOAD_TEX(0))
  52
  53 #define SET_STATE( i915, STATE )                \
  54 do {                                            \
  55    i915->current->emitted &= ~ACTIVE;           \
  56    i915->current = &i915->STATE;                \
  57    i915->current->emitted &= ~ACTIVE;           \
  58 } while (0)
  59
  60
  61 static void
  62 meta_no_stencil_write(struct intel_context *intel)
  63 {
  64    struct i915_context *i915 = i915_context(&intel->ctx);
  65
  66    /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_FALSE )
  67     */
  68    i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_TEST_ENABLE |
  69                                          S5_STENCIL_WRITE_ENABLE);
  70
  71    i915->meta.emitted &= ~I915_UPLOAD_CTX;
  72 }
  73
  74 static void
  75 meta_no_depth_write(struct intel_context *intel)
  76 {
  77    struct i915_context *i915 = i915_context(&intel->ctx);
  78
  79    /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE )
  80     */
  81    i915->meta.Ctx[I915_CTXREG_LIS6] &= ~(S6_DEPTH_TEST_ENABLE |
  82                                          S6_DEPTH_WRITE_ENABLE);
  83
  84    i915->meta.emitted &= ~I915_UPLOAD_CTX;
  85 }
  86
  87 static void
  88 meta_depth_replace(struct intel_context *intel)
  89 {
  90    struct i915_context *i915 = i915_context(&intel->ctx);
  91
  92    /* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_TRUE )
  93     * ctx->Driver.DepthMask( ctx, GL_TRUE )
  94     */
  95    i915->meta.Ctx[I915_CTXREG_LIS6] |= (S6_DEPTH_TEST_ENABLE |
  96                                         S6_DEPTH_WRITE_ENABLE);
  97
  98    /* ctx->Driver.DepthFunc( ctx, GL_ALWAYS )
  99     */
 100    i915->meta.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_TEST_FUNC_MASK;
 101    i915->meta.Ctx[I915_CTXREG_LIS6] |=
 102       COMPAREFUNC_ALWAYS << S6_DEPTH_TEST_FUNC_SHIFT;
 103
 104    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 105 }
 106
 107
 108 /* Set stencil unit to replace always with the reference value.
 109  */
 110 static void
 111 meta_stencil_replace(struct intel_context *intel,
 112                      GLuint s_mask, GLuint s_clear)
 113 {
 114    struct i915_context *i915 = i915_context(&intel->ctx);
 115    GLuint op = STENCILOP_REPLACE;
 116    GLuint func = COMPAREFUNC_ALWAYS;
 117
 118    /* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_TRUE )
 119     */
 120    i915->meta.Ctx[I915_CTXREG_LIS5] |= (S5_STENCIL_TEST_ENABLE |
 121                                         S5_STENCIL_WRITE_ENABLE);
 122
 123    /* ctx->Driver.StencilMask( ctx, s_mask )
 124     */
 125    i915->meta.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
 126
 127    i915->meta.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK |
 128                                           STENCIL_WRITE_MASK(s_mask));
 129
 130    /* ctx->Driver.StencilOp( ctx, GL_REPLACE, GL_REPLACE, GL_REPLACE )
 131     */
 132    i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_FAIL_MASK |
 133                                          S5_STENCIL_PASS_Z_FAIL_MASK |
 134                                          S5_STENCIL_PASS_Z_PASS_MASK);
 135
 136    i915->meta.Ctx[I915_CTXREG_LIS5] |= ((op << S5_STENCIL_FAIL_SHIFT) |
 137                                         (op << S5_STENCIL_PASS_Z_FAIL_SHIFT) |
 138                                         (op << S5_STENCIL_PASS_Z_PASS_SHIFT));
 139
 140
 141    /* ctx->Driver.StencilFunc( ctx, GL_ALWAYS, s_ref, ~0 )
 142     */
 143    i915->meta.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK;
 144    i915->meta.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
 145                                           STENCIL_TEST_MASK(0xff));
 146
 147    i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_REF_MASK |
 148                                          S5_STENCIL_TEST_FUNC_MASK);
 149
 150    i915->meta.Ctx[I915_CTXREG_LIS5] |= ((s_clear << S5_STENCIL_REF_SHIFT) |
 151                                         (func << S5_STENCIL_TEST_FUNC_SHIFT));
 152
 153
 154    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 155 }
 156
 157
 158 static void
 159 meta_color_mask(struct intel_context *intel, GLboolean state)
 160 {
 161    struct i915_context *i915 = i915_context(&intel->ctx);
 162    const GLuint mask = (S5_WRITEDISABLE_RED |
 163                         S5_WRITEDISABLE_GREEN |
 164                         S5_WRITEDISABLE_BLUE | S5_WRITEDISABLE_ALPHA);
 165
 166    /* Copy colormask state from "regular" hw context.
 167     */
 168    if (state) {
 169       i915->meta.Ctx[I915_CTXREG_LIS5] &= ~mask;
 170       i915->meta.Ctx[I915_CTXREG_LIS5] |=
 171          (i915->state.Ctx[I915_CTXREG_LIS5] & mask);
 172    }
 173    else
 174       i915->meta.Ctx[I915_CTXREG_LIS5] |= mask;
 175
 176    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 177 }
 178
 179
 180
 181 static void
 182 meta_import_pixel_state(struct intel_context *intel)
 183 {
 184    struct i915_context *i915 = i915_context(&intel->ctx);
 185    memcpy(i915->meta.Fog, i915->state.Fog, I915_FOG_SETUP_SIZE * 4);
 186
 187    i915->meta.Ctx[I915_CTXREG_LIS5] = i915->state.Ctx[I915_CTXREG_LIS5];
 188    i915->meta.Ctx[I915_CTXREG_LIS6] = i915->state.Ctx[I915_CTXREG_LIS6];
 189    i915->meta.Ctx[I915_CTXREG_STATE4] = i915->state.Ctx[I915_CTXREG_STATE4];
 190    i915->meta.Ctx[I915_CTXREG_BLENDCOLOR1] =
 191       i915->state.Ctx[I915_CTXREG_BLENDCOLOR1];
 192    i915->meta.Ctx[I915_CTXREG_IAB] = i915->state.Ctx[I915_CTXREG_IAB];
 193
 194    i915->meta.Buffer[I915_DESTREG_SENABLE] =
 195       i915->state.Buffer[I915_DESTREG_SENABLE];
 196    i915->meta.Buffer[I915_DESTREG_SR1] = i915->state.Buffer[I915_DESTREG_SR1];
 197    i915->meta.Buffer[I915_DESTREG_SR2] = i915->state.Buffer[I915_DESTREG_SR2];
 198
 199    i915->meta.emitted &= ~I915_UPLOAD_FOG;
 200    i915->meta.emitted &= ~I915_UPLOAD_BUFFERS;
 201    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 202 }
 203
 204
 205
 206
 207 #define REG( type, nr ) (((type)<<5)|(nr))
 208
 209 #define REG_R(x)       REG(REG_TYPE_R, x)
 210 #define REG_T(x)       REG(REG_TYPE_T, x)
 211 #define REG_CONST(x)   REG(REG_TYPE_CONST, x)
 212 #define REG_S(x)       REG(REG_TYPE_S, x)
 213 #define REG_OC         REG(REG_TYPE_OC, 0)
 214 #define REG_OD         REG(REG_TYPE_OD, 0)
 215 #define REG_U(x)       REG(REG_TYPE_U, x)
 216
 217 #define REG_T_DIFFUSE  REG(REG_TYPE_T, T_DIFFUSE)
 218 #define REG_T_SPECULAR REG(REG_TYPE_T, T_SPECULAR)
 219 #define REG_T_FOG_W    REG(REG_TYPE_T, T_FOG_W)
 220 #define REG_T_TEX(x)   REG(REG_TYPE_T, x)
 221
 222
 223 #define A0_DEST_REG( reg ) ( (reg) << A0_DEST_NR_SHIFT )
 224 #define A0_SRC0_REG( reg ) ( (reg) << A0_SRC0_NR_SHIFT )
 225 #define A1_SRC1_REG( reg ) ( (reg) << A1_SRC1_NR_SHIFT )
 226 #define A1_SRC2_REG( reg ) ( (reg) << A1_SRC2_NR_SHIFT )
 227 #define A2_SRC2_REG( reg ) ( (reg) << A2_SRC2_NR_SHIFT )
 228 #define D0_DECL_REG( reg ) ( (reg) << D0_NR_SHIFT )
 229 #define T0_DEST_REG( reg ) ( (reg) << T0_DEST_NR_SHIFT )
 230
 231 #define T0_SAMPLER( unit )     ((unit)<<T0_SAMPLER_NR_SHIFT)
 232
 233 #define T1_ADDRESS_REG( type, nr ) (((type)<<T1_ADDRESS_REG_TYPE_SHIFT)| \
 234                                     ((nr)<<T1_ADDRESS_REG_NR_SHIFT))
 235
 236
 237 #define A1_SRC0_XYZW ((SRC_X << A1_SRC0_CHANNEL_X_SHIFT) |      \
 238                       (SRC_Y << A1_SRC0_CHANNEL_Y_SHIFT) |      \
 239                       (SRC_Z << A1_SRC0_CHANNEL_Z_SHIFT) |      \
 240                       (SRC_W << A1_SRC0_CHANNEL_W_SHIFT))
 241
 242 #define A1_SRC1_XY   ((SRC_X << A1_SRC1_CHANNEL_X_SHIFT) |      \
 243                       (SRC_Y << A1_SRC1_CHANNEL_Y_SHIFT))
 244
 245 #define A2_SRC1_ZW   ((SRC_Z << A2_SRC1_CHANNEL_Z_SHIFT) |      \
 246                       (SRC_W << A2_SRC1_CHANNEL_W_SHIFT))
 247
 248 #define A2_SRC2_XYZW ((SRC_X << A2_SRC2_CHANNEL_X_SHIFT) |      \
 249                       (SRC_Y << A2_SRC2_CHANNEL_Y_SHIFT) |      \
 250                       (SRC_Z << A2_SRC2_CHANNEL_Z_SHIFT) |      \
 251                       (SRC_W << A2_SRC2_CHANNEL_W_SHIFT))
 252
 253
 254
 255
 256
 257 static void
 258 meta_no_texture(struct intel_context *intel)
 259 {
 260    struct i915_context *i915 = i915_context(&intel->ctx);
 261
 262    static const GLuint prog[] = {
 263       _3DSTATE_PIXEL_SHADER_PROGRAM,
 264
 265       /* Declare incoming diffuse color:
 266        */
 267       (D0_DCL | D0_DECL_REG(REG_T_DIFFUSE) | D0_CHANNEL_ALL),
 268       D1_MBZ,
 269       D2_MBZ,
 270
 271       /* output-color = mov(t_diffuse)
 272        */
 273       (A0_MOV |
 274        A0_DEST_REG(REG_OC) |
 275        A0_DEST_CHANNEL_ALL | A0_SRC0_REG(REG_T_DIFFUSE)),
 276       (A1_SRC0_XYZW),
 277       0,
 278    };
 279
 280
 281    memcpy(i915->meta.Program, prog, sizeof(prog));
 282    i915->meta.ProgramSize = sizeof(prog) / sizeof(*prog);
 283    i915->meta.Program[0] |= i915->meta.ProgramSize - 2;
 284    i915->meta.emitted &= ~I915_UPLOAD_PROGRAM;
 285 }
 286
 287 static void
 288 meta_texture_blend_replace(struct intel_context *intel)
 289 {
 290    struct i915_context *i915 = i915_context(&intel->ctx);
 291
 292    static const GLuint prog[] = {
 293       _3DSTATE_PIXEL_SHADER_PROGRAM,
 294
 295       /* Declare the sampler:
 296        */
 297       (D0_DCL | D0_DECL_REG(REG_S(0)) | D0_SAMPLE_TYPE_2D | D0_CHANNEL_NONE),
 298       D1_MBZ,
 299       D2_MBZ,
 300
 301       /* Declare the interpolated texture coordinate:
 302        */
 303       (D0_DCL | D0_DECL_REG(REG_T_TEX(0)) | D0_CHANNEL_ALL),
 304       D1_MBZ,
 305       D2_MBZ,
 306
 307       /* output-color = texld(sample0, texcoord0)
 308        */
 309       (T0_TEXLD | T0_DEST_REG(REG_OC) | T0_SAMPLER(0)),
 310       T1_ADDRESS_REG(REG_TYPE_T, 0),
 311       T2_MBZ
 312    };
 313
 314    memcpy(i915->meta.Program, prog, sizeof(prog));
 315    i915->meta.ProgramSize = sizeof(prog) / sizeof(*prog);
 316    i915->meta.Program[0] |= i915->meta.ProgramSize - 2;
 317    i915->meta.emitted &= ~I915_UPLOAD_PROGRAM;
 318 }
 319
 320
 321
 322
 323
 324 /* Set up an arbitary piece of memory as a rectangular texture
 325  * (including the front or back buffer).
 326  */
 327 static GLboolean
 328 meta_tex_rect_source(struct intel_context *intel,
 329                      dri_bo *buffer,
 330                      GLuint offset,
 331                      GLuint pitch, GLuint height, GLenum format, GLenum type)
 332 {
 333    struct i915_context *i915 = i915_context(&intel->ctx);
 334    GLuint unit = 0;
 335    GLint numLevels = 1;
 336    GLuint *state = i915->meta.Tex[0];
 337    GLuint textureFormat;
 338    GLuint cpp;
 339
 340    /* A full implementation of this would do the upload through
 341     * glTexImage2d, and get all the conversion operations at that
 342     * point.  We are restricted, but still at least have access to the
 343     * fragment program swizzle.
 344     */
 345    switch (format) {
 346    case GL_BGRA:
 347       switch (type) {
 348       case GL_UNSIGNED_INT_8_8_8_8_REV:
 349       case GL_UNSIGNED_BYTE:
 350          textureFormat = (MAPSURF_32BIT | MT_32BIT_ARGB8888);
 351          cpp = 4;
 352          break;
 353       default:
 354          return GL_FALSE;
 355       }
 356       break;
 357    case GL_RGBA:
 358       switch (type) {
 359       case GL_UNSIGNED_INT_8_8_8_8_REV:
 360       case GL_UNSIGNED_BYTE:
 361          textureFormat = (MAPSURF_32BIT | MT_32BIT_ABGR8888);
 362          cpp = 4;
 363          break;
 364       default:
 365          return GL_FALSE;
 366       }
 367       break;
 368    case GL_BGR:
 369       switch (type) {
 370       case GL_UNSIGNED_SHORT_5_6_5_REV:
 371          textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565);
 372          cpp = 2;
 373          break;
 374       default:
 375          return GL_FALSE;
 376       }
 377       break;
 378    case GL_RGB:
 379       switch (type) {
 380       case GL_UNSIGNED_SHORT_5_6_5:
 381          textureFormat = (MAPSURF_16BIT | MT_16BIT_RGB565);
 382          cpp = 2;
 383          break;
 384       default:
 385          return GL_FALSE;
 386       }
 387       break;
 388
 389    default:
 390       return GL_FALSE;
 391    }
 392
 393
 394    if ((pitch * cpp) & 3) {
 395       _mesa_printf("%s: texture is not dword pitch\n", __FUNCTION__);
 396       return GL_FALSE;
 397    }
 398
 399 /*    intel_region_release(&i915->meta.tex_region[0]); */
 400 /*    intel_region_reference(&i915->meta.tex_region[0], region); */
 401    i915->meta.tex_buffer[0] = buffer;
 402    i915->meta.tex_offset[0] = offset;
 403
 404    state[I915_TEXREG_MS3] = (((height - 1) << MS3_HEIGHT_SHIFT) |
 405                              ((pitch - 1) << MS3_WIDTH_SHIFT) |
 406                              textureFormat | MS3_USE_FENCE_REGS);
 407
 408    state[I915_TEXREG_MS4] = (((((pitch * cpp) / 4) - 1) << MS4_PITCH_SHIFT) |
 409                              MS4_CUBE_FACE_ENA_MASK |
 410                              ((((numLevels - 1) * 4)) << MS4_MAX_LOD_SHIFT));
 411
 412    state[I915_TEXREG_SS2] = ((FILTER_NEAREST << SS2_MIN_FILTER_SHIFT) |
 413                              (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT) |
 414                              (FILTER_NEAREST << SS2_MAG_FILTER_SHIFT));
 415
 416    state[I915_TEXREG_SS3] = ((TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT) |
 417                              (TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT) |
 418                              (TEXCOORDMODE_WRAP << SS3_TCZ_ADDR_MODE_SHIFT) |
 419                              (unit << SS3_TEXTUREMAP_INDEX_SHIFT));
 420
 421    state[I915_TEXREG_SS4] = 0;
 422
 423    i915->meta.emitted &= ~I915_UPLOAD_TEX(0);
 424    return GL_TRUE;
 425 }
 426
 427
 428 /**
 429  * Set the color and depth drawing region for meta ops.
 430  */
 431 static void
 432 meta_draw_region(struct intel_context *intel,
 433                  struct intel_region *color_region,
 434                  struct intel_region *depth_region)
 435 {
 436    struct i915_context *i915 = i915_context(&intel->ctx);
 437    i915_state_draw_region(intel, &i915->meta, color_region, depth_region);
 438 }
 439
 440
 441 static void
 442 set_vertex_format(struct intel_context *intel)
 443 {
 444    struct i915_context *i915 = i915_context(&intel->ctx);
 445
 446    i915->meta.Ctx[I915_CTXREG_LIS2] =
 447       (S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) |
 448        S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT) |
 449        S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) |
 450        S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) |
 451        S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) |
 452        S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) |
 453        S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) |
 454        S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT));
 455
 456    i915->meta.Ctx[I915_CTXREG_LIS4] &= ~S4_VFMT_MASK;
 457
 458    i915->meta.Ctx[I915_CTXREG_LIS4] |= (S4_VFMT_COLOR | S4_VFMT_XYZ);
 459
 460    i915->meta.emitted &= ~I915_UPLOAD_CTX;
 461 }
 462
 463
 464
 465 /* Operations where the 3D engine is decoupled temporarily from the
 466  * current GL state and used for other purposes than simply rendering
 467  * incoming triangles.
 468  */
 469 static void
 470 install_meta_state(struct intel_context *intel)
 471 {
 472    struct i915_context *i915 = i915_context(&intel->ctx);
 473    memcpy(&i915->meta, &i915->initial, sizeof(i915->meta));
 474    i915->meta.active = ACTIVE;
 475    i915->meta.emitted = 0;
 476
 477    SET_STATE(i915, meta);
 478    set_vertex_format(intel);
 479    meta_no_texture(intel);
 480 }
 481
 482 static void
 483 leave_meta_state(struct intel_context *intel)
 484 {
 485    struct i915_context *i915 = i915_context(&intel->ctx);
 486    intel_region_release(&i915->meta.draw_region);
 487    intel_region_release(&i915->meta.depth_region);
 488 /*    intel_region_release(&i915->meta.tex_region[0]); */
 489    SET_STATE(i915, state);
 490 }
 491
 492
 493
 494 void
 495 i915InitMetaFuncs(struct i915_context *i915)
 496 {
 497    i915->intel.vtbl.install_meta_state = install_meta_state;
 498    i915->intel.vtbl.leave_meta_state = leave_meta_state;
 499    i915->intel.vtbl.meta_no_depth_write = meta_no_depth_write;
 500    i915->intel.vtbl.meta_no_stencil_write = meta_no_stencil_write;
 501    i915->intel.vtbl.meta_stencil_replace = meta_stencil_replace;
 502    i915->intel.vtbl.meta_depth_replace = meta_depth_replace;
 503    i915->intel.vtbl.meta_color_mask = meta_color_mask;
 504    i915->intel.vtbl.meta_no_texture = meta_no_texture;
 505    i915->intel.vtbl.meta_texture_blend_replace = meta_texture_blend_replace;
 506    i915->intel.vtbl.meta_tex_rect_source = meta_tex_rect_source;
 507    i915->intel.vtbl.meta_draw_region = meta_draw_region;
 508    i915->intel.vtbl.meta_import_pixel_state = meta_import_pixel_state;
 509 }