1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/glheader.h"
30 #include "main/context.h"
31 #include "main/macros.h"
32 #include "main/enums.h"
34 #include "main/state.h"
36 #include "tnl/t_context.h"
40 #include "drivers/common/driverfuncs.h"
42 #include "intel_fbo.h"
43 #include "intel_screen.h"
44 #include "intel_batchbuffer.h"
45 #include "intel_buffers.h"
47 #include "i915_context.h"
50 #define FILE_DEBUG_FLAG DEBUG_STATE
53 i915_update_stencil(struct gl_context
* ctx
)
55 struct i915_context
*i915
= I915_CONTEXT(ctx
);
56 GLuint front_ref
, front_writemask
, front_mask
;
57 GLenum front_func
, front_fail
, front_pass_z_fail
, front_pass_z_pass
;
58 GLuint back_ref
, back_writemask
, back_mask
;
59 GLenum back_func
, back_fail
, back_pass_z_fail
, back_pass_z_pass
;
62 /* The 915 considers CW to be "front" for two-sided stencil, so choose
65 /* _NEW_POLYGON | _NEW_STENCIL */
66 if (ctx
->Polygon
.FrontFace
== GL_CW
) {
67 front_ref
= ctx
->Stencil
.Ref
[0];
68 front_mask
= ctx
->Stencil
.ValueMask
[0];
69 front_writemask
= ctx
->Stencil
.WriteMask
[0];
70 front_func
= ctx
->Stencil
.Function
[0];
71 front_fail
= ctx
->Stencil
.FailFunc
[0];
72 front_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[0];
73 front_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[0];
74 back_ref
= ctx
->Stencil
.Ref
[ctx
->Stencil
._BackFace
];
75 back_mask
= ctx
->Stencil
.ValueMask
[ctx
->Stencil
._BackFace
];
76 back_writemask
= ctx
->Stencil
.WriteMask
[ctx
->Stencil
._BackFace
];
77 back_func
= ctx
->Stencil
.Function
[ctx
->Stencil
._BackFace
];
78 back_fail
= ctx
->Stencil
.FailFunc
[ctx
->Stencil
._BackFace
];
79 back_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[ctx
->Stencil
._BackFace
];
80 back_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[ctx
->Stencil
._BackFace
];
82 front_ref
= ctx
->Stencil
.Ref
[ctx
->Stencil
._BackFace
];
83 front_mask
= ctx
->Stencil
.ValueMask
[ctx
->Stencil
._BackFace
];
84 front_writemask
= ctx
->Stencil
.WriteMask
[ctx
->Stencil
._BackFace
];
85 front_func
= ctx
->Stencil
.Function
[ctx
->Stencil
._BackFace
];
86 front_fail
= ctx
->Stencil
.FailFunc
[ctx
->Stencil
._BackFace
];
87 front_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[ctx
->Stencil
._BackFace
];
88 front_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[ctx
->Stencil
._BackFace
];
89 back_ref
= ctx
->Stencil
.Ref
[0];
90 back_mask
= ctx
->Stencil
.ValueMask
[0];
91 back_writemask
= ctx
->Stencil
.WriteMask
[0];
92 back_func
= ctx
->Stencil
.Function
[0];
93 back_fail
= ctx
->Stencil
.FailFunc
[0];
94 back_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[0];
95 back_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[0];
97 #define set_ctx_bits(reg, mask, set) do{ \
98 GLuint dw = i915->state.Ctx[reg]; \
101 dirty |= dw != i915->state.Ctx[reg]; \
102 i915->state.Ctx[reg] = dw; \
105 /* Set front state. */
106 set_ctx_bits(I915_CTXREG_STATE4
,
107 MODE4_ENABLE_STENCIL_TEST_MASK
|
108 MODE4_ENABLE_STENCIL_WRITE_MASK
,
109 ENABLE_STENCIL_TEST_MASK
|
110 ENABLE_STENCIL_WRITE_MASK
|
111 STENCIL_TEST_MASK(front_mask
) |
112 STENCIL_WRITE_MASK(front_writemask
));
114 set_ctx_bits(I915_CTXREG_LIS5
,
115 S5_STENCIL_REF_MASK
|
116 S5_STENCIL_TEST_FUNC_MASK
|
117 S5_STENCIL_FAIL_MASK
|
118 S5_STENCIL_PASS_Z_FAIL_MASK
|
119 S5_STENCIL_PASS_Z_PASS_MASK
,
120 (front_ref
<< S5_STENCIL_REF_SHIFT
) |
121 (intel_translate_compare_func(front_func
) << S5_STENCIL_TEST_FUNC_SHIFT
) |
122 (intel_translate_stencil_op(front_fail
) << S5_STENCIL_FAIL_SHIFT
) |
123 (intel_translate_stencil_op(front_pass_z_fail
) <<
124 S5_STENCIL_PASS_Z_FAIL_SHIFT
) |
125 (intel_translate_stencil_op(front_pass_z_pass
) <<
126 S5_STENCIL_PASS_Z_PASS_SHIFT
));
128 /* Set back state if different from front. */
129 if (ctx
->Stencil
._TestTwoSide
) {
130 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS
,
131 BFO_STENCIL_REF_MASK
|
132 BFO_STENCIL_TEST_MASK
|
133 BFO_STENCIL_FAIL_MASK
|
134 BFO_STENCIL_PASS_Z_FAIL_MASK
|
135 BFO_STENCIL_PASS_Z_PASS_MASK
,
136 BFO_STENCIL_TWO_SIDE
|
137 (back_ref
<< BFO_STENCIL_REF_SHIFT
) |
138 (intel_translate_compare_func(back_func
) << BFO_STENCIL_TEST_SHIFT
) |
139 (intel_translate_stencil_op(back_fail
) << BFO_STENCIL_FAIL_SHIFT
) |
140 (intel_translate_stencil_op(back_pass_z_fail
) <<
141 BFO_STENCIL_PASS_Z_FAIL_SHIFT
) |
142 (intel_translate_stencil_op(back_pass_z_pass
) <<
143 BFO_STENCIL_PASS_Z_PASS_SHIFT
));
145 set_ctx_bits(I915_CTXREG_BF_STENCIL_MASKS
,
146 BFM_STENCIL_TEST_MASK_MASK
|
147 BFM_STENCIL_WRITE_MASK_MASK
,
148 BFM_STENCIL_TEST_MASK(back_mask
) |
149 BFM_STENCIL_WRITE_MASK(back_writemask
));
151 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS
,
152 BFO_STENCIL_TWO_SIDE
, 0);
158 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
162 i915StencilFuncSeparate(struct gl_context
* ctx
, GLenum face
, GLenum func
, GLint ref
,
168 i915StencilMaskSeparate(struct gl_context
* ctx
, GLenum face
, GLuint mask
)
173 i915StencilOpSeparate(struct gl_context
* ctx
, GLenum face
, GLenum fail
, GLenum zfail
,
179 i915AlphaFunc(struct gl_context
* ctx
, GLenum func
, GLfloat ref
)
181 struct i915_context
*i915
= I915_CONTEXT(ctx
);
182 int test
= intel_translate_compare_func(func
);
186 UNCLAMPED_FLOAT_TO_UBYTE(refByte
, ref
);
188 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
189 dw
&= ~(S6_ALPHA_TEST_FUNC_MASK
| S6_ALPHA_REF_MASK
);
190 dw
|= ((test
<< S6_ALPHA_TEST_FUNC_SHIFT
) |
191 (((GLuint
) refByte
) << S6_ALPHA_REF_SHIFT
));
192 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
193 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
194 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
198 /* This function makes sure that the proper enables are
199 * set for LogicOp, Independant Alpha Blend, and Blending.
200 * It needs to be called from numerous places where we
201 * could change the LogicOp or Independant Alpha Blend without subsequent
205 i915EvalLogicOpBlendState(struct gl_context
* ctx
)
207 struct i915_context
*i915
= I915_CONTEXT(ctx
);
210 dw0
= i915
->state
.Ctx
[I915_CTXREG_LIS5
];
211 dw1
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
213 if (ctx
->Color
.ColorLogicOpEnabled
) {
214 dw0
|= S5_LOGICOP_ENABLE
;
215 dw1
&= ~S6_CBUF_BLEND_ENABLE
;
218 dw0
&= ~S5_LOGICOP_ENABLE
;
220 if (ctx
->Color
.BlendEnabled
) {
221 dw1
|= S6_CBUF_BLEND_ENABLE
;
224 dw1
&= ~S6_CBUF_BLEND_ENABLE
;
227 if (dw0
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
] ||
228 dw1
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
229 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = dw0
;
230 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw1
;
232 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
237 i915BlendColor(struct gl_context
* ctx
, const GLfloat color
[4])
239 struct i915_context
*i915
= I915_CONTEXT(ctx
);
243 DBG("%s\n", __FUNCTION__
);
245 UNCLAMPED_FLOAT_TO_UBYTE(r
, color
[RCOMP
]);
246 UNCLAMPED_FLOAT_TO_UBYTE(g
, color
[GCOMP
]);
247 UNCLAMPED_FLOAT_TO_UBYTE(b
, color
[BCOMP
]);
248 UNCLAMPED_FLOAT_TO_UBYTE(a
, color
[ACOMP
]);
250 dw
= (a
<< 24) | (r
<< 16) | (g
<< 8) | b
;
251 if (dw
!= i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR1
]) {
252 i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR1
] = dw
;
253 I915_STATECHANGE(i915
, I915_UPLOAD_BLEND
);
258 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
259 #define SRC_BLND_FACT(f) ((f)<<S6_CBUF_SRC_BLEND_FACT_SHIFT)
260 #define DST_ABLND_FACT(f) ((f)<<IAB_DST_FACTOR_SHIFT)
261 #define SRC_ABLND_FACT(f) ((f)<<IAB_SRC_FACTOR_SHIFT)
266 translate_blend_equation(GLenum mode
)
270 return BLENDFUNC_ADD
;
272 return BLENDFUNC_MIN
;
274 return BLENDFUNC_MAX
;
275 case GL_FUNC_SUBTRACT
:
276 return BLENDFUNC_SUBTRACT
;
277 case GL_FUNC_REVERSE_SUBTRACT
:
278 return BLENDFUNC_REVERSE_SUBTRACT
;
285 i915UpdateBlendState(struct gl_context
* ctx
)
287 struct i915_context
*i915
= I915_CONTEXT(ctx
);
288 GLuint iab
= (i915
->state
.Blend
[I915_BLENDREG_IAB
] &
289 ~(IAB_SRC_FACTOR_MASK
|
290 IAB_DST_FACTOR_MASK
|
291 (BLENDFUNC_MASK
<< IAB_FUNC_SHIFT
) | IAB_ENABLE
));
293 GLuint lis6
= (i915
->state
.Ctx
[I915_CTXREG_LIS6
] &
294 ~(S6_CBUF_SRC_BLEND_FACT_MASK
|
295 S6_CBUF_DST_BLEND_FACT_MASK
| S6_CBUF_BLEND_FUNC_MASK
));
297 GLuint eqRGB
= ctx
->Color
.Blend
[0].EquationRGB
;
298 GLuint eqA
= ctx
->Color
.Blend
[0].EquationA
;
299 GLuint srcRGB
= ctx
->Color
.Blend
[0].SrcRGB
;
300 GLuint dstRGB
= ctx
->Color
.Blend
[0].DstRGB
;
301 GLuint srcA
= ctx
->Color
.Blend
[0].SrcA
;
302 GLuint dstA
= ctx
->Color
.Blend
[0].DstA
;
304 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
) {
305 srcRGB
= dstRGB
= GL_ONE
;
308 if (eqA
== GL_MIN
|| eqA
== GL_MAX
) {
309 srcA
= dstA
= GL_ONE
;
312 lis6
|= SRC_BLND_FACT(intel_translate_blend_factor(srcRGB
));
313 lis6
|= DST_BLND_FACT(intel_translate_blend_factor(dstRGB
));
314 lis6
|= translate_blend_equation(eqRGB
) << S6_CBUF_BLEND_FUNC_SHIFT
;
316 iab
|= SRC_ABLND_FACT(intel_translate_blend_factor(srcA
));
317 iab
|= DST_ABLND_FACT(intel_translate_blend_factor(dstA
));
318 iab
|= translate_blend_equation(eqA
) << IAB_FUNC_SHIFT
;
320 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
323 if (iab
!= i915
->state
.Blend
[I915_BLENDREG_IAB
]) {
324 i915
->state
.Blend
[I915_BLENDREG_IAB
] = iab
;
325 I915_STATECHANGE(i915
, I915_UPLOAD_BLEND
);
327 if (lis6
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
328 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = lis6
;
329 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
332 /* This will catch a logicop blend equation */
333 i915EvalLogicOpBlendState(ctx
);
338 i915BlendFuncSeparate(struct gl_context
* ctx
, GLenum srcRGB
,
339 GLenum dstRGB
, GLenum srcA
, GLenum dstA
)
341 i915UpdateBlendState(ctx
);
346 i915BlendEquationSeparate(struct gl_context
* ctx
, GLenum eqRGB
, GLenum eqA
)
348 i915UpdateBlendState(ctx
);
353 i915DepthFunc(struct gl_context
* ctx
, GLenum func
)
355 struct i915_context
*i915
= I915_CONTEXT(ctx
);
356 int test
= intel_translate_compare_func(func
);
359 DBG("%s\n", __FUNCTION__
);
361 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
362 dw
&= ~S6_DEPTH_TEST_FUNC_MASK
;
363 dw
|= test
<< S6_DEPTH_TEST_FUNC_SHIFT
;
364 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
365 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
366 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
371 i915DepthMask(struct gl_context
* ctx
, GLboolean flag
)
373 struct i915_context
*i915
= I915_CONTEXT(ctx
);
376 DBG("%s flag (%d)\n", __FUNCTION__
, flag
);
378 if (!ctx
->DrawBuffer
|| !ctx
->DrawBuffer
->Visual
.depthBits
)
381 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
382 if (flag
&& ctx
->Depth
.Test
)
383 dw
|= S6_DEPTH_WRITE_ENABLE
;
385 dw
&= ~S6_DEPTH_WRITE_ENABLE
;
386 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
387 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
388 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
395 * Update the viewport transformation matrix. Depends on:
396 * - viewport pos/size
398 * - window pos/size or FBO size
401 intelCalcViewport(struct gl_context
* ctx
)
403 struct intel_context
*intel
= intel_context(ctx
);
405 if (ctx
->DrawBuffer
->Name
== 0) {
406 _math_matrix_viewport(&intel
->ViewportMatrix
,
408 ctx
->DrawBuffer
->Height
- ctx
->Viewport
.Y
,
410 -ctx
->Viewport
.Height
,
415 _math_matrix_viewport(&intel
->ViewportMatrix
,
419 ctx
->Viewport
.Height
,
427 /** Called from ctx->Driver.Viewport() */
429 i915Viewport(struct gl_context
* ctx
,
430 GLint x
, GLint y
, GLsizei width
, GLsizei height
)
432 intelCalcViewport(ctx
);
436 /** Called from ctx->Driver.DepthRange() */
438 i915DepthRange(struct gl_context
* ctx
, GLclampd nearval
, GLclampd farval
)
440 intelCalcViewport(ctx
);
444 /* =============================================================
447 * The i915 supports a 4x4 stipple natively, GL wants 32x32.
448 * Fortunately stipple is usually a repeating pattern.
451 i915PolygonStipple(struct gl_context
* ctx
, const GLubyte
* mask
)
453 struct i915_context
*i915
= I915_CONTEXT(ctx
);
457 int active
= (ctx
->Polygon
.StippleFlag
&&
458 i915
->intel
.reduced_primitive
== GL_TRIANGLES
);
462 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
463 i915
->state
.Stipple
[I915_STPREG_ST1
] &= ~ST1_ENABLE
;
466 /* Use the already unpacked stipple data from the context rather than the
467 * uninterpreted mask passed in.
469 mask
= (const GLubyte
*)ctx
->PolygonStipple
;
472 p
[0] = mask
[12] & 0xf;
474 p
[1] = mask
[8] & 0xf;
476 p
[2] = mask
[4] & 0xf;
478 p
[3] = mask
[0] & 0xf;
481 for (k
= 0; k
< 8; k
++)
482 for (j
= 3; j
>= 0; j
--)
483 for (i
= 0; i
< 4; i
++, m
++)
485 i915
->intel
.hw_stipple
= 0;
489 newMask
= (((p
[0] & 0xf) << 0) |
490 ((p
[1] & 0xf) << 4) |
491 ((p
[2] & 0xf) << 8) | ((p
[3] & 0xf) << 12));
494 if (newMask
== 0xffff || newMask
== 0x0) {
495 /* this is needed to make conform pass */
496 i915
->intel
.hw_stipple
= 0;
500 i915
->state
.Stipple
[I915_STPREG_ST1
] &= ~0xffff;
501 i915
->state
.Stipple
[I915_STPREG_ST1
] |= newMask
;
502 i915
->intel
.hw_stipple
= 1;
505 i915
->state
.Stipple
[I915_STPREG_ST1
] |= ST1_ENABLE
;
509 /* =============================================================
513 i915Scissor(struct gl_context
* ctx
, GLint x
, GLint y
, GLsizei w
, GLsizei h
)
515 struct i915_context
*i915
= I915_CONTEXT(ctx
);
518 if (!ctx
->DrawBuffer
)
521 DBG("%s %d,%d %dx%d\n", __FUNCTION__
, x
, y
, w
, h
);
523 if (ctx
->DrawBuffer
->Name
== 0) {
525 y1
= ctx
->DrawBuffer
->Height
- (y
+ h
);
528 DBG("%s %d..%d,%d..%d (inverted)\n", __FUNCTION__
, x1
, x2
, y1
, y2
);
531 /* FBO - not inverted
537 DBG("%s %d..%d,%d..%d (not inverted)\n", __FUNCTION__
, x1
, x2
, y1
, y2
);
540 x1
= CLAMP(x1
, 0, ctx
->DrawBuffer
->Width
- 1);
541 y1
= CLAMP(y1
, 0, ctx
->DrawBuffer
->Height
- 1);
542 x2
= CLAMP(x2
, 0, ctx
->DrawBuffer
->Width
- 1);
543 y2
= CLAMP(y2
, 0, ctx
->DrawBuffer
->Height
- 1);
545 DBG("%s %d..%d,%d..%d (clamped)\n", __FUNCTION__
, x1
, x2
, y1
, y2
);
547 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
548 i915
->state
.Buffer
[I915_DESTREG_SR1
] = (y1
<< 16) | (x1
& 0xffff);
549 i915
->state
.Buffer
[I915_DESTREG_SR2
] = (y2
<< 16) | (x2
& 0xffff);
553 i915LogicOp(struct gl_context
* ctx
, GLenum opcode
)
555 struct i915_context
*i915
= I915_CONTEXT(ctx
);
556 int tmp
= intel_translate_logic_op(opcode
);
558 DBG("%s\n", __FUNCTION__
);
560 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
561 i915
->state
.Ctx
[I915_CTXREG_STATE4
] &= ~LOGICOP_MASK
;
562 i915
->state
.Ctx
[I915_CTXREG_STATE4
] |= LOGIC_OP_FUNC(tmp
);
568 i915CullFaceFrontFace(struct gl_context
* ctx
, GLenum unused
)
570 struct i915_context
*i915
= I915_CONTEXT(ctx
);
573 DBG("%s %d\n", __FUNCTION__
,
574 ctx
->DrawBuffer
? ctx
->DrawBuffer
->Name
: 0);
576 if (!ctx
->Polygon
.CullFlag
) {
577 mode
= S4_CULLMODE_NONE
;
579 else if (ctx
->Polygon
.CullFaceMode
!= GL_FRONT_AND_BACK
) {
580 mode
= S4_CULLMODE_CW
;
582 if (ctx
->DrawBuffer
&& ctx
->DrawBuffer
->Name
!= 0)
583 mode
^= (S4_CULLMODE_CW
^ S4_CULLMODE_CCW
);
584 if (ctx
->Polygon
.CullFaceMode
== GL_FRONT
)
585 mode
^= (S4_CULLMODE_CW
^ S4_CULLMODE_CCW
);
586 if (ctx
->Polygon
.FrontFace
!= GL_CCW
)
587 mode
^= (S4_CULLMODE_CW
^ S4_CULLMODE_CCW
);
590 mode
= S4_CULLMODE_BOTH
;
593 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
594 dw
&= ~S4_CULLMODE_MASK
;
596 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
597 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = dw
;
598 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
603 i915LineWidth(struct gl_context
* ctx
, GLfloat widthf
)
605 struct i915_context
*i915
= I915_CONTEXT(ctx
);
606 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
] & ~S4_LINE_WIDTH_MASK
;
609 DBG("%s\n", __FUNCTION__
);
611 width
= (int) (widthf
* 2);
612 width
= CLAMP(width
, 1, 0xf);
613 lis4
|= width
<< S4_LINE_WIDTH_SHIFT
;
615 if (lis4
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
616 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
617 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = lis4
;
622 i915PointSize(struct gl_context
* ctx
, GLfloat size
)
624 struct i915_context
*i915
= I915_CONTEXT(ctx
);
625 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
] & ~S4_POINT_WIDTH_MASK
;
626 GLint point_size
= (int) round(size
);
628 DBG("%s\n", __FUNCTION__
);
630 point_size
= CLAMP(point_size
, 1, 255);
631 lis4
|= point_size
<< S4_POINT_WIDTH_SHIFT
;
633 if (lis4
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
634 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
635 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = lis4
;
641 i915PointParameterfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
*params
)
643 struct i915_context
*i915
= I915_CONTEXT(ctx
);
646 case GL_POINT_SPRITE_COORD_ORIGIN
:
647 /* This could be supported, but it would require modifying the fragment
648 * program to invert the y component of the texture coordinate by
649 * inserting a 'SUB tc.y, {1.0}.xxxx, tc' instruction.
651 FALLBACK(&i915
->intel
, I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN
,
652 (params
[0] != GL_UPPER_LEFT
));
658 /* =============================================================
663 i915ColorMask(struct gl_context
* ctx
,
664 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
)
666 struct i915_context
*i915
= I915_CONTEXT(ctx
);
667 GLuint tmp
= i915
->state
.Ctx
[I915_CTXREG_LIS5
] & ~S5_WRITEDISABLE_MASK
;
669 DBG("%s r(%d) g(%d) b(%d) a(%d)\n", __FUNCTION__
, r
, g
, b
,
673 tmp
|= S5_WRITEDISABLE_RED
;
675 tmp
|= S5_WRITEDISABLE_GREEN
;
677 tmp
|= S5_WRITEDISABLE_BLUE
;
679 tmp
|= S5_WRITEDISABLE_ALPHA
;
681 if (tmp
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
]) {
682 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
683 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = tmp
;
688 update_specular(struct gl_context
* ctx
)
690 /* A hack to trigger the rebuild of the fragment program.
692 intel_context(ctx
)->NewGLState
|= _NEW_TEXTURE
;
696 i915LightModelfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
)
698 DBG("%s\n", __FUNCTION__
);
700 if (pname
== GL_LIGHT_MODEL_COLOR_CONTROL
) {
701 update_specular(ctx
);
706 i915ShadeModel(struct gl_context
* ctx
, GLenum mode
)
708 struct i915_context
*i915
= I915_CONTEXT(ctx
);
709 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
711 if (mode
== GL_SMOOTH
) {
712 i915
->state
.Ctx
[I915_CTXREG_LIS4
] &= ~(S4_FLATSHADE_ALPHA
|
714 S4_FLATSHADE_SPECULAR
);
717 i915
->state
.Ctx
[I915_CTXREG_LIS4
] |= (S4_FLATSHADE_ALPHA
|
719 S4_FLATSHADE_SPECULAR
);
723 /* =============================================================
726 * This empty function remains because _mesa_init_driver_state calls
727 * dd_function_table::Fogfv unconditionally. We have to have some function
728 * there so that it doesn't try to call a NULL pointer.
731 i915Fogfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
)
738 /* =============================================================
742 i915Enable(struct gl_context
* ctx
, GLenum cap
, GLboolean state
)
744 struct i915_context
*i915
= I915_CONTEXT(ctx
);
753 update_specular(ctx
);
757 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
759 dw
|= S6_ALPHA_TEST_ENABLE
;
761 dw
&= ~S6_ALPHA_TEST_ENABLE
;
762 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
763 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
764 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
769 i915EvalLogicOpBlendState(ctx
);
772 case GL_COLOR_LOGIC_OP
:
773 i915EvalLogicOpBlendState(ctx
);
775 /* Logicop doesn't seem to work at 16bpp:
777 if (ctx
->Visual
.rgbBits
== 16)
778 FALLBACK(&i915
->intel
, I915_FALLBACK_LOGICOP
, state
);
781 case GL_FRAGMENT_PROGRAM_ARB
:
785 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS5
];
787 dw
|= S5_COLOR_DITHER_ENABLE
;
789 dw
&= ~S5_COLOR_DITHER_ENABLE
;
790 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
]) {
791 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = dw
;
792 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
797 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
799 if (!ctx
->DrawBuffer
|| !ctx
->DrawBuffer
->Visual
.depthBits
)
803 dw
|= S6_DEPTH_TEST_ENABLE
;
805 dw
&= ~S6_DEPTH_TEST_ENABLE
;
806 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
807 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
808 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
811 i915DepthMask(ctx
, ctx
->Depth
.Mask
);
814 case GL_SCISSOR_TEST
:
815 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
817 i915
->state
.Buffer
[I915_DESTREG_SENABLE
] =
818 (_3DSTATE_SCISSOR_ENABLE_CMD
| ENABLE_SCISSOR_RECT
);
820 i915
->state
.Buffer
[I915_DESTREG_SENABLE
] =
821 (_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
825 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
827 dw
|= S4_LINE_ANTIALIAS_ENABLE
;
829 dw
&= ~S4_LINE_ANTIALIAS_ENABLE
;
830 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
831 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = dw
;
832 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
837 i915CullFaceFrontFace(ctx
, 0);
840 case GL_STENCIL_TEST
:
841 if (!ctx
->DrawBuffer
|| !ctx
->DrawBuffer
->Visual
.stencilBits
)
844 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS5
];
846 dw
|= (S5_STENCIL_TEST_ENABLE
| S5_STENCIL_WRITE_ENABLE
);
848 dw
&= ~(S5_STENCIL_TEST_ENABLE
| S5_STENCIL_WRITE_ENABLE
);
849 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
]) {
850 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = dw
;
851 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
855 case GL_POLYGON_STIPPLE
:
856 /* The stipple command worked on my 855GM box, but not my 845G.
857 * I'll do more testing later to find out exactly which hardware
858 * supports it. Disabled for now.
860 if (i915
->intel
.hw_stipple
&&
861 i915
->intel
.reduced_primitive
== GL_TRIANGLES
) {
862 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
864 i915
->state
.Stipple
[I915_STPREG_ST1
] |= ST1_ENABLE
;
866 i915
->state
.Stipple
[I915_STPREG_ST1
] &= ~ST1_ENABLE
;
870 case GL_POLYGON_SMOOTH
:
873 case GL_POINT_SPRITE
:
874 /* This state change is handled in i915_reduced_primitive_state because
875 * the hardware bit should only be set when rendering points.
877 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
879 dw
|= S4_SPRITE_POINT_ENABLE
;
881 dw
&= ~S4_SPRITE_POINT_ENABLE
;
882 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
883 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = dw
;
884 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
888 case GL_POINT_SMOOTH
:
898 i915_init_packets(struct i915_context
*i915
)
901 memset(&i915
->state
, 0, sizeof(i915
->state
));
905 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
906 I915_STATECHANGE(i915
, I915_UPLOAD_BLEND
);
907 /* Probably don't want to upload all this stuff every time one
910 i915
->state
.Ctx
[I915_CTXREG_LI
] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1
|
913 I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
914 i915
->state
.Ctx
[I915_CTXREG_LIS2
] = 0;
915 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = 0;
916 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = 0;
918 if (i915
->intel
.ctx
.Visual
.rgbBits
== 16)
919 i915
->state
.Ctx
[I915_CTXREG_LIS5
] |= S5_COLOR_DITHER_ENABLE
;
922 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = (S6_COLOR_WRITE_ENABLE
|
923 (2 << S6_TRISTRIP_PV_SHIFT
));
925 i915
->state
.Ctx
[I915_CTXREG_STATE4
] = (_3DSTATE_MODES_4_CMD
|
926 ENABLE_LOGIC_OP_FUNC
|
927 LOGIC_OP_FUNC(LOGICOP_COPY
) |
928 ENABLE_STENCIL_TEST_MASK
|
929 STENCIL_TEST_MASK(0xff) |
930 ENABLE_STENCIL_WRITE_MASK
|
931 STENCIL_WRITE_MASK(0xff));
933 i915
->state
.Blend
[I915_BLENDREG_IAB
] =
934 (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD
| IAB_MODIFY_ENABLE
|
935 IAB_MODIFY_FUNC
| IAB_MODIFY_SRC_FACTOR
| IAB_MODIFY_DST_FACTOR
);
937 i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR0
] =
938 _3DSTATE_CONST_BLEND_COLOR_CMD
;
939 i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR1
] = 0;
941 i915
->state
.Ctx
[I915_CTXREG_BF_STENCIL_MASKS
] =
942 _3DSTATE_BACKFACE_STENCIL_MASKS
|
943 BFM_ENABLE_STENCIL_TEST_MASK
|
944 BFM_ENABLE_STENCIL_WRITE_MASK
|
945 (0xff << BFM_STENCIL_WRITE_MASK_SHIFT
) |
946 (0xff << BFM_STENCIL_TEST_MASK_SHIFT
);
947 i915
->state
.Ctx
[I915_CTXREG_BF_STENCIL_OPS
] =
948 _3DSTATE_BACKFACE_STENCIL_OPS
|
949 BFO_ENABLE_STENCIL_REF
|
950 BFO_ENABLE_STENCIL_FUNCS
|
951 BFO_ENABLE_STENCIL_TWO_SIDE
;
955 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
956 i915
->state
.Stipple
[I915_STPREG_ST0
] = _3DSTATE_STIPPLE
;
960 i915
->state
.Buffer
[I915_DESTREG_DV0
] = _3DSTATE_DST_BUF_VARS_CMD
;
963 i915
->state
.Buffer
[I915_DESTREG_SENABLE
] =
964 (_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
965 i915
->state
.Buffer
[I915_DESTREG_SR0
] = _3DSTATE_SCISSOR_RECT_0_CMD
;
966 i915
->state
.Buffer
[I915_DESTREG_SR1
] = 0;
967 i915
->state
.Buffer
[I915_DESTREG_SR2
] = 0;
970 i915
->state
.RasterRules
[I915_RASTER_RULES
] = _3DSTATE_RASTER_RULES_CMD
|
971 ENABLE_POINT_RASTER_RULE
|
972 OGL_POINT_RASTER_RULE
|
973 ENABLE_LINE_STRIP_PROVOKE_VRTX
|
974 ENABLE_TRI_FAN_PROVOKE_VRTX
|
975 LINE_STRIP_PROVOKE_VRTX(1) |
976 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D
| TEXKILL_4D
;
980 I915_STATECHANGE(i915
, I915_UPLOAD_DEFAULTS
);
981 i915
->state
.Default
[I915_DEFREG_C0
] = _3DSTATE_DEFAULT_DIFFUSE
;
982 i915
->state
.Default
[I915_DEFREG_C1
] = 0;
983 i915
->state
.Default
[I915_DEFREG_S0
] = _3DSTATE_DEFAULT_SPECULAR
;
984 i915
->state
.Default
[I915_DEFREG_S1
] = 0;
985 i915
->state
.Default
[I915_DEFREG_Z0
] = _3DSTATE_DEFAULT_Z
;
986 i915
->state
.Default
[I915_DEFREG_Z1
] = 0;
991 /* These will be emitted every at the head of every buffer, unless
992 * we get hardware contexts working.
994 i915
->state
.active
= (I915_UPLOAD_PROGRAM
|
995 I915_UPLOAD_STIPPLE
|
998 I915_UPLOAD_BUFFERS
|
999 I915_UPLOAD_INVARIENT
|
1000 I915_UPLOAD_RASTER_RULES
);
1004 i915_update_provoking_vertex(struct gl_context
* ctx
)
1006 struct i915_context
*i915
= I915_CONTEXT(ctx
);
1008 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
1009 i915
->state
.Ctx
[I915_CTXREG_LIS6
] &= ~(S6_TRISTRIP_PV_MASK
);
1011 I915_STATECHANGE(i915
, I915_UPLOAD_RASTER_RULES
);
1012 i915
->state
.RasterRules
[I915_RASTER_RULES
] &= ~(LINE_STRIP_PROVOKE_VRTX_MASK
|
1013 TRI_FAN_PROVOKE_VRTX_MASK
);
1016 if (ctx
->Light
.ProvokingVertex
== GL_LAST_VERTEX_CONVENTION
) {
1017 i915
->state
.RasterRules
[I915_RASTER_RULES
] |= (LINE_STRIP_PROVOKE_VRTX(1) |
1018 TRI_FAN_PROVOKE_VRTX(2));
1019 i915
->state
.Ctx
[I915_CTXREG_LIS6
] |= (2 << S6_TRISTRIP_PV_SHIFT
);
1021 i915
->state
.RasterRules
[I915_RASTER_RULES
] |= (LINE_STRIP_PROVOKE_VRTX(0) |
1022 TRI_FAN_PROVOKE_VRTX(1));
1023 i915
->state
.Ctx
[I915_CTXREG_LIS6
] |= (0 << S6_TRISTRIP_PV_SHIFT
);
1028 i915InitStateFunctions(struct dd_function_table
*functions
)
1030 functions
->AlphaFunc
= i915AlphaFunc
;
1031 functions
->BlendColor
= i915BlendColor
;
1032 functions
->BlendEquationSeparate
= i915BlendEquationSeparate
;
1033 functions
->BlendFuncSeparate
= i915BlendFuncSeparate
;
1034 functions
->ColorMask
= i915ColorMask
;
1035 functions
->CullFace
= i915CullFaceFrontFace
;
1036 functions
->DepthFunc
= i915DepthFunc
;
1037 functions
->DepthMask
= i915DepthMask
;
1038 functions
->Enable
= i915Enable
;
1039 functions
->Fogfv
= i915Fogfv
;
1040 functions
->FrontFace
= i915CullFaceFrontFace
;
1041 functions
->LightModelfv
= i915LightModelfv
;
1042 functions
->LineWidth
= i915LineWidth
;
1043 functions
->LogicOpcode
= i915LogicOp
;
1044 functions
->PointSize
= i915PointSize
;
1045 functions
->PointParameterfv
= i915PointParameterfv
;
1046 functions
->PolygonStipple
= i915PolygonStipple
;
1047 functions
->Scissor
= i915Scissor
;
1048 functions
->ShadeModel
= i915ShadeModel
;
1049 functions
->StencilFuncSeparate
= i915StencilFuncSeparate
;
1050 functions
->StencilMaskSeparate
= i915StencilMaskSeparate
;
1051 functions
->StencilOpSeparate
= i915StencilOpSeparate
;
1052 functions
->DepthRange
= i915DepthRange
;
1053 functions
->Viewport
= i915Viewport
;
1058 i915InitState(struct i915_context
*i915
)
1060 struct gl_context
*ctx
= &i915
->intel
.ctx
;
1062 i915_init_packets(i915
);
1064 _mesa_init_driver_state(ctx
);