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[mesa.git] / src / mesa / drivers / dri / i915 / i915_state.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "main/glheader.h"
30 #include "main/context.h"
31 #include "main/macros.h"
32 #include "main/enums.h"
33 #include "main/dd.h"
34 #include "main/state.h"
35 #include "tnl/tnl.h"
36 #include "tnl/t_context.h"
37
38 #include "texmem.h"
39
40 #include "drivers/common/driverfuncs.h"
41
42 #include "intel_fbo.h"
43 #include "intel_screen.h"
44 #include "intel_batchbuffer.h"
45 #include "intel_buffers.h"
46
47 #include "i915_context.h"
48 #include "i915_reg.h"
49
50 #define FILE_DEBUG_FLAG DEBUG_STATE
51
52 void
53 i915_update_stencil(struct gl_context * ctx)
54 {
55 struct i915_context *i915 = I915_CONTEXT(ctx);
56 GLuint front_ref, front_writemask, front_mask;
57 GLenum front_func, front_fail, front_pass_z_fail, front_pass_z_pass;
58 GLuint back_ref, back_writemask, back_mask;
59 GLenum back_func, back_fail, back_pass_z_fail, back_pass_z_pass;
60 GLuint dirty = 0;
61
62 /* The 915 considers CW to be "front" for two-sided stencil, so choose
63 * appropriately.
64 */
65 /* _NEW_POLYGON | _NEW_STENCIL */
66 if (ctx->Polygon.FrontFace == GL_CW) {
67 front_ref = ctx->Stencil.Ref[0];
68 front_mask = ctx->Stencil.ValueMask[0];
69 front_writemask = ctx->Stencil.WriteMask[0];
70 front_func = ctx->Stencil.Function[0];
71 front_fail = ctx->Stencil.FailFunc[0];
72 front_pass_z_fail = ctx->Stencil.ZFailFunc[0];
73 front_pass_z_pass = ctx->Stencil.ZPassFunc[0];
74 back_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
75 back_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
76 back_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
77 back_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
78 back_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
79 back_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
80 back_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
81 } else {
82 front_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
83 front_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
84 front_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
85 front_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
86 front_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
87 front_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
88 front_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
89 back_ref = ctx->Stencil.Ref[0];
90 back_mask = ctx->Stencil.ValueMask[0];
91 back_writemask = ctx->Stencil.WriteMask[0];
92 back_func = ctx->Stencil.Function[0];
93 back_fail = ctx->Stencil.FailFunc[0];
94 back_pass_z_fail = ctx->Stencil.ZFailFunc[0];
95 back_pass_z_pass = ctx->Stencil.ZPassFunc[0];
96 }
97 #define set_ctx_bits(reg, mask, set) do{ \
98 GLuint dw = i915->state.Ctx[reg]; \
99 dw &= ~(mask); \
100 dw |= (set); \
101 dirty |= dw != i915->state.Ctx[reg]; \
102 i915->state.Ctx[reg] = dw; \
103 } while(0)
104
105 /* Set front state. */
106 set_ctx_bits(I915_CTXREG_STATE4,
107 MODE4_ENABLE_STENCIL_TEST_MASK |
108 MODE4_ENABLE_STENCIL_WRITE_MASK,
109 ENABLE_STENCIL_TEST_MASK |
110 ENABLE_STENCIL_WRITE_MASK |
111 STENCIL_TEST_MASK(front_mask) |
112 STENCIL_WRITE_MASK(front_writemask));
113
114 set_ctx_bits(I915_CTXREG_LIS5,
115 S5_STENCIL_REF_MASK |
116 S5_STENCIL_TEST_FUNC_MASK |
117 S5_STENCIL_FAIL_MASK |
118 S5_STENCIL_PASS_Z_FAIL_MASK |
119 S5_STENCIL_PASS_Z_PASS_MASK,
120 (front_ref << S5_STENCIL_REF_SHIFT) |
121 (intel_translate_compare_func(front_func) << S5_STENCIL_TEST_FUNC_SHIFT) |
122 (intel_translate_stencil_op(front_fail) << S5_STENCIL_FAIL_SHIFT) |
123 (intel_translate_stencil_op(front_pass_z_fail) <<
124 S5_STENCIL_PASS_Z_FAIL_SHIFT) |
125 (intel_translate_stencil_op(front_pass_z_pass) <<
126 S5_STENCIL_PASS_Z_PASS_SHIFT));
127
128 /* Set back state if different from front. */
129 if (ctx->Stencil._TestTwoSide) {
130 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS,
131 BFO_STENCIL_REF_MASK |
132 BFO_STENCIL_TEST_MASK |
133 BFO_STENCIL_FAIL_MASK |
134 BFO_STENCIL_PASS_Z_FAIL_MASK |
135 BFO_STENCIL_PASS_Z_PASS_MASK,
136 BFO_STENCIL_TWO_SIDE |
137 (back_ref << BFO_STENCIL_REF_SHIFT) |
138 (intel_translate_compare_func(back_func) << BFO_STENCIL_TEST_SHIFT) |
139 (intel_translate_stencil_op(back_fail) << BFO_STENCIL_FAIL_SHIFT) |
140 (intel_translate_stencil_op(back_pass_z_fail) <<
141 BFO_STENCIL_PASS_Z_FAIL_SHIFT) |
142 (intel_translate_stencil_op(back_pass_z_pass) <<
143 BFO_STENCIL_PASS_Z_PASS_SHIFT));
144
145 set_ctx_bits(I915_CTXREG_BF_STENCIL_MASKS,
146 BFM_STENCIL_TEST_MASK_MASK |
147 BFM_STENCIL_WRITE_MASK_MASK,
148 BFM_STENCIL_TEST_MASK(back_mask) |
149 BFM_STENCIL_WRITE_MASK(back_writemask));
150 } else {
151 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS,
152 BFO_STENCIL_TWO_SIDE, 0);
153 }
154
155 #undef set_ctx_bits
156
157 if (dirty)
158 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
159 }
160
161 static void
162 i915StencilFuncSeparate(struct gl_context * ctx, GLenum face, GLenum func, GLint ref,
163 GLuint mask)
164 {
165 }
166
167 static void
168 i915StencilMaskSeparate(struct gl_context * ctx, GLenum face, GLuint mask)
169 {
170 }
171
172 static void
173 i915StencilOpSeparate(struct gl_context * ctx, GLenum face, GLenum fail, GLenum zfail,
174 GLenum zpass)
175 {
176 }
177
178 static void
179 i915AlphaFunc(struct gl_context * ctx, GLenum func, GLfloat ref)
180 {
181 struct i915_context *i915 = I915_CONTEXT(ctx);
182 int test = intel_translate_compare_func(func);
183 GLubyte refByte;
184 GLuint dw;
185
186 UNCLAMPED_FLOAT_TO_UBYTE(refByte, ref);
187
188 dw = i915->state.Ctx[I915_CTXREG_LIS6];
189 dw &= ~(S6_ALPHA_TEST_FUNC_MASK | S6_ALPHA_REF_MASK);
190 dw |= ((test << S6_ALPHA_TEST_FUNC_SHIFT) |
191 (((GLuint) refByte) << S6_ALPHA_REF_SHIFT));
192 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
193 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
194 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
195 }
196 }
197
198 /* This function makes sure that the proper enables are
199 * set for LogicOp, Independant Alpha Blend, and Blending.
200 * It needs to be called from numerous places where we
201 * could change the LogicOp or Independant Alpha Blend without subsequent
202 * calls to glEnable.
203 */
204 static void
205 i915EvalLogicOpBlendState(struct gl_context * ctx)
206 {
207 struct i915_context *i915 = I915_CONTEXT(ctx);
208 GLuint dw0, dw1;
209
210 dw0 = i915->state.Ctx[I915_CTXREG_LIS5];
211 dw1 = i915->state.Ctx[I915_CTXREG_LIS6];
212
213 if (_mesa_rgba_logicop_enabled(ctx)) {
214 dw0 |= S5_LOGICOP_ENABLE;
215 dw1 &= ~S6_CBUF_BLEND_ENABLE;
216 }
217 else {
218 dw0 &= ~S5_LOGICOP_ENABLE;
219
220 if (ctx->Color.BlendEnabled) {
221 dw1 |= S6_CBUF_BLEND_ENABLE;
222 }
223 else {
224 dw1 &= ~S6_CBUF_BLEND_ENABLE;
225 }
226 }
227 if (dw0 != i915->state.Ctx[I915_CTXREG_LIS5] ||
228 dw1 != i915->state.Ctx[I915_CTXREG_LIS6]) {
229 i915->state.Ctx[I915_CTXREG_LIS5] = dw0;
230 i915->state.Ctx[I915_CTXREG_LIS6] = dw1;
231
232 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
233 }
234 }
235
236 static void
237 i915BlendColor(struct gl_context * ctx, const GLfloat color[4])
238 {
239 struct i915_context *i915 = I915_CONTEXT(ctx);
240 GLubyte r, g, b, a;
241 GLuint dw;
242
243 DBG("%s\n", __FUNCTION__);
244
245 UNCLAMPED_FLOAT_TO_UBYTE(r, color[RCOMP]);
246 UNCLAMPED_FLOAT_TO_UBYTE(g, color[GCOMP]);
247 UNCLAMPED_FLOAT_TO_UBYTE(b, color[BCOMP]);
248 UNCLAMPED_FLOAT_TO_UBYTE(a, color[ACOMP]);
249
250 dw = (a << 24) | (r << 16) | (g << 8) | b;
251 if (dw != i915->state.Blend[I915_BLENDREG_BLENDCOLOR1]) {
252 i915->state.Blend[I915_BLENDREG_BLENDCOLOR1] = dw;
253 I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
254 }
255 }
256
257
258 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
259 #define SRC_BLND_FACT(f) ((f)<<S6_CBUF_SRC_BLEND_FACT_SHIFT)
260 #define DST_ABLND_FACT(f) ((f)<<IAB_DST_FACTOR_SHIFT)
261 #define SRC_ABLND_FACT(f) ((f)<<IAB_SRC_FACTOR_SHIFT)
262
263
264
265 static GLuint
266 translate_blend_equation(GLenum mode)
267 {
268 switch (mode) {
269 case GL_FUNC_ADD:
270 return BLENDFUNC_ADD;
271 case GL_MIN:
272 return BLENDFUNC_MIN;
273 case GL_MAX:
274 return BLENDFUNC_MAX;
275 case GL_FUNC_SUBTRACT:
276 return BLENDFUNC_SUBTRACT;
277 case GL_FUNC_REVERSE_SUBTRACT:
278 return BLENDFUNC_REVERSE_SUBTRACT;
279 default:
280 return 0;
281 }
282 }
283
284 static void
285 i915UpdateBlendState(struct gl_context * ctx)
286 {
287 struct i915_context *i915 = I915_CONTEXT(ctx);
288 GLuint iab = (i915->state.Blend[I915_BLENDREG_IAB] &
289 ~(IAB_SRC_FACTOR_MASK |
290 IAB_DST_FACTOR_MASK |
291 (BLENDFUNC_MASK << IAB_FUNC_SHIFT) | IAB_ENABLE));
292
293 GLuint lis6 = (i915->state.Ctx[I915_CTXREG_LIS6] &
294 ~(S6_CBUF_SRC_BLEND_FACT_MASK |
295 S6_CBUF_DST_BLEND_FACT_MASK | S6_CBUF_BLEND_FUNC_MASK));
296
297 GLuint eqRGB = ctx->Color.Blend[0].EquationRGB;
298 GLuint eqA = ctx->Color.Blend[0].EquationA;
299 GLuint srcRGB = ctx->Color.Blend[0].SrcRGB;
300 GLuint dstRGB = ctx->Color.Blend[0].DstRGB;
301 GLuint srcA = ctx->Color.Blend[0].SrcA;
302 GLuint dstA = ctx->Color.Blend[0].DstA;
303
304 if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
305 srcRGB = dstRGB = GL_ONE;
306 }
307
308 if (eqA == GL_MIN || eqA == GL_MAX) {
309 srcA = dstA = GL_ONE;
310 }
311
312 lis6 |= SRC_BLND_FACT(intel_translate_blend_factor(srcRGB));
313 lis6 |= DST_BLND_FACT(intel_translate_blend_factor(dstRGB));
314 lis6 |= translate_blend_equation(eqRGB) << S6_CBUF_BLEND_FUNC_SHIFT;
315
316 iab |= SRC_ABLND_FACT(intel_translate_blend_factor(srcA));
317 iab |= DST_ABLND_FACT(intel_translate_blend_factor(dstA));
318 iab |= translate_blend_equation(eqA) << IAB_FUNC_SHIFT;
319
320 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB)
321 iab |= IAB_ENABLE;
322
323 if (iab != i915->state.Blend[I915_BLENDREG_IAB]) {
324 i915->state.Blend[I915_BLENDREG_IAB] = iab;
325 I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
326 }
327 if (lis6 != i915->state.Ctx[I915_CTXREG_LIS6]) {
328 i915->state.Ctx[I915_CTXREG_LIS6] = lis6;
329 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
330 }
331
332 /* This will catch a logicop blend equation */
333 i915EvalLogicOpBlendState(ctx);
334 }
335
336
337 static void
338 i915BlendFuncSeparate(struct gl_context * ctx, GLenum srcRGB,
339 GLenum dstRGB, GLenum srcA, GLenum dstA)
340 {
341 i915UpdateBlendState(ctx);
342 }
343
344
345 static void
346 i915BlendEquationSeparate(struct gl_context * ctx, GLenum eqRGB, GLenum eqA)
347 {
348 i915UpdateBlendState(ctx);
349 }
350
351
352 static void
353 i915DepthFunc(struct gl_context * ctx, GLenum func)
354 {
355 struct i915_context *i915 = I915_CONTEXT(ctx);
356 int test = intel_translate_compare_func(func);
357 GLuint dw;
358
359 DBG("%s\n", __FUNCTION__);
360
361 dw = i915->state.Ctx[I915_CTXREG_LIS6];
362 dw &= ~S6_DEPTH_TEST_FUNC_MASK;
363 dw |= test << S6_DEPTH_TEST_FUNC_SHIFT;
364 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
365 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
366 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
367 }
368 }
369
370 static void
371 i915DepthMask(struct gl_context * ctx, GLboolean flag)
372 {
373 struct i915_context *i915 = I915_CONTEXT(ctx);
374 GLuint dw;
375
376 DBG("%s flag (%d)\n", __FUNCTION__, flag);
377
378 dw = i915->state.Ctx[I915_CTXREG_LIS6];
379 if (flag && ctx->Depth.Test)
380 dw |= S6_DEPTH_WRITE_ENABLE;
381 else
382 dw &= ~S6_DEPTH_WRITE_ENABLE;
383 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
384 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
385 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
386 }
387 }
388
389
390
391 /**
392 * Update the viewport transformation matrix. Depends on:
393 * - viewport pos/size
394 * - depthrange
395 * - window pos/size or FBO size
396 */
397 void
398 intelCalcViewport(struct gl_context * ctx)
399 {
400 struct intel_context *intel = intel_context(ctx);
401 const GLfloat *v = ctx->Viewport._WindowMap.m;
402 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
403 GLfloat *m = intel->ViewportMatrix.m;
404 GLfloat yScale, yBias;
405
406 if (ctx->DrawBuffer->Name) {
407 /* User created FBO */
408 /* y=0=bottom */
409 yScale = 1.0;
410 yBias = 0.0;
411 }
412 else {
413 /* window buffer, y=0=top */
414 yScale = -1.0;
415 yBias = ctx->DrawBuffer->Height;
416 }
417
418 m[MAT_SX] = v[MAT_SX];
419 m[MAT_TX] = v[MAT_TX];
420
421 m[MAT_SY] = v[MAT_SY] * yScale;
422 m[MAT_TY] = v[MAT_TY] * yScale + yBias;
423
424 m[MAT_SZ] = v[MAT_SZ] * depthScale;
425 m[MAT_TZ] = v[MAT_TZ] * depthScale;
426 }
427
428
429 /** Called from ctx->Driver.Viewport() */
430 static void
431 i915Viewport(struct gl_context * ctx,
432 GLint x, GLint y, GLsizei width, GLsizei height)
433 {
434 intelCalcViewport(ctx);
435 }
436
437
438 /** Called from ctx->Driver.DepthRange() */
439 static void
440 i915DepthRange(struct gl_context * ctx, GLclampd nearval, GLclampd farval)
441 {
442 intelCalcViewport(ctx);
443 }
444
445
446 /* =============================================================
447 * Polygon stipple
448 *
449 * The i915 supports a 4x4 stipple natively, GL wants 32x32.
450 * Fortunately stipple is usually a repeating pattern.
451 */
452 static void
453 i915PolygonStipple(struct gl_context * ctx, const GLubyte * mask)
454 {
455 struct i915_context *i915 = I915_CONTEXT(ctx);
456 const GLubyte *m;
457 GLubyte p[4];
458 int i, j, k;
459 int active = (ctx->Polygon.StippleFlag &&
460 i915->intel.reduced_primitive == GL_TRIANGLES);
461 GLuint newMask;
462
463 if (active) {
464 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
465 i915->state.Stipple[I915_STPREG_ST1] &= ~ST1_ENABLE;
466 }
467
468 /* Use the already unpacked stipple data from the context rather than the
469 * uninterpreted mask passed in.
470 */
471 mask = (const GLubyte *)ctx->PolygonStipple;
472 m = mask;
473
474 p[0] = mask[12] & 0xf;
475 p[0] |= p[0] << 4;
476 p[1] = mask[8] & 0xf;
477 p[1] |= p[1] << 4;
478 p[2] = mask[4] & 0xf;
479 p[2] |= p[2] << 4;
480 p[3] = mask[0] & 0xf;
481 p[3] |= p[3] << 4;
482
483 for (k = 0; k < 8; k++)
484 for (j = 3; j >= 0; j--)
485 for (i = 0; i < 4; i++, m++)
486 if (*m != p[j]) {
487 i915->intel.hw_stipple = 0;
488 return;
489 }
490
491 newMask = (((p[0] & 0xf) << 0) |
492 ((p[1] & 0xf) << 4) |
493 ((p[2] & 0xf) << 8) | ((p[3] & 0xf) << 12));
494
495
496 if (newMask == 0xffff || newMask == 0x0) {
497 /* this is needed to make conform pass */
498 i915->intel.hw_stipple = 0;
499 return;
500 }
501
502 i915->state.Stipple[I915_STPREG_ST1] &= ~0xffff;
503 i915->state.Stipple[I915_STPREG_ST1] |= newMask;
504 i915->intel.hw_stipple = 1;
505
506 if (active)
507 i915->state.Stipple[I915_STPREG_ST1] |= ST1_ENABLE;
508 }
509
510
511 /* =============================================================
512 * Hardware clipping
513 */
514 static void
515 i915Scissor(struct gl_context * ctx, GLint x, GLint y, GLsizei w, GLsizei h)
516 {
517 struct i915_context *i915 = I915_CONTEXT(ctx);
518 int x1, y1, x2, y2;
519
520 if (!ctx->DrawBuffer)
521 return;
522
523 DBG("%s %d,%d %dx%d\n", __FUNCTION__, x, y, w, h);
524
525 if (ctx->DrawBuffer->Name == 0) {
526 x1 = x;
527 y1 = ctx->DrawBuffer->Height - (y + h);
528 x2 = x + w - 1;
529 y2 = y1 + h - 1;
530 DBG("%s %d..%d,%d..%d (inverted)\n", __FUNCTION__, x1, x2, y1, y2);
531 }
532 else {
533 /* FBO - not inverted
534 */
535 x1 = x;
536 y1 = y;
537 x2 = x + w - 1;
538 y2 = y + h - 1;
539 DBG("%s %d..%d,%d..%d (not inverted)\n", __FUNCTION__, x1, x2, y1, y2);
540 }
541
542 x1 = CLAMP(x1, 0, ctx->DrawBuffer->Width - 1);
543 y1 = CLAMP(y1, 0, ctx->DrawBuffer->Height - 1);
544 x2 = CLAMP(x2, 0, ctx->DrawBuffer->Width - 1);
545 y2 = CLAMP(y2, 0, ctx->DrawBuffer->Height - 1);
546
547 DBG("%s %d..%d,%d..%d (clamped)\n", __FUNCTION__, x1, x2, y1, y2);
548
549 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
550 i915->state.Buffer[I915_DESTREG_SR1] = (y1 << 16) | (x1 & 0xffff);
551 i915->state.Buffer[I915_DESTREG_SR2] = (y2 << 16) | (x2 & 0xffff);
552 }
553
554 static void
555 i915LogicOp(struct gl_context * ctx, GLenum opcode)
556 {
557 struct i915_context *i915 = I915_CONTEXT(ctx);
558 int tmp = intel_translate_logic_op(opcode);
559
560 DBG("%s\n", __FUNCTION__);
561
562 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
563 i915->state.Ctx[I915_CTXREG_STATE4] &= ~LOGICOP_MASK;
564 i915->state.Ctx[I915_CTXREG_STATE4] |= LOGIC_OP_FUNC(tmp);
565 }
566
567
568
569 static void
570 i915CullFaceFrontFace(struct gl_context * ctx, GLenum unused)
571 {
572 struct i915_context *i915 = I915_CONTEXT(ctx);
573 GLuint mode, dw;
574
575 DBG("%s %d\n", __FUNCTION__,
576 ctx->DrawBuffer ? ctx->DrawBuffer->Name : 0);
577
578 if (!ctx->Polygon.CullFlag) {
579 mode = S4_CULLMODE_NONE;
580 }
581 else if (ctx->Polygon.CullFaceMode != GL_FRONT_AND_BACK) {
582 mode = S4_CULLMODE_CW;
583
584 if (ctx->DrawBuffer && ctx->DrawBuffer->Name != 0)
585 mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
586 if (ctx->Polygon.CullFaceMode == GL_FRONT)
587 mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
588 if (ctx->Polygon.FrontFace != GL_CCW)
589 mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
590 }
591 else {
592 mode = S4_CULLMODE_BOTH;
593 }
594
595 dw = i915->state.Ctx[I915_CTXREG_LIS4];
596 dw &= ~S4_CULLMODE_MASK;
597 dw |= mode;
598 if (dw != i915->state.Ctx[I915_CTXREG_LIS4]) {
599 i915->state.Ctx[I915_CTXREG_LIS4] = dw;
600 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
601 }
602 }
603
604 static void
605 i915LineWidth(struct gl_context * ctx, GLfloat widthf)
606 {
607 struct i915_context *i915 = I915_CONTEXT(ctx);
608 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_LINE_WIDTH_MASK;
609 int width;
610
611 DBG("%s\n", __FUNCTION__);
612
613 width = (int) (widthf * 2);
614 width = CLAMP(width, 1, 0xf);
615 lis4 |= width << S4_LINE_WIDTH_SHIFT;
616
617 if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
618 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
619 i915->state.Ctx[I915_CTXREG_LIS4] = lis4;
620 }
621 }
622
623 static void
624 i915PointSize(struct gl_context * ctx, GLfloat size)
625 {
626 struct i915_context *i915 = I915_CONTEXT(ctx);
627 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_POINT_WIDTH_MASK;
628 GLint point_size = (int) round(size);
629
630 DBG("%s\n", __FUNCTION__);
631
632 point_size = CLAMP(point_size, 1, 255);
633 lis4 |= point_size << S4_POINT_WIDTH_SHIFT;
634
635 if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
636 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
637 i915->state.Ctx[I915_CTXREG_LIS4] = lis4;
638 }
639 }
640
641
642 static void
643 i915PointParameterfv(struct gl_context * ctx, GLenum pname, const GLfloat *params)
644 {
645 struct i915_context *i915 = I915_CONTEXT(ctx);
646
647 switch (pname) {
648 case GL_POINT_SPRITE_COORD_ORIGIN:
649 /* This could be supported, but it would require modifying the fragment
650 * program to invert the y component of the texture coordinate by
651 * inserting a 'SUB tc.y, {1.0}.xxxx, tc' instruction.
652 */
653 FALLBACK(&i915->intel, I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN,
654 (params[0] != GL_UPPER_LEFT));
655 break;
656 }
657 }
658
659
660 /* =============================================================
661 * Color masks
662 */
663
664 static void
665 i915ColorMask(struct gl_context * ctx,
666 GLboolean r, GLboolean g, GLboolean b, GLboolean a)
667 {
668 struct i915_context *i915 = I915_CONTEXT(ctx);
669 GLuint tmp = i915->state.Ctx[I915_CTXREG_LIS5] & ~S5_WRITEDISABLE_MASK;
670
671 DBG("%s r(%d) g(%d) b(%d) a(%d)\n", __FUNCTION__, r, g, b,
672 a);
673
674 if (!r)
675 tmp |= S5_WRITEDISABLE_RED;
676 if (!g)
677 tmp |= S5_WRITEDISABLE_GREEN;
678 if (!b)
679 tmp |= S5_WRITEDISABLE_BLUE;
680 if (!a)
681 tmp |= S5_WRITEDISABLE_ALPHA;
682
683 if (tmp != i915->state.Ctx[I915_CTXREG_LIS5]) {
684 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
685 i915->state.Ctx[I915_CTXREG_LIS5] = tmp;
686 }
687 }
688
689 static void
690 update_specular(struct gl_context * ctx)
691 {
692 /* A hack to trigger the rebuild of the fragment program.
693 */
694 intel_context(ctx)->NewGLState |= _NEW_TEXTURE;
695 }
696
697 static void
698 i915LightModelfv(struct gl_context * ctx, GLenum pname, const GLfloat * param)
699 {
700 DBG("%s\n", __FUNCTION__);
701
702 if (pname == GL_LIGHT_MODEL_COLOR_CONTROL) {
703 update_specular(ctx);
704 }
705 }
706
707 static void
708 i915ShadeModel(struct gl_context * ctx, GLenum mode)
709 {
710 struct i915_context *i915 = I915_CONTEXT(ctx);
711 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
712
713 if (mode == GL_SMOOTH) {
714 i915->state.Ctx[I915_CTXREG_LIS4] &= ~(S4_FLATSHADE_ALPHA |
715 S4_FLATSHADE_COLOR |
716 S4_FLATSHADE_SPECULAR);
717 }
718 else {
719 i915->state.Ctx[I915_CTXREG_LIS4] |= (S4_FLATSHADE_ALPHA |
720 S4_FLATSHADE_COLOR |
721 S4_FLATSHADE_SPECULAR);
722 }
723 }
724
725 /* =============================================================
726 * Fog
727 */
728 void
729 i915_update_fog(struct gl_context * ctx)
730 {
731 struct i915_context *i915 = I915_CONTEXT(ctx);
732 GLuint dw;
733
734 assert(ctx->FragmentProgram._Current);
735
736 i915->vertex_fog = I915_FOG_NONE;
737
738 I915_ACTIVESTATE(i915, I915_UPLOAD_FOG, 0);
739 dw = i915->state.Ctx[I915_CTXREG_LIS5] & ~S5_FOG_ENABLE;
740
741 if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
742 i915->state.Ctx[I915_CTXREG_LIS5] = dw;
743 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
744 }
745
746 /* Always enable pixel fog. Vertex fog using fog coord will conflict
747 * with fog code appended onto fragment program.
748 */
749 _tnl_allow_vertex_fog( ctx, 0 );
750 _tnl_allow_pixel_fog( ctx, 1 );
751 }
752
753 static void
754 i915Fogfv(struct gl_context * ctx, GLenum pname, const GLfloat * param)
755 {
756 struct i915_context *i915 = I915_CONTEXT(ctx);
757
758 switch (pname) {
759 case GL_FOG_COORDINATE_SOURCE_EXT:
760 case GL_FOG_MODE:
761 case GL_FOG_START:
762 case GL_FOG_END:
763 break;
764
765 case GL_FOG_DENSITY:
766 I915_STATECHANGE(i915, I915_UPLOAD_FOG);
767
768 if (i915->state.Fog[I915_FOGREG_MODE1] & FMC1_FOGINDEX_Z) {
769 i915->state.Fog[I915_FOGREG_MODE3] =
770 (GLuint) (ctx->Fog.Density * FMC3_D_ONE);
771 }
772 else {
773 fi_type fi;
774 fi.f = ctx->Fog.Density;
775 i915->state.Fog[I915_FOGREG_MODE3] = fi.i;
776 }
777 break;
778
779 case GL_FOG_COLOR:
780 I915_STATECHANGE(i915, I915_UPLOAD_FOG);
781 i915->state.Fog[I915_FOGREG_COLOR] =
782 (_3DSTATE_FOG_COLOR_CMD |
783 ((GLubyte) (ctx->Fog.Color[0] * 255.0F) << 16) |
784 ((GLubyte) (ctx->Fog.Color[1] * 255.0F) << 8) |
785 ((GLubyte) (ctx->Fog.Color[2] * 255.0F) << 0));
786 break;
787
788 default:
789 break;
790 }
791 }
792
793 static void
794 i915Hint(struct gl_context * ctx, GLenum target, GLenum state)
795 {
796 switch (target) {
797 case GL_FOG_HINT:
798 break;
799 default:
800 break;
801 }
802 }
803
804 /* =============================================================
805 */
806
807 static void
808 i915Enable(struct gl_context * ctx, GLenum cap, GLboolean state)
809 {
810 struct i915_context *i915 = I915_CONTEXT(ctx);
811 GLuint dw;
812
813 switch (cap) {
814 case GL_TEXTURE_2D:
815 break;
816
817 case GL_LIGHTING:
818 case GL_COLOR_SUM:
819 update_specular(ctx);
820 break;
821
822 case GL_ALPHA_TEST:
823 dw = i915->state.Ctx[I915_CTXREG_LIS6];
824 if (state)
825 dw |= S6_ALPHA_TEST_ENABLE;
826 else
827 dw &= ~S6_ALPHA_TEST_ENABLE;
828 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
829 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
830 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
831 }
832 break;
833
834 case GL_BLEND:
835 i915EvalLogicOpBlendState(ctx);
836 break;
837
838 case GL_COLOR_LOGIC_OP:
839 i915EvalLogicOpBlendState(ctx);
840
841 /* Logicop doesn't seem to work at 16bpp:
842 */
843 if (ctx->Visual.rgbBits == 16)
844 FALLBACK(&i915->intel, I915_FALLBACK_LOGICOP, state);
845 break;
846
847 case GL_FRAGMENT_PROGRAM_ARB:
848 break;
849
850 case GL_DITHER:
851 dw = i915->state.Ctx[I915_CTXREG_LIS5];
852 if (state)
853 dw |= S5_COLOR_DITHER_ENABLE;
854 else
855 dw &= ~S5_COLOR_DITHER_ENABLE;
856 if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
857 i915->state.Ctx[I915_CTXREG_LIS5] = dw;
858 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
859 }
860 break;
861
862 case GL_DEPTH_TEST:
863 dw = i915->state.Ctx[I915_CTXREG_LIS6];
864 if (state)
865 dw |= S6_DEPTH_TEST_ENABLE;
866 else
867 dw &= ~S6_DEPTH_TEST_ENABLE;
868 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
869 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
870 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
871 }
872
873 i915DepthMask(ctx, ctx->Depth.Mask);
874 break;
875
876 case GL_SCISSOR_TEST:
877 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
878 if (state)
879 i915->state.Buffer[I915_DESTREG_SENABLE] =
880 (_3DSTATE_SCISSOR_ENABLE_CMD | ENABLE_SCISSOR_RECT);
881 else
882 i915->state.Buffer[I915_DESTREG_SENABLE] =
883 (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
884 break;
885
886 case GL_LINE_SMOOTH:
887 dw = i915->state.Ctx[I915_CTXREG_LIS4];
888 if (state)
889 dw |= S4_LINE_ANTIALIAS_ENABLE;
890 else
891 dw &= ~S4_LINE_ANTIALIAS_ENABLE;
892 if (dw != i915->state.Ctx[I915_CTXREG_LIS4]) {
893 i915->state.Ctx[I915_CTXREG_LIS4] = dw;
894 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
895 }
896 break;
897
898 case GL_FOG:
899 break;
900
901 case GL_CULL_FACE:
902 i915CullFaceFrontFace(ctx, 0);
903 break;
904
905 case GL_STENCIL_TEST:
906 {
907 GLboolean hw_stencil = GL_FALSE;
908 if (ctx->DrawBuffer) {
909 struct intel_renderbuffer *irbStencil
910 = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
911 hw_stencil = (irbStencil && irbStencil->region);
912 }
913 if (hw_stencil) {
914 dw = i915->state.Ctx[I915_CTXREG_LIS5];
915 if (state)
916 dw |= (S5_STENCIL_TEST_ENABLE | S5_STENCIL_WRITE_ENABLE);
917 else
918 dw &= ~(S5_STENCIL_TEST_ENABLE | S5_STENCIL_WRITE_ENABLE);
919 if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
920 i915->state.Ctx[I915_CTXREG_LIS5] = dw;
921 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
922 }
923 }
924 else {
925 FALLBACK(&i915->intel, I915_FALLBACK_STENCIL, state);
926 }
927 }
928 break;
929
930 case GL_POLYGON_STIPPLE:
931 /* The stipple command worked on my 855GM box, but not my 845G.
932 * I'll do more testing later to find out exactly which hardware
933 * supports it. Disabled for now.
934 */
935 if (i915->intel.hw_stipple &&
936 i915->intel.reduced_primitive == GL_TRIANGLES) {
937 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
938 if (state)
939 i915->state.Stipple[I915_STPREG_ST1] |= ST1_ENABLE;
940 else
941 i915->state.Stipple[I915_STPREG_ST1] &= ~ST1_ENABLE;
942 }
943 break;
944
945 case GL_POLYGON_SMOOTH:
946 break;
947
948 case GL_POINT_SPRITE:
949 /* This state change is handled in i915_reduced_primitive_state because
950 * the hardware bit should only be set when rendering points.
951 */
952 dw = i915->state.Ctx[I915_CTXREG_LIS4];
953 if (state)
954 dw |= S4_SPRITE_POINT_ENABLE;
955 else
956 dw &= ~S4_SPRITE_POINT_ENABLE;
957 if (dw != i915->state.Ctx[I915_CTXREG_LIS4]) {
958 i915->state.Ctx[I915_CTXREG_LIS4] = dw;
959 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
960 }
961 break;
962
963 case GL_POINT_SMOOTH:
964 break;
965
966 default:
967 ;
968 }
969 }
970
971
972 static void
973 i915_init_packets(struct i915_context *i915)
974 {
975 /* Zero all state */
976 memset(&i915->state, 0, sizeof(i915->state));
977
978
979 {
980 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
981 I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
982 /* Probably don't want to upload all this stuff every time one
983 * piece changes.
984 */
985 i915->state.Ctx[I915_CTXREG_LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
986 I1_LOAD_S(2) |
987 I1_LOAD_S(4) |
988 I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
989 i915->state.Ctx[I915_CTXREG_LIS2] = 0;
990 i915->state.Ctx[I915_CTXREG_LIS4] = 0;
991 i915->state.Ctx[I915_CTXREG_LIS5] = 0;
992
993 if (i915->intel.ctx.Visual.rgbBits == 16)
994 i915->state.Ctx[I915_CTXREG_LIS5] |= S5_COLOR_DITHER_ENABLE;
995
996
997 i915->state.Ctx[I915_CTXREG_LIS6] = (S6_COLOR_WRITE_ENABLE |
998 (2 << S6_TRISTRIP_PV_SHIFT));
999
1000 i915->state.Ctx[I915_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
1001 ENABLE_LOGIC_OP_FUNC |
1002 LOGIC_OP_FUNC(LOGICOP_COPY) |
1003 ENABLE_STENCIL_TEST_MASK |
1004 STENCIL_TEST_MASK(0xff) |
1005 ENABLE_STENCIL_WRITE_MASK |
1006 STENCIL_WRITE_MASK(0xff));
1007
1008 i915->state.Blend[I915_BLENDREG_IAB] =
1009 (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE |
1010 IAB_MODIFY_FUNC | IAB_MODIFY_SRC_FACTOR | IAB_MODIFY_DST_FACTOR);
1011
1012 i915->state.Blend[I915_BLENDREG_BLENDCOLOR0] =
1013 _3DSTATE_CONST_BLEND_COLOR_CMD;
1014 i915->state.Blend[I915_BLENDREG_BLENDCOLOR1] = 0;
1015
1016 i915->state.Ctx[I915_CTXREG_BF_STENCIL_MASKS] =
1017 _3DSTATE_BACKFACE_STENCIL_MASKS |
1018 BFM_ENABLE_STENCIL_TEST_MASK |
1019 BFM_ENABLE_STENCIL_WRITE_MASK |
1020 (0xff << BFM_STENCIL_WRITE_MASK_SHIFT) |
1021 (0xff << BFM_STENCIL_TEST_MASK_SHIFT);
1022 i915->state.Ctx[I915_CTXREG_BF_STENCIL_OPS] =
1023 _3DSTATE_BACKFACE_STENCIL_OPS |
1024 BFO_ENABLE_STENCIL_REF |
1025 BFO_ENABLE_STENCIL_FUNCS |
1026 BFO_ENABLE_STENCIL_TWO_SIDE;
1027 }
1028
1029 {
1030 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
1031 i915->state.Stipple[I915_STPREG_ST0] = _3DSTATE_STIPPLE;
1032 }
1033
1034
1035 {
1036 I915_STATECHANGE(i915, I915_UPLOAD_FOG);
1037 i915->state.Fog[I915_FOGREG_MODE0] = _3DSTATE_FOG_MODE_CMD;
1038 i915->state.Fog[I915_FOGREG_MODE1] = (FMC1_FOGFUNC_MODIFY_ENABLE |
1039 FMC1_FOGFUNC_VERTEX |
1040 FMC1_FOGINDEX_MODIFY_ENABLE |
1041 FMC1_FOGINDEX_W |
1042 FMC1_C1_C2_MODIFY_ENABLE |
1043 FMC1_DENSITY_MODIFY_ENABLE);
1044 i915->state.Fog[I915_FOGREG_COLOR] = _3DSTATE_FOG_COLOR_CMD;
1045 }
1046
1047 {
1048 i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
1049
1050 /* scissor */
1051 i915->state.Buffer[I915_DESTREG_SENABLE] =
1052 (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
1053 i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
1054 i915->state.Buffer[I915_DESTREG_SR1] = 0;
1055 i915->state.Buffer[I915_DESTREG_SR2] = 0;
1056 }
1057
1058 i915->state.RasterRules[I915_RASTER_RULES] = _3DSTATE_RASTER_RULES_CMD |
1059 ENABLE_POINT_RASTER_RULE |
1060 OGL_POINT_RASTER_RULE |
1061 ENABLE_LINE_STRIP_PROVOKE_VRTX |
1062 ENABLE_TRI_FAN_PROVOKE_VRTX |
1063 LINE_STRIP_PROVOKE_VRTX(1) |
1064 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D;
1065
1066 #if 0
1067 {
1068 I915_STATECHANGE(i915, I915_UPLOAD_DEFAULTS);
1069 i915->state.Default[I915_DEFREG_C0] = _3DSTATE_DEFAULT_DIFFUSE;
1070 i915->state.Default[I915_DEFREG_C1] = 0;
1071 i915->state.Default[I915_DEFREG_S0] = _3DSTATE_DEFAULT_SPECULAR;
1072 i915->state.Default[I915_DEFREG_S1] = 0;
1073 i915->state.Default[I915_DEFREG_Z0] = _3DSTATE_DEFAULT_Z;
1074 i915->state.Default[I915_DEFREG_Z1] = 0;
1075 }
1076 #endif
1077
1078
1079 /* These will be emitted every at the head of every buffer, unless
1080 * we get hardware contexts working.
1081 */
1082 i915->state.active = (I915_UPLOAD_PROGRAM |
1083 I915_UPLOAD_STIPPLE |
1084 I915_UPLOAD_CTX |
1085 I915_UPLOAD_BLEND |
1086 I915_UPLOAD_BUFFERS |
1087 I915_UPLOAD_INVARIENT |
1088 I915_UPLOAD_RASTER_RULES);
1089 }
1090
1091 void
1092 i915_update_provoking_vertex(struct gl_context * ctx)
1093 {
1094 struct i915_context *i915 = I915_CONTEXT(ctx);
1095
1096 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
1097 i915->state.Ctx[I915_CTXREG_LIS6] &= ~(S6_TRISTRIP_PV_MASK);
1098
1099 I915_STATECHANGE(i915, I915_UPLOAD_RASTER_RULES);
1100 i915->state.RasterRules[I915_RASTER_RULES] &= ~(LINE_STRIP_PROVOKE_VRTX_MASK |
1101 TRI_FAN_PROVOKE_VRTX_MASK);
1102
1103 /* _NEW_LIGHT */
1104 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION) {
1105 i915->state.RasterRules[I915_RASTER_RULES] |= (LINE_STRIP_PROVOKE_VRTX(1) |
1106 TRI_FAN_PROVOKE_VRTX(2));
1107 i915->state.Ctx[I915_CTXREG_LIS6] |= (2 << S6_TRISTRIP_PV_SHIFT);
1108 } else {
1109 i915->state.RasterRules[I915_RASTER_RULES] |= (LINE_STRIP_PROVOKE_VRTX(0) |
1110 TRI_FAN_PROVOKE_VRTX(1));
1111 i915->state.Ctx[I915_CTXREG_LIS6] |= (0 << S6_TRISTRIP_PV_SHIFT);
1112 }
1113 }
1114
1115 void
1116 i915InitStateFunctions(struct dd_function_table *functions)
1117 {
1118 functions->AlphaFunc = i915AlphaFunc;
1119 functions->BlendColor = i915BlendColor;
1120 functions->BlendEquationSeparate = i915BlendEquationSeparate;
1121 functions->BlendFuncSeparate = i915BlendFuncSeparate;
1122 functions->ColorMask = i915ColorMask;
1123 functions->CullFace = i915CullFaceFrontFace;
1124 functions->DepthFunc = i915DepthFunc;
1125 functions->DepthMask = i915DepthMask;
1126 functions->Enable = i915Enable;
1127 functions->Fogfv = i915Fogfv;
1128 functions->FrontFace = i915CullFaceFrontFace;
1129 functions->Hint = i915Hint;
1130 functions->LightModelfv = i915LightModelfv;
1131 functions->LineWidth = i915LineWidth;
1132 functions->LogicOpcode = i915LogicOp;
1133 functions->PointSize = i915PointSize;
1134 functions->PointParameterfv = i915PointParameterfv;
1135 functions->PolygonStipple = i915PolygonStipple;
1136 functions->Scissor = i915Scissor;
1137 functions->ShadeModel = i915ShadeModel;
1138 functions->StencilFuncSeparate = i915StencilFuncSeparate;
1139 functions->StencilMaskSeparate = i915StencilMaskSeparate;
1140 functions->StencilOpSeparate = i915StencilOpSeparate;
1141 functions->DepthRange = i915DepthRange;
1142 functions->Viewport = i915Viewport;
1143 }
1144
1145
1146 void
1147 i915InitState(struct i915_context *i915)
1148 {
1149 struct gl_context *ctx = &i915->intel.ctx;
1150
1151 i915_init_packets(i915);
1152
1153 _mesa_init_driver_state(ctx);
1154 }