i915: Add support for EXT_stencil_two_side and ATI_separate_stencil.
[mesa.git] / src / mesa / drivers / dri / i915 / i915_state.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
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11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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26 **************************************************************************/
27
28
29 #include "main/glheader.h"
30 #include "main/context.h"
31 #include "main/macros.h"
32 #include "main/enums.h"
33 #include "main/dd.h"
34 #include "tnl/tnl.h"
35 #include "tnl/t_context.h"
36
37 #include "texmem.h"
38
39 #include "drivers/common/driverfuncs.h"
40
41 #include "intel_fbo.h"
42 #include "intel_screen.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_buffers.h"
45
46 #include "i915_context.h"
47 #include "i915_reg.h"
48
49 #define FILE_DEBUG_FLAG DEBUG_STATE
50
51 void
52 i915_update_stencil(GLcontext * ctx)
53 {
54 struct i915_context *i915 = I915_CONTEXT(ctx);
55 GLuint front_ref, front_writemask, front_mask;
56 GLenum front_func, front_fail, front_pass_z_fail, front_pass_z_pass;
57 GLuint back_ref, back_writemask, back_mask;
58 GLenum back_func, back_fail, back_pass_z_fail, back_pass_z_pass;
59
60 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
61
62 /* The 915 considers CW to be "front" for two-sided stencil, so choose
63 * appropriately.
64 */
65 /* _NEW_POLYGON | _NEW_STENCIL */
66 if (ctx->Polygon.FrontFace == GL_CW) {
67 front_ref = ctx->Stencil.Ref[0];
68 front_mask = ctx->Stencil.ValueMask[0];
69 front_writemask = ctx->Stencil.WriteMask[0];
70 front_func = ctx->Stencil.Function[0];
71 front_fail = ctx->Stencil.FailFunc[0];
72 front_pass_z_fail = ctx->Stencil.ZFailFunc[0];
73 front_pass_z_pass = ctx->Stencil.ZPassFunc[0];
74 back_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
75 back_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
76 back_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
77 back_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
78 back_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
79 back_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
80 back_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
81 } else {
82 front_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
83 front_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
84 front_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
85 front_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
86 front_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
87 front_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
88 front_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
89 back_ref = ctx->Stencil.Ref[0];
90 back_mask = ctx->Stencil.ValueMask[0];
91 back_writemask = ctx->Stencil.WriteMask[0];
92 back_func = ctx->Stencil.Function[0];
93 back_fail = ctx->Stencil.FailFunc[0];
94 back_pass_z_fail = ctx->Stencil.ZFailFunc[0];
95 back_pass_z_pass = ctx->Stencil.ZPassFunc[0];
96 }
97
98 /* Set front state. */
99 i915->state.Ctx[I915_CTXREG_STATE4] &= ~(MODE4_ENABLE_STENCIL_TEST_MASK |
100 MODE4_ENABLE_STENCIL_WRITE_MASK);
101 i915->state.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
102 ENABLE_STENCIL_WRITE_MASK |
103 STENCIL_TEST_MASK(front_mask) |
104 STENCIL_WRITE_MASK(front_writemask));
105
106 i915->state.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_REF_MASK |
107 S5_STENCIL_TEST_FUNC_MASK |
108 S5_STENCIL_FAIL_MASK |
109 S5_STENCIL_PASS_Z_FAIL_MASK |
110 S5_STENCIL_PASS_Z_PASS_MASK);
111
112 i915->state.Ctx[I915_CTXREG_LIS5] |=
113 (front_ref << S5_STENCIL_REF_SHIFT) |
114 (intel_translate_compare_func(front_func) << S5_STENCIL_TEST_FUNC_SHIFT) |
115 (intel_translate_stencil_op(front_fail) << S5_STENCIL_FAIL_SHIFT) |
116 (intel_translate_stencil_op(front_pass_z_fail) <<
117 S5_STENCIL_PASS_Z_FAIL_SHIFT) |
118 (intel_translate_stencil_op(front_pass_z_pass) <<
119 S5_STENCIL_PASS_Z_PASS_SHIFT);
120
121 /* Set back state if different from front. */
122 if (ctx->Stencil._TestTwoSide) {
123 i915->state.Ctx[I915_CTXREG_BF_STENCIL_OPS] &=
124 ~(BFO_STENCIL_REF_MASK |
125 BFO_STENCIL_TEST_MASK |
126 BFO_STENCIL_FAIL_MASK |
127 BFO_STENCIL_PASS_Z_FAIL_MASK |
128 BFO_STENCIL_PASS_Z_PASS_MASK);
129 i915->state.Ctx[I915_CTXREG_BF_STENCIL_OPS] |= BFO_STENCIL_TWO_SIDE |
130 (back_ref << BFO_STENCIL_REF_SHIFT) |
131 (intel_translate_compare_func(back_func) << BFO_STENCIL_TEST_SHIFT) |
132 (intel_translate_stencil_op(back_fail) << BFO_STENCIL_FAIL_SHIFT) |
133 (intel_translate_stencil_op(back_pass_z_fail) <<
134 BFO_STENCIL_PASS_Z_FAIL_SHIFT) |
135 (intel_translate_stencil_op(back_pass_z_pass) <<
136 BFO_STENCIL_PASS_Z_PASS_SHIFT);
137
138 i915->state.Ctx[I915_CTXREG_BF_STENCIL_MASKS] &=
139 ~(BFM_STENCIL_TEST_MASK_MASK |
140 BFM_STENCIL_WRITE_MASK_MASK);
141 i915->state.Ctx[I915_CTXREG_BF_STENCIL_MASKS] |=
142 BFM_STENCIL_TEST_MASK(back_mask) |
143 BFM_STENCIL_WRITE_MASK(back_writemask);
144 } else {
145 i915->state.Ctx[I915_CTXREG_BF_STENCIL_OPS] &= ~BFO_STENCIL_TWO_SIDE;
146 }
147 }
148
149 static void
150 i915StencilFuncSeparate(GLcontext * ctx, GLenum face, GLenum func, GLint ref,
151 GLuint mask)
152 {
153 }
154
155 static void
156 i915StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask)
157 {
158 }
159
160 static void
161 i915StencilOpSeparate(GLcontext * ctx, GLenum face, GLenum fail, GLenum zfail,
162 GLenum zpass)
163 {
164 }
165
166 static void
167 i915AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref)
168 {
169 struct i915_context *i915 = I915_CONTEXT(ctx);
170 int test = intel_translate_compare_func(func);
171 GLubyte refByte;
172
173 UNCLAMPED_FLOAT_TO_UBYTE(refByte, ref);
174
175 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
176 i915->state.Ctx[I915_CTXREG_LIS6] &= ~(S6_ALPHA_TEST_FUNC_MASK |
177 S6_ALPHA_REF_MASK);
178 i915->state.Ctx[I915_CTXREG_LIS6] |= ((test << S6_ALPHA_TEST_FUNC_SHIFT) |
179 (((GLuint) refByte) <<
180 S6_ALPHA_REF_SHIFT));
181 }
182
183 /* This function makes sure that the proper enables are
184 * set for LogicOp, Independant Alpha Blend, and Blending.
185 * It needs to be called from numerous places where we
186 * could change the LogicOp or Independant Alpha Blend without subsequent
187 * calls to glEnable.
188 */
189 static void
190 i915EvalLogicOpBlendState(GLcontext * ctx)
191 {
192 struct i915_context *i915 = I915_CONTEXT(ctx);
193
194 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
195
196 if (RGBA_LOGICOP_ENABLED(ctx)) {
197 i915->state.Ctx[I915_CTXREG_LIS5] |= S5_LOGICOP_ENABLE;
198 i915->state.Ctx[I915_CTXREG_LIS6] &= ~S6_CBUF_BLEND_ENABLE;
199 }
200 else {
201 i915->state.Ctx[I915_CTXREG_LIS5] &= ~S5_LOGICOP_ENABLE;
202
203 if (ctx->Color.BlendEnabled) {
204 i915->state.Ctx[I915_CTXREG_LIS6] |= S6_CBUF_BLEND_ENABLE;
205 }
206 else {
207 i915->state.Ctx[I915_CTXREG_LIS6] &= ~S6_CBUF_BLEND_ENABLE;
208 }
209 }
210 }
211
212 static void
213 i915BlendColor(GLcontext * ctx, const GLfloat color[4])
214 {
215 struct i915_context *i915 = I915_CONTEXT(ctx);
216 GLubyte r, g, b, a;
217
218 DBG("%s\n", __FUNCTION__);
219
220 UNCLAMPED_FLOAT_TO_UBYTE(r, color[RCOMP]);
221 UNCLAMPED_FLOAT_TO_UBYTE(g, color[GCOMP]);
222 UNCLAMPED_FLOAT_TO_UBYTE(b, color[BCOMP]);
223 UNCLAMPED_FLOAT_TO_UBYTE(a, color[ACOMP]);
224
225 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
226 i915->state.Ctx[I915_CTXREG_BLENDCOLOR1] =
227 (a << 24) | (r << 16) | (g << 8) | b;
228 }
229
230
231 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
232 #define SRC_BLND_FACT(f) ((f)<<S6_CBUF_SRC_BLEND_FACT_SHIFT)
233 #define DST_ABLND_FACT(f) ((f)<<IAB_DST_FACTOR_SHIFT)
234 #define SRC_ABLND_FACT(f) ((f)<<IAB_SRC_FACTOR_SHIFT)
235
236
237
238 static GLuint
239 translate_blend_equation(GLenum mode)
240 {
241 switch (mode) {
242 case GL_FUNC_ADD:
243 return BLENDFUNC_ADD;
244 case GL_MIN:
245 return BLENDFUNC_MIN;
246 case GL_MAX:
247 return BLENDFUNC_MAX;
248 case GL_FUNC_SUBTRACT:
249 return BLENDFUNC_SUBTRACT;
250 case GL_FUNC_REVERSE_SUBTRACT:
251 return BLENDFUNC_REVERSE_SUBTRACT;
252 default:
253 return 0;
254 }
255 }
256
257 static void
258 i915UpdateBlendState(GLcontext * ctx)
259 {
260 struct i915_context *i915 = I915_CONTEXT(ctx);
261 GLuint iab = (i915->state.Ctx[I915_CTXREG_IAB] &
262 ~(IAB_SRC_FACTOR_MASK |
263 IAB_DST_FACTOR_MASK |
264 (BLENDFUNC_MASK << IAB_FUNC_SHIFT) | IAB_ENABLE));
265
266 GLuint lis6 = (i915->state.Ctx[I915_CTXREG_LIS6] &
267 ~(S6_CBUF_SRC_BLEND_FACT_MASK |
268 S6_CBUF_DST_BLEND_FACT_MASK | S6_CBUF_BLEND_FUNC_MASK));
269
270 GLuint eqRGB = ctx->Color.BlendEquationRGB;
271 GLuint eqA = ctx->Color.BlendEquationA;
272 GLuint srcRGB = ctx->Color.BlendSrcRGB;
273 GLuint dstRGB = ctx->Color.BlendDstRGB;
274 GLuint srcA = ctx->Color.BlendSrcA;
275 GLuint dstA = ctx->Color.BlendDstA;
276
277 if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
278 srcRGB = dstRGB = GL_ONE;
279 }
280
281 if (eqA == GL_MIN || eqA == GL_MAX) {
282 srcA = dstA = GL_ONE;
283 }
284
285 lis6 |= SRC_BLND_FACT(intel_translate_blend_factor(srcRGB));
286 lis6 |= DST_BLND_FACT(intel_translate_blend_factor(dstRGB));
287 lis6 |= translate_blend_equation(eqRGB) << S6_CBUF_BLEND_FUNC_SHIFT;
288
289 iab |= SRC_ABLND_FACT(intel_translate_blend_factor(srcA));
290 iab |= DST_ABLND_FACT(intel_translate_blend_factor(dstA));
291 iab |= translate_blend_equation(eqA) << IAB_FUNC_SHIFT;
292
293 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB)
294 iab |= IAB_ENABLE;
295
296 if (iab != i915->state.Ctx[I915_CTXREG_IAB] ||
297 lis6 != i915->state.Ctx[I915_CTXREG_LIS6]) {
298 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
299 i915->state.Ctx[I915_CTXREG_IAB] = iab;
300 i915->state.Ctx[I915_CTXREG_LIS6] = lis6;
301 }
302
303 /* This will catch a logicop blend equation */
304 i915EvalLogicOpBlendState(ctx);
305 }
306
307
308 static void
309 i915BlendFuncSeparate(GLcontext * ctx, GLenum srcRGB,
310 GLenum dstRGB, GLenum srcA, GLenum dstA)
311 {
312 i915UpdateBlendState(ctx);
313 }
314
315
316 static void
317 i915BlendEquationSeparate(GLcontext * ctx, GLenum eqRGB, GLenum eqA)
318 {
319 i915UpdateBlendState(ctx);
320 }
321
322
323 static void
324 i915DepthFunc(GLcontext * ctx, GLenum func)
325 {
326 struct i915_context *i915 = I915_CONTEXT(ctx);
327 int test = intel_translate_compare_func(func);
328
329 DBG("%s\n", __FUNCTION__);
330
331 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
332 i915->state.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_TEST_FUNC_MASK;
333 i915->state.Ctx[I915_CTXREG_LIS6] |= test << S6_DEPTH_TEST_FUNC_SHIFT;
334 }
335
336 static void
337 i915DepthMask(GLcontext * ctx, GLboolean flag)
338 {
339 struct i915_context *i915 = I915_CONTEXT(ctx);
340
341 DBG("%s flag (%d)\n", __FUNCTION__, flag);
342
343 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
344
345 if (flag && ctx->Depth.Test)
346 i915->state.Ctx[I915_CTXREG_LIS6] |= S6_DEPTH_WRITE_ENABLE;
347 else
348 i915->state.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_WRITE_ENABLE;
349 }
350
351
352
353 /**
354 * Update the viewport transformation matrix. Depends on:
355 * - viewport pos/size
356 * - depthrange
357 * - window pos/size or FBO size
358 */
359 void
360 intelCalcViewport(GLcontext * ctx)
361 {
362 struct intel_context *intel = intel_context(ctx);
363 const GLfloat *v = ctx->Viewport._WindowMap.m;
364 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
365 GLfloat *m = intel->ViewportMatrix.m;
366 GLfloat yScale, yBias;
367
368 if (ctx->DrawBuffer->Name) {
369 /* User created FBO */
370 /* y=0=bottom */
371 yScale = 1.0;
372 yBias = 0.0;
373 }
374 else {
375 /* window buffer, y=0=top */
376 yScale = -1.0;
377 yBias = (intel->driDrawable) ? intel->driDrawable->h : 0.0F;
378 }
379
380 m[MAT_SX] = v[MAT_SX];
381 m[MAT_TX] = v[MAT_TX];
382
383 m[MAT_SY] = v[MAT_SY] * yScale;
384 m[MAT_TY] = v[MAT_TY] * yScale + yBias;
385
386 m[MAT_SZ] = v[MAT_SZ] * depthScale;
387 m[MAT_TZ] = v[MAT_TZ] * depthScale;
388 }
389
390
391 /** Called from ctx->Driver.Viewport() */
392 static void
393 i915Viewport(GLcontext * ctx,
394 GLint x, GLint y, GLsizei width, GLsizei height)
395 {
396 intelCalcViewport(ctx);
397
398 intel_viewport(ctx, x, y, width, height);
399 }
400
401
402 /** Called from ctx->Driver.DepthRange() */
403 static void
404 i915DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval)
405 {
406 intelCalcViewport(ctx);
407 }
408
409
410 /* =============================================================
411 * Polygon stipple
412 *
413 * The i915 supports a 4x4 stipple natively, GL wants 32x32.
414 * Fortunately stipple is usually a repeating pattern.
415 */
416 static void
417 i915PolygonStipple(GLcontext * ctx, const GLubyte * mask)
418 {
419 struct i915_context *i915 = I915_CONTEXT(ctx);
420 const GLubyte *m;
421 GLubyte p[4];
422 int i, j, k;
423 int active = (ctx->Polygon.StippleFlag &&
424 i915->intel.reduced_primitive == GL_TRIANGLES);
425 GLuint newMask;
426
427 if (active) {
428 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
429 i915->state.Stipple[I915_STPREG_ST1] &= ~ST1_ENABLE;
430 }
431
432 /* Use the already unpacked stipple data from the context rather than the
433 * uninterpreted mask passed in.
434 */
435 mask = (const GLubyte *)ctx->PolygonStipple;
436 m = mask;
437
438 p[0] = mask[12] & 0xf;
439 p[0] |= p[0] << 4;
440 p[1] = mask[8] & 0xf;
441 p[1] |= p[1] << 4;
442 p[2] = mask[4] & 0xf;
443 p[2] |= p[2] << 4;
444 p[3] = mask[0] & 0xf;
445 p[3] |= p[3] << 4;
446
447 for (k = 0; k < 8; k++)
448 for (j = 3; j >= 0; j--)
449 for (i = 0; i < 4; i++, m++)
450 if (*m != p[j]) {
451 i915->intel.hw_stipple = 0;
452 return;
453 }
454
455 newMask = (((p[0] & 0xf) << 0) |
456 ((p[1] & 0xf) << 4) |
457 ((p[2] & 0xf) << 8) | ((p[3] & 0xf) << 12));
458
459
460 if (newMask == 0xffff || newMask == 0x0) {
461 /* this is needed to make conform pass */
462 i915->intel.hw_stipple = 0;
463 return;
464 }
465
466 i915->state.Stipple[I915_STPREG_ST1] &= ~0xffff;
467 i915->state.Stipple[I915_STPREG_ST1] |= newMask;
468 i915->intel.hw_stipple = 1;
469
470 if (active)
471 i915->state.Stipple[I915_STPREG_ST1] |= ST1_ENABLE;
472 }
473
474
475 /* =============================================================
476 * Hardware clipping
477 */
478 static void
479 i915Scissor(GLcontext * ctx, GLint x, GLint y, GLsizei w, GLsizei h)
480 {
481 struct i915_context *i915 = I915_CONTEXT(ctx);
482 int x1, y1, x2, y2;
483
484 if (!ctx->DrawBuffer)
485 return;
486
487 DBG("%s %d,%d %dx%d\n", __FUNCTION__, x, y, w, h);
488
489 if (ctx->DrawBuffer->Name == 0) {
490 x1 = x;
491 y1 = ctx->DrawBuffer->Height - (y + h);
492 x2 = x + w - 1;
493 y2 = y1 + h - 1;
494 DBG("%s %d..%d,%d..%d (inverted)\n", __FUNCTION__, x1, x2, y1, y2);
495 }
496 else {
497 /* FBO - not inverted
498 */
499 x1 = x;
500 y1 = y;
501 x2 = x + w - 1;
502 y2 = y + h - 1;
503 DBG("%s %d..%d,%d..%d (not inverted)\n", __FUNCTION__, x1, x2, y1, y2);
504 }
505
506 x1 = CLAMP(x1, 0, ctx->DrawBuffer->Width - 1);
507 y1 = CLAMP(y1, 0, ctx->DrawBuffer->Height - 1);
508 x2 = CLAMP(x2, 0, ctx->DrawBuffer->Width - 1);
509 y2 = CLAMP(y2, 0, ctx->DrawBuffer->Height - 1);
510
511 DBG("%s %d..%d,%d..%d (clamped)\n", __FUNCTION__, x1, x2, y1, y2);
512
513 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
514 i915->state.Buffer[I915_DESTREG_SR1] = (y1 << 16) | (x1 & 0xffff);
515 i915->state.Buffer[I915_DESTREG_SR2] = (y2 << 16) | (x2 & 0xffff);
516 }
517
518 static void
519 i915LogicOp(GLcontext * ctx, GLenum opcode)
520 {
521 struct i915_context *i915 = I915_CONTEXT(ctx);
522 int tmp = intel_translate_logic_op(opcode);
523
524 DBG("%s\n", __FUNCTION__);
525
526 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
527 i915->state.Ctx[I915_CTXREG_STATE4] &= ~LOGICOP_MASK;
528 i915->state.Ctx[I915_CTXREG_STATE4] |= LOGIC_OP_FUNC(tmp);
529 }
530
531
532
533 static void
534 i915CullFaceFrontFace(GLcontext * ctx, GLenum unused)
535 {
536 struct i915_context *i915 = I915_CONTEXT(ctx);
537 GLuint mode;
538
539 DBG("%s %d\n", __FUNCTION__,
540 ctx->DrawBuffer ? ctx->DrawBuffer->Name : 0);
541
542 if (!ctx->Polygon.CullFlag) {
543 mode = S4_CULLMODE_NONE;
544 }
545 else if (ctx->Polygon.CullFaceMode != GL_FRONT_AND_BACK) {
546 mode = S4_CULLMODE_CW;
547
548 if (ctx->DrawBuffer && ctx->DrawBuffer->Name != 0)
549 mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
550 if (ctx->Polygon.CullFaceMode == GL_FRONT)
551 mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
552 if (ctx->Polygon.FrontFace != GL_CCW)
553 mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
554 }
555 else {
556 mode = S4_CULLMODE_BOTH;
557 }
558
559 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
560 i915->state.Ctx[I915_CTXREG_LIS4] &= ~S4_CULLMODE_MASK;
561 i915->state.Ctx[I915_CTXREG_LIS4] |= mode;
562 }
563
564 static void
565 i915LineWidth(GLcontext * ctx, GLfloat widthf)
566 {
567 struct i915_context *i915 = I915_CONTEXT(ctx);
568 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_LINE_WIDTH_MASK;
569 int width;
570
571 DBG("%s\n", __FUNCTION__);
572
573 width = (int) (widthf * 2);
574 CLAMP_SELF(width, 1, 0xf);
575 lis4 |= width << S4_LINE_WIDTH_SHIFT;
576
577 if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
578 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
579 i915->state.Ctx[I915_CTXREG_LIS4] = lis4;
580 }
581 }
582
583 static void
584 i915PointSize(GLcontext * ctx, GLfloat size)
585 {
586 struct i915_context *i915 = I915_CONTEXT(ctx);
587 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_POINT_WIDTH_MASK;
588 GLint point_size = (int) size;
589
590 DBG("%s\n", __FUNCTION__);
591
592 CLAMP_SELF(point_size, 1, 255);
593 lis4 |= point_size << S4_POINT_WIDTH_SHIFT;
594
595 if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
596 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
597 i915->state.Ctx[I915_CTXREG_LIS4] = lis4;
598 }
599 }
600
601
602 /* =============================================================
603 * Color masks
604 */
605
606 static void
607 i915ColorMask(GLcontext * ctx,
608 GLboolean r, GLboolean g, GLboolean b, GLboolean a)
609 {
610 struct i915_context *i915 = I915_CONTEXT(ctx);
611 GLuint tmp = i915->state.Ctx[I915_CTXREG_LIS5] & ~S5_WRITEDISABLE_MASK;
612
613 DBG("%s r(%d) g(%d) b(%d) a(%d)\n", __FUNCTION__, r, g, b,
614 a);
615
616 if (!r)
617 tmp |= S5_WRITEDISABLE_RED;
618 if (!g)
619 tmp |= S5_WRITEDISABLE_GREEN;
620 if (!b)
621 tmp |= S5_WRITEDISABLE_BLUE;
622 if (!a)
623 tmp |= S5_WRITEDISABLE_ALPHA;
624
625 if (tmp != i915->state.Ctx[I915_CTXREG_LIS5]) {
626 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
627 i915->state.Ctx[I915_CTXREG_LIS5] = tmp;
628 }
629 }
630
631 static void
632 update_specular(GLcontext * ctx)
633 {
634 /* A hack to trigger the rebuild of the fragment program.
635 */
636 intel_context(ctx)->NewGLState |= _NEW_TEXTURE;
637 }
638
639 static void
640 i915LightModelfv(GLcontext * ctx, GLenum pname, const GLfloat * param)
641 {
642 DBG("%s\n", __FUNCTION__);
643
644 if (pname == GL_LIGHT_MODEL_COLOR_CONTROL) {
645 update_specular(ctx);
646 }
647 }
648
649 static void
650 i915ShadeModel(GLcontext * ctx, GLenum mode)
651 {
652 struct i915_context *i915 = I915_CONTEXT(ctx);
653 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
654
655 if (mode == GL_SMOOTH) {
656 i915->state.Ctx[I915_CTXREG_LIS4] &= ~(S4_FLATSHADE_ALPHA |
657 S4_FLATSHADE_COLOR |
658 S4_FLATSHADE_SPECULAR);
659 }
660 else {
661 i915->state.Ctx[I915_CTXREG_LIS4] |= (S4_FLATSHADE_ALPHA |
662 S4_FLATSHADE_COLOR |
663 S4_FLATSHADE_SPECULAR);
664 }
665 }
666
667 /* =============================================================
668 * Fog
669 */
670 void
671 i915_update_fog(GLcontext * ctx)
672 {
673 struct i915_context *i915 = I915_CONTEXT(ctx);
674 GLenum mode;
675 GLboolean enabled;
676 GLboolean try_pixel_fog;
677
678 if (ctx->FragmentProgram._Current) {
679 /* Pull in static fog state from program */
680 mode = ctx->FragmentProgram._Current->FogOption;
681 enabled = (mode != GL_NONE);
682 try_pixel_fog = 0;
683 }
684 else {
685 enabled = ctx->Fog.Enabled;
686 mode = ctx->Fog.Mode;
687 #if 0
688 /* XXX - DISABLED -- Need ortho fallback */
689 try_pixel_fog = (ctx->Fog.FogCoordinateSource == GL_FRAGMENT_DEPTH_EXT
690 && ctx->Hint.Fog == GL_NICEST);
691 #else
692 try_pixel_fog = 0;
693 #endif
694 }
695
696 if (!enabled) {
697 i915->vertex_fog = I915_FOG_NONE;
698 }
699 else if (try_pixel_fog) {
700 I915_STATECHANGE(i915, I915_UPLOAD_FOG);
701 i915->state.Fog[I915_FOGREG_MODE1] &= ~FMC1_FOGFUNC_MASK;
702 i915->vertex_fog = I915_FOG_PIXEL;
703
704 switch (mode) {
705 case GL_LINEAR:
706 if (ctx->Fog.End <= ctx->Fog.Start) {
707 /* XXX - this won't work with fragment programs. Need to
708 * either fallback or append fog instructions to end of
709 * program in the case of linear fog.
710 */
711 printf("vertex fog!\n");
712 i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_VERTEX;
713 i915->vertex_fog = I915_FOG_VERTEX;
714 }
715 else {
716 GLfloat c2 = 1.0 / (ctx->Fog.End - ctx->Fog.Start);
717 GLfloat c1 = ctx->Fog.End * c2;
718
719 i915->state.Fog[I915_FOGREG_MODE1] &= ~FMC1_C1_MASK;
720 i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_PIXEL_LINEAR;
721 i915->state.Fog[I915_FOGREG_MODE1] |=
722 ((GLuint) (c1 * FMC1_C1_ONE)) & FMC1_C1_MASK;
723
724 if (i915->state.Fog[I915_FOGREG_MODE1] & FMC1_FOGINDEX_Z) {
725 i915->state.Fog[I915_FOGREG_MODE2]
726 = (GLuint) (c2 * FMC2_C2_ONE);
727 }
728 else {
729 fi_type fi;
730 fi.f = c2;
731 i915->state.Fog[I915_FOGREG_MODE2] = fi.i;
732 }
733 }
734 break;
735 case GL_EXP:
736 i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_PIXEL_EXP;
737 break;
738 case GL_EXP2:
739 i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_PIXEL_EXP2;
740 break;
741 default:
742 break;
743 }
744 }
745 else { /* if (i915->vertex_fog != I915_FOG_VERTEX) */
746 I915_STATECHANGE(i915, I915_UPLOAD_FOG);
747 i915->state.Fog[I915_FOGREG_MODE1] &= ~FMC1_FOGFUNC_MASK;
748 i915->state.Fog[I915_FOGREG_MODE1] |= FMC1_FOGFUNC_VERTEX;
749 i915->vertex_fog = I915_FOG_VERTEX;
750 }
751
752 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
753 I915_ACTIVESTATE(i915, I915_UPLOAD_FOG, enabled);
754 if (enabled)
755 i915->state.Ctx[I915_CTXREG_LIS5] |= S5_FOG_ENABLE;
756 else
757 i915->state.Ctx[I915_CTXREG_LIS5] &= ~S5_FOG_ENABLE;
758
759 /* Always enable pixel fog. Vertex fog using fog coord will conflict
760 * with fog code appended onto fragment program.
761 */
762 _tnl_allow_vertex_fog( ctx, 0 );
763 _tnl_allow_pixel_fog( ctx, 1 );
764 }
765
766 static void
767 i915Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param)
768 {
769 struct i915_context *i915 = I915_CONTEXT(ctx);
770
771 switch (pname) {
772 case GL_FOG_COORDINATE_SOURCE_EXT:
773 case GL_FOG_MODE:
774 case GL_FOG_START:
775 case GL_FOG_END:
776 break;
777
778 case GL_FOG_DENSITY:
779 I915_STATECHANGE(i915, I915_UPLOAD_FOG);
780
781 if (i915->state.Fog[I915_FOGREG_MODE1] & FMC1_FOGINDEX_Z) {
782 i915->state.Fog[I915_FOGREG_MODE3] =
783 (GLuint) (ctx->Fog.Density * FMC3_D_ONE);
784 }
785 else {
786 fi_type fi;
787 fi.f = ctx->Fog.Density;
788 i915->state.Fog[I915_FOGREG_MODE3] = fi.i;
789 }
790 break;
791
792 case GL_FOG_COLOR:
793 I915_STATECHANGE(i915, I915_UPLOAD_FOG);
794 i915->state.Fog[I915_FOGREG_COLOR] =
795 (_3DSTATE_FOG_COLOR_CMD |
796 ((GLubyte) (ctx->Fog.Color[0] * 255.0F) << 16) |
797 ((GLubyte) (ctx->Fog.Color[1] * 255.0F) << 8) |
798 ((GLubyte) (ctx->Fog.Color[2] * 255.0F) << 0));
799 break;
800
801 default:
802 break;
803 }
804 }
805
806 static void
807 i915Hint(GLcontext * ctx, GLenum target, GLenum state)
808 {
809 switch (target) {
810 case GL_FOG_HINT:
811 break;
812 default:
813 break;
814 }
815 }
816
817 /* =============================================================
818 */
819
820 static void
821 i915Enable(GLcontext * ctx, GLenum cap, GLboolean state)
822 {
823 struct i915_context *i915 = I915_CONTEXT(ctx);
824
825 switch (cap) {
826 case GL_TEXTURE_2D:
827 break;
828
829 case GL_LIGHTING:
830 case GL_COLOR_SUM:
831 update_specular(ctx);
832 break;
833
834 case GL_ALPHA_TEST:
835 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
836 if (state)
837 i915->state.Ctx[I915_CTXREG_LIS6] |= S6_ALPHA_TEST_ENABLE;
838 else
839 i915->state.Ctx[I915_CTXREG_LIS6] &= ~S6_ALPHA_TEST_ENABLE;
840 break;
841
842 case GL_BLEND:
843 i915EvalLogicOpBlendState(ctx);
844 break;
845
846 case GL_COLOR_LOGIC_OP:
847 i915EvalLogicOpBlendState(ctx);
848
849 /* Logicop doesn't seem to work at 16bpp:
850 */
851 if (ctx->Visual.rgbBits == 16)
852 FALLBACK(&i915->intel, I915_FALLBACK_LOGICOP, state);
853 break;
854
855 case GL_FRAGMENT_PROGRAM_ARB:
856 break;
857
858 case GL_DITHER:
859 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
860 if (state)
861 i915->state.Ctx[I915_CTXREG_LIS5] |= S5_COLOR_DITHER_ENABLE;
862 else
863 i915->state.Ctx[I915_CTXREG_LIS5] &= ~S5_COLOR_DITHER_ENABLE;
864 break;
865
866 case GL_DEPTH_TEST:
867 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
868 if (state)
869 i915->state.Ctx[I915_CTXREG_LIS6] |= S6_DEPTH_TEST_ENABLE;
870 else
871 i915->state.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_TEST_ENABLE;
872
873 i915DepthMask(ctx, ctx->Depth.Mask);
874 break;
875
876 case GL_SCISSOR_TEST:
877 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
878 if (state)
879 i915->state.Buffer[I915_DESTREG_SENABLE] =
880 (_3DSTATE_SCISSOR_ENABLE_CMD | ENABLE_SCISSOR_RECT);
881 else
882 i915->state.Buffer[I915_DESTREG_SENABLE] =
883 (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
884 break;
885
886 case GL_LINE_SMOOTH:
887 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
888 if (state)
889 i915->state.Ctx[I915_CTXREG_LIS4] |= S4_LINE_ANTIALIAS_ENABLE;
890 else
891 i915->state.Ctx[I915_CTXREG_LIS4] &= ~S4_LINE_ANTIALIAS_ENABLE;
892 break;
893
894 case GL_FOG:
895 break;
896
897 case GL_CULL_FACE:
898 i915CullFaceFrontFace(ctx, 0);
899 break;
900
901 case GL_STENCIL_TEST:
902 {
903 GLboolean hw_stencil = GL_FALSE;
904 if (ctx->DrawBuffer) {
905 struct intel_renderbuffer *irbStencil
906 = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
907 hw_stencil = (irbStencil && irbStencil->region);
908 }
909 if (hw_stencil) {
910 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
911 if (state)
912 i915->state.Ctx[I915_CTXREG_LIS5] |= (S5_STENCIL_TEST_ENABLE |
913 S5_STENCIL_WRITE_ENABLE);
914 else
915 i915->state.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_TEST_ENABLE |
916 S5_STENCIL_WRITE_ENABLE);
917 }
918 else {
919 FALLBACK(&i915->intel, I915_FALLBACK_STENCIL, state);
920 }
921 }
922 break;
923
924 case GL_POLYGON_STIPPLE:
925 /* The stipple command worked on my 855GM box, but not my 845G.
926 * I'll do more testing later to find out exactly which hardware
927 * supports it. Disabled for now.
928 */
929 if (i915->intel.hw_stipple &&
930 i915->intel.reduced_primitive == GL_TRIANGLES) {
931 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
932 if (state)
933 i915->state.Stipple[I915_STPREG_ST1] |= ST1_ENABLE;
934 else
935 i915->state.Stipple[I915_STPREG_ST1] &= ~ST1_ENABLE;
936 }
937 break;
938
939 case GL_POLYGON_SMOOTH:
940 break;
941
942 case GL_POINT_SMOOTH:
943 break;
944
945 default:
946 ;
947 }
948 }
949
950
951 static void
952 i915_init_packets(struct i915_context *i915)
953 {
954 /* Zero all state */
955 memset(&i915->state, 0, sizeof(i915->state));
956
957
958 {
959 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
960 /* Probably don't want to upload all this stuff every time one
961 * piece changes.
962 */
963 i915->state.Ctx[I915_CTXREG_LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
964 I1_LOAD_S(2) |
965 I1_LOAD_S(4) |
966 I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
967 i915->state.Ctx[I915_CTXREG_LIS2] = 0;
968 i915->state.Ctx[I915_CTXREG_LIS4] = 0;
969 i915->state.Ctx[I915_CTXREG_LIS5] = 0;
970
971 if (i915->intel.ctx.Visual.rgbBits == 16)
972 i915->state.Ctx[I915_CTXREG_LIS5] |= S5_COLOR_DITHER_ENABLE;
973
974
975 i915->state.Ctx[I915_CTXREG_LIS6] = (S6_COLOR_WRITE_ENABLE |
976 (2 << S6_TRISTRIP_PV_SHIFT));
977
978 i915->state.Ctx[I915_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
979 ENABLE_LOGIC_OP_FUNC |
980 LOGIC_OP_FUNC(LOGICOP_COPY) |
981 ENABLE_STENCIL_TEST_MASK |
982 STENCIL_TEST_MASK(0xff) |
983 ENABLE_STENCIL_WRITE_MASK |
984 STENCIL_WRITE_MASK(0xff));
985
986 i915->state.Ctx[I915_CTXREG_IAB] =
987 (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE |
988 IAB_MODIFY_FUNC | IAB_MODIFY_SRC_FACTOR | IAB_MODIFY_DST_FACTOR);
989
990 i915->state.Ctx[I915_CTXREG_BLENDCOLOR0] =
991 _3DSTATE_CONST_BLEND_COLOR_CMD;
992 i915->state.Ctx[I915_CTXREG_BLENDCOLOR1] = 0;
993
994 i915->state.Ctx[I915_CTXREG_BF_STENCIL_MASKS] =
995 _3DSTATE_BACKFACE_STENCIL_MASKS |
996 BFM_ENABLE_STENCIL_TEST_MASK |
997 BFM_ENABLE_STENCIL_WRITE_MASK |
998 (0xff << BFM_STENCIL_WRITE_MASK_SHIFT) |
999 (0xff << BFM_STENCIL_TEST_MASK_SHIFT);
1000 i915->state.Ctx[I915_CTXREG_BF_STENCIL_OPS] =
1001 _3DSTATE_BACKFACE_STENCIL_OPS |
1002 BFO_ENABLE_STENCIL_REF |
1003 BFO_ENABLE_STENCIL_FUNCS |
1004 BFO_ENABLE_STENCIL_TWO_SIDE;
1005 }
1006
1007 {
1008 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
1009 i915->state.Stipple[I915_STPREG_ST0] = _3DSTATE_STIPPLE;
1010 }
1011
1012
1013 {
1014 I915_STATECHANGE(i915, I915_UPLOAD_FOG);
1015 i915->state.Fog[I915_FOGREG_MODE0] = _3DSTATE_FOG_MODE_CMD;
1016 i915->state.Fog[I915_FOGREG_MODE1] = (FMC1_FOGFUNC_MODIFY_ENABLE |
1017 FMC1_FOGFUNC_VERTEX |
1018 FMC1_FOGINDEX_MODIFY_ENABLE |
1019 FMC1_FOGINDEX_W |
1020 FMC1_C1_C2_MODIFY_ENABLE |
1021 FMC1_DENSITY_MODIFY_ENABLE);
1022 i915->state.Fog[I915_FOGREG_COLOR] = _3DSTATE_FOG_COLOR_CMD;
1023 }
1024
1025 {
1026 i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
1027
1028 /* scissor */
1029 i915->state.Buffer[I915_DESTREG_SENABLE] =
1030 (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
1031 i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
1032 i915->state.Buffer[I915_DESTREG_SR1] = 0;
1033 i915->state.Buffer[I915_DESTREG_SR2] = 0;
1034 }
1035
1036
1037 #if 0
1038 {
1039 I915_STATECHANGE(i915, I915_UPLOAD_DEFAULTS);
1040 i915->state.Default[I915_DEFREG_C0] = _3DSTATE_DEFAULT_DIFFUSE;
1041 i915->state.Default[I915_DEFREG_C1] = 0;
1042 i915->state.Default[I915_DEFREG_S0] = _3DSTATE_DEFAULT_SPECULAR;
1043 i915->state.Default[I915_DEFREG_S1] = 0;
1044 i915->state.Default[I915_DEFREG_Z0] = _3DSTATE_DEFAULT_Z;
1045 i915->state.Default[I915_DEFREG_Z1] = 0;
1046 }
1047 #endif
1048
1049
1050 /* These will be emitted every at the head of every buffer, unless
1051 * we get hardware contexts working.
1052 */
1053 i915->state.active = (I915_UPLOAD_PROGRAM |
1054 I915_UPLOAD_STIPPLE |
1055 I915_UPLOAD_CTX |
1056 I915_UPLOAD_BUFFERS | I915_UPLOAD_INVARIENT);
1057 }
1058
1059 void
1060 i915InitStateFunctions(struct dd_function_table *functions)
1061 {
1062 functions->AlphaFunc = i915AlphaFunc;
1063 functions->BlendColor = i915BlendColor;
1064 functions->BlendEquationSeparate = i915BlendEquationSeparate;
1065 functions->BlendFuncSeparate = i915BlendFuncSeparate;
1066 functions->ColorMask = i915ColorMask;
1067 functions->CullFace = i915CullFaceFrontFace;
1068 functions->DepthFunc = i915DepthFunc;
1069 functions->DepthMask = i915DepthMask;
1070 functions->Enable = i915Enable;
1071 functions->Fogfv = i915Fogfv;
1072 functions->FrontFace = i915CullFaceFrontFace;
1073 functions->Hint = i915Hint;
1074 functions->LightModelfv = i915LightModelfv;
1075 functions->LineWidth = i915LineWidth;
1076 functions->LogicOpcode = i915LogicOp;
1077 functions->PointSize = i915PointSize;
1078 functions->PolygonStipple = i915PolygonStipple;
1079 functions->Scissor = i915Scissor;
1080 functions->ShadeModel = i915ShadeModel;
1081 functions->StencilFuncSeparate = i915StencilFuncSeparate;
1082 functions->StencilMaskSeparate = i915StencilMaskSeparate;
1083 functions->StencilOpSeparate = i915StencilOpSeparate;
1084 functions->DepthRange = i915DepthRange;
1085 functions->Viewport = i915Viewport;
1086 }
1087
1088
1089 void
1090 i915InitState(struct i915_context *i915)
1091 {
1092 GLcontext *ctx = &i915->intel.ctx;
1093
1094 i915_init_packets(i915);
1095
1096 _mesa_init_driver_state(ctx);
1097
1098 memcpy(&i915->initial, &i915->state, sizeof(i915->state));
1099 i915->current = &i915->state;
1100 }