1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/glheader.h"
30 #include "main/context.h"
31 #include "main/macros.h"
32 #include "main/enums.h"
34 #include "main/state.h"
36 #include "tnl/t_context.h"
38 #include "drivers/common/driverfuncs.h"
40 #include "intel_fbo.h"
41 #include "intel_screen.h"
42 #include "intel_batchbuffer.h"
43 #include "intel_buffers.h"
45 #include "i915_context.h"
48 #define FILE_DEBUG_FLAG DEBUG_STATE
51 i915_update_stencil(struct gl_context
* ctx
)
53 struct i915_context
*i915
= I915_CONTEXT(ctx
);
54 GLuint front_ref
, front_writemask
, front_mask
;
55 GLenum front_func
, front_fail
, front_pass_z_fail
, front_pass_z_pass
;
56 GLuint back_ref
, back_writemask
, back_mask
;
57 GLenum back_func
, back_fail
, back_pass_z_fail
, back_pass_z_pass
;
60 /* The 915 considers CW to be "front" for two-sided stencil, so choose
63 /* _NEW_POLYGON | _NEW_STENCIL */
64 if (ctx
->Polygon
.FrontFace
== GL_CW
) {
65 front_ref
= ctx
->Stencil
.Ref
[0];
66 front_mask
= ctx
->Stencil
.ValueMask
[0];
67 front_writemask
= ctx
->Stencil
.WriteMask
[0];
68 front_func
= ctx
->Stencil
.Function
[0];
69 front_fail
= ctx
->Stencil
.FailFunc
[0];
70 front_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[0];
71 front_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[0];
72 back_ref
= ctx
->Stencil
.Ref
[ctx
->Stencil
._BackFace
];
73 back_mask
= ctx
->Stencil
.ValueMask
[ctx
->Stencil
._BackFace
];
74 back_writemask
= ctx
->Stencil
.WriteMask
[ctx
->Stencil
._BackFace
];
75 back_func
= ctx
->Stencil
.Function
[ctx
->Stencil
._BackFace
];
76 back_fail
= ctx
->Stencil
.FailFunc
[ctx
->Stencil
._BackFace
];
77 back_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[ctx
->Stencil
._BackFace
];
78 back_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[ctx
->Stencil
._BackFace
];
80 front_ref
= ctx
->Stencil
.Ref
[ctx
->Stencil
._BackFace
];
81 front_mask
= ctx
->Stencil
.ValueMask
[ctx
->Stencil
._BackFace
];
82 front_writemask
= ctx
->Stencil
.WriteMask
[ctx
->Stencil
._BackFace
];
83 front_func
= ctx
->Stencil
.Function
[ctx
->Stencil
._BackFace
];
84 front_fail
= ctx
->Stencil
.FailFunc
[ctx
->Stencil
._BackFace
];
85 front_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[ctx
->Stencil
._BackFace
];
86 front_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[ctx
->Stencil
._BackFace
];
87 back_ref
= ctx
->Stencil
.Ref
[0];
88 back_mask
= ctx
->Stencil
.ValueMask
[0];
89 back_writemask
= ctx
->Stencil
.WriteMask
[0];
90 back_func
= ctx
->Stencil
.Function
[0];
91 back_fail
= ctx
->Stencil
.FailFunc
[0];
92 back_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[0];
93 back_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[0];
95 #define set_ctx_bits(reg, mask, set) do{ \
96 GLuint dw = i915->state.Ctx[reg]; \
99 dirty |= dw != i915->state.Ctx[reg]; \
100 i915->state.Ctx[reg] = dw; \
103 /* Set front state. */
104 set_ctx_bits(I915_CTXREG_STATE4
,
105 MODE4_ENABLE_STENCIL_TEST_MASK
|
106 MODE4_ENABLE_STENCIL_WRITE_MASK
,
107 ENABLE_STENCIL_TEST_MASK
|
108 ENABLE_STENCIL_WRITE_MASK
|
109 STENCIL_TEST_MASK(front_mask
) |
110 STENCIL_WRITE_MASK(front_writemask
));
112 set_ctx_bits(I915_CTXREG_LIS5
,
113 S5_STENCIL_REF_MASK
|
114 S5_STENCIL_TEST_FUNC_MASK
|
115 S5_STENCIL_FAIL_MASK
|
116 S5_STENCIL_PASS_Z_FAIL_MASK
|
117 S5_STENCIL_PASS_Z_PASS_MASK
,
118 (front_ref
<< S5_STENCIL_REF_SHIFT
) |
119 (intel_translate_compare_func(front_func
) << S5_STENCIL_TEST_FUNC_SHIFT
) |
120 (intel_translate_stencil_op(front_fail
) << S5_STENCIL_FAIL_SHIFT
) |
121 (intel_translate_stencil_op(front_pass_z_fail
) <<
122 S5_STENCIL_PASS_Z_FAIL_SHIFT
) |
123 (intel_translate_stencil_op(front_pass_z_pass
) <<
124 S5_STENCIL_PASS_Z_PASS_SHIFT
));
126 /* Set back state if different from front. */
127 if (ctx
->Stencil
._TestTwoSide
) {
128 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS
,
129 BFO_STENCIL_REF_MASK
|
130 BFO_STENCIL_TEST_MASK
|
131 BFO_STENCIL_FAIL_MASK
|
132 BFO_STENCIL_PASS_Z_FAIL_MASK
|
133 BFO_STENCIL_PASS_Z_PASS_MASK
,
134 BFO_STENCIL_TWO_SIDE
|
135 (back_ref
<< BFO_STENCIL_REF_SHIFT
) |
136 (intel_translate_compare_func(back_func
) << BFO_STENCIL_TEST_SHIFT
) |
137 (intel_translate_stencil_op(back_fail
) << BFO_STENCIL_FAIL_SHIFT
) |
138 (intel_translate_stencil_op(back_pass_z_fail
) <<
139 BFO_STENCIL_PASS_Z_FAIL_SHIFT
) |
140 (intel_translate_stencil_op(back_pass_z_pass
) <<
141 BFO_STENCIL_PASS_Z_PASS_SHIFT
));
143 set_ctx_bits(I915_CTXREG_BF_STENCIL_MASKS
,
144 BFM_STENCIL_TEST_MASK_MASK
|
145 BFM_STENCIL_WRITE_MASK_MASK
,
146 BFM_STENCIL_TEST_MASK(back_mask
) |
147 BFM_STENCIL_WRITE_MASK(back_writemask
));
149 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS
,
150 BFO_STENCIL_TWO_SIDE
, 0);
156 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
160 i915StencilFuncSeparate(struct gl_context
* ctx
, GLenum face
, GLenum func
, GLint ref
,
166 i915StencilMaskSeparate(struct gl_context
* ctx
, GLenum face
, GLuint mask
)
171 i915StencilOpSeparate(struct gl_context
* ctx
, GLenum face
, GLenum fail
, GLenum zfail
,
177 i915AlphaFunc(struct gl_context
* ctx
, GLenum func
, GLfloat ref
)
179 struct i915_context
*i915
= I915_CONTEXT(ctx
);
180 int test
= intel_translate_compare_func(func
);
184 UNCLAMPED_FLOAT_TO_UBYTE(refByte
, ref
);
186 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
187 dw
&= ~(S6_ALPHA_TEST_FUNC_MASK
| S6_ALPHA_REF_MASK
);
188 dw
|= ((test
<< S6_ALPHA_TEST_FUNC_SHIFT
) |
189 (((GLuint
) refByte
) << S6_ALPHA_REF_SHIFT
));
190 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
191 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
192 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
196 /* This function makes sure that the proper enables are
197 * set for LogicOp, Independant Alpha Blend, and Blending.
198 * It needs to be called from numerous places where we
199 * could change the LogicOp or Independant Alpha Blend without subsequent
203 i915EvalLogicOpBlendState(struct gl_context
* ctx
)
205 struct i915_context
*i915
= I915_CONTEXT(ctx
);
208 dw0
= i915
->state
.Ctx
[I915_CTXREG_LIS5
];
209 dw1
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
211 if (ctx
->Color
.ColorLogicOpEnabled
) {
212 dw0
|= S5_LOGICOP_ENABLE
;
213 dw1
&= ~S6_CBUF_BLEND_ENABLE
;
216 dw0
&= ~S5_LOGICOP_ENABLE
;
218 if (ctx
->Color
.BlendEnabled
) {
219 dw1
|= S6_CBUF_BLEND_ENABLE
;
222 dw1
&= ~S6_CBUF_BLEND_ENABLE
;
225 if (dw0
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
] ||
226 dw1
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
227 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = dw0
;
228 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw1
;
230 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
235 i915BlendColor(struct gl_context
* ctx
, const GLfloat color
[4])
237 struct i915_context
*i915
= I915_CONTEXT(ctx
);
241 DBG("%s\n", __FUNCTION__
);
243 UNCLAMPED_FLOAT_TO_UBYTE(r
, color
[RCOMP
]);
244 UNCLAMPED_FLOAT_TO_UBYTE(g
, color
[GCOMP
]);
245 UNCLAMPED_FLOAT_TO_UBYTE(b
, color
[BCOMP
]);
246 UNCLAMPED_FLOAT_TO_UBYTE(a
, color
[ACOMP
]);
248 dw
= (a
<< 24) | (r
<< 16) | (g
<< 8) | b
;
249 if (dw
!= i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR1
]) {
250 i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR1
] = dw
;
251 I915_STATECHANGE(i915
, I915_UPLOAD_BLEND
);
256 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
257 #define SRC_BLND_FACT(f) ((f)<<S6_CBUF_SRC_BLEND_FACT_SHIFT)
258 #define DST_ABLND_FACT(f) ((f)<<IAB_DST_FACTOR_SHIFT)
259 #define SRC_ABLND_FACT(f) ((f)<<IAB_SRC_FACTOR_SHIFT)
264 translate_blend_equation(GLenum mode
)
268 return BLENDFUNC_ADD
;
270 return BLENDFUNC_MIN
;
272 return BLENDFUNC_MAX
;
273 case GL_FUNC_SUBTRACT
:
274 return BLENDFUNC_SUBTRACT
;
275 case GL_FUNC_REVERSE_SUBTRACT
:
276 return BLENDFUNC_REVERSE_SUBTRACT
;
283 i915UpdateBlendState(struct gl_context
* ctx
)
285 struct i915_context
*i915
= I915_CONTEXT(ctx
);
286 GLuint iab
= (i915
->state
.Blend
[I915_BLENDREG_IAB
] &
287 ~(IAB_SRC_FACTOR_MASK
|
288 IAB_DST_FACTOR_MASK
|
289 (BLENDFUNC_MASK
<< IAB_FUNC_SHIFT
) | IAB_ENABLE
));
291 GLuint lis6
= (i915
->state
.Ctx
[I915_CTXREG_LIS6
] &
292 ~(S6_CBUF_SRC_BLEND_FACT_MASK
|
293 S6_CBUF_DST_BLEND_FACT_MASK
| S6_CBUF_BLEND_FUNC_MASK
));
295 GLuint eqRGB
= ctx
->Color
.Blend
[0].EquationRGB
;
296 GLuint eqA
= ctx
->Color
.Blend
[0].EquationA
;
297 GLuint srcRGB
= ctx
->Color
.Blend
[0].SrcRGB
;
298 GLuint dstRGB
= ctx
->Color
.Blend
[0].DstRGB
;
299 GLuint srcA
= ctx
->Color
.Blend
[0].SrcA
;
300 GLuint dstA
= ctx
->Color
.Blend
[0].DstA
;
302 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
) {
303 srcRGB
= dstRGB
= GL_ONE
;
306 if (eqA
== GL_MIN
|| eqA
== GL_MAX
) {
307 srcA
= dstA
= GL_ONE
;
310 lis6
|= SRC_BLND_FACT(intel_translate_blend_factor(srcRGB
));
311 lis6
|= DST_BLND_FACT(intel_translate_blend_factor(dstRGB
));
312 lis6
|= translate_blend_equation(eqRGB
) << S6_CBUF_BLEND_FUNC_SHIFT
;
314 iab
|= SRC_ABLND_FACT(intel_translate_blend_factor(srcA
));
315 iab
|= DST_ABLND_FACT(intel_translate_blend_factor(dstA
));
316 iab
|= translate_blend_equation(eqA
) << IAB_FUNC_SHIFT
;
318 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
321 if (iab
!= i915
->state
.Blend
[I915_BLENDREG_IAB
]) {
322 i915
->state
.Blend
[I915_BLENDREG_IAB
] = iab
;
323 I915_STATECHANGE(i915
, I915_UPLOAD_BLEND
);
325 if (lis6
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
326 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = lis6
;
327 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
330 /* This will catch a logicop blend equation */
331 i915EvalLogicOpBlendState(ctx
);
336 i915BlendFuncSeparate(struct gl_context
* ctx
, GLenum srcRGB
,
337 GLenum dstRGB
, GLenum srcA
, GLenum dstA
)
339 i915UpdateBlendState(ctx
);
344 i915BlendEquationSeparate(struct gl_context
* ctx
, GLenum eqRGB
, GLenum eqA
)
346 i915UpdateBlendState(ctx
);
351 i915DepthFunc(struct gl_context
* ctx
, GLenum func
)
353 struct i915_context
*i915
= I915_CONTEXT(ctx
);
354 int test
= intel_translate_compare_func(func
);
357 DBG("%s\n", __FUNCTION__
);
359 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
360 dw
&= ~S6_DEPTH_TEST_FUNC_MASK
;
361 dw
|= test
<< S6_DEPTH_TEST_FUNC_SHIFT
;
362 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
363 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
364 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
369 i915DepthMask(struct gl_context
* ctx
, GLboolean flag
)
371 struct i915_context
*i915
= I915_CONTEXT(ctx
);
374 DBG("%s flag (%d)\n", __FUNCTION__
, flag
);
376 if (!ctx
->DrawBuffer
|| !ctx
->DrawBuffer
->Visual
.depthBits
)
379 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
380 if (flag
&& ctx
->Depth
.Test
)
381 dw
|= S6_DEPTH_WRITE_ENABLE
;
383 dw
&= ~S6_DEPTH_WRITE_ENABLE
;
384 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
385 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
386 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
393 * Update the viewport transformation matrix. Depends on:
394 * - viewport pos/size
396 * - window pos/size or FBO size
399 intelCalcViewport(struct gl_context
* ctx
)
401 struct intel_context
*intel
= intel_context(ctx
);
403 if (ctx
->DrawBuffer
->Name
== 0) {
404 _math_matrix_viewport(&intel
->ViewportMatrix
,
406 ctx
->DrawBuffer
->Height
- ctx
->Viewport
.Y
,
408 -ctx
->Viewport
.Height
,
413 _math_matrix_viewport(&intel
->ViewportMatrix
,
417 ctx
->Viewport
.Height
,
425 /** Called from ctx->Driver.Viewport() */
427 i915Viewport(struct gl_context
* ctx
,
428 GLint x
, GLint y
, GLsizei width
, GLsizei height
)
430 intelCalcViewport(ctx
);
434 /** Called from ctx->Driver.DepthRange() */
436 i915DepthRange(struct gl_context
* ctx
, GLclampd nearval
, GLclampd farval
)
438 intelCalcViewport(ctx
);
442 /* =============================================================
445 * The i915 supports a 4x4 stipple natively, GL wants 32x32.
446 * Fortunately stipple is usually a repeating pattern.
449 i915PolygonStipple(struct gl_context
* ctx
, const GLubyte
* mask
)
451 struct i915_context
*i915
= I915_CONTEXT(ctx
);
455 int active
= (ctx
->Polygon
.StippleFlag
&&
456 i915
->intel
.reduced_primitive
== GL_TRIANGLES
);
460 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
461 i915
->state
.Stipple
[I915_STPREG_ST1
] &= ~ST1_ENABLE
;
464 /* Use the already unpacked stipple data from the context rather than the
465 * uninterpreted mask passed in.
467 mask
= (const GLubyte
*)ctx
->PolygonStipple
;
470 p
[0] = mask
[12] & 0xf;
472 p
[1] = mask
[8] & 0xf;
474 p
[2] = mask
[4] & 0xf;
476 p
[3] = mask
[0] & 0xf;
479 for (k
= 0; k
< 8; k
++)
480 for (j
= 3; j
>= 0; j
--)
481 for (i
= 0; i
< 4; i
++, m
++)
483 i915
->intel
.hw_stipple
= 0;
487 newMask
= (((p
[0] & 0xf) << 0) |
488 ((p
[1] & 0xf) << 4) |
489 ((p
[2] & 0xf) << 8) | ((p
[3] & 0xf) << 12));
492 if (newMask
== 0xffff || newMask
== 0x0) {
493 /* this is needed to make conform pass */
494 i915
->intel
.hw_stipple
= 0;
498 i915
->state
.Stipple
[I915_STPREG_ST1
] &= ~0xffff;
499 i915
->state
.Stipple
[I915_STPREG_ST1
] |= newMask
;
500 i915
->intel
.hw_stipple
= 1;
503 i915
->state
.Stipple
[I915_STPREG_ST1
] |= ST1_ENABLE
;
507 /* =============================================================
511 i915Scissor(struct gl_context
* ctx
, GLint x
, GLint y
, GLsizei w
, GLsizei h
)
513 struct i915_context
*i915
= I915_CONTEXT(ctx
);
516 if (!ctx
->DrawBuffer
)
519 DBG("%s %d,%d %dx%d\n", __FUNCTION__
, x
, y
, w
, h
);
521 if (ctx
->DrawBuffer
->Name
== 0) {
523 y1
= ctx
->DrawBuffer
->Height
- (y
+ h
);
526 DBG("%s %d..%d,%d..%d (inverted)\n", __FUNCTION__
, x1
, x2
, y1
, y2
);
529 /* FBO - not inverted
535 DBG("%s %d..%d,%d..%d (not inverted)\n", __FUNCTION__
, x1
, x2
, y1
, y2
);
538 x1
= CLAMP(x1
, 0, ctx
->DrawBuffer
->Width
- 1);
539 y1
= CLAMP(y1
, 0, ctx
->DrawBuffer
->Height
- 1);
540 x2
= CLAMP(x2
, 0, ctx
->DrawBuffer
->Width
- 1);
541 y2
= CLAMP(y2
, 0, ctx
->DrawBuffer
->Height
- 1);
543 DBG("%s %d..%d,%d..%d (clamped)\n", __FUNCTION__
, x1
, x2
, y1
, y2
);
545 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
546 i915
->state
.Buffer
[I915_DESTREG_SR1
] = (y1
<< 16) | (x1
& 0xffff);
547 i915
->state
.Buffer
[I915_DESTREG_SR2
] = (y2
<< 16) | (x2
& 0xffff);
551 i915LogicOp(struct gl_context
* ctx
, GLenum opcode
)
553 struct i915_context
*i915
= I915_CONTEXT(ctx
);
554 int tmp
= intel_translate_logic_op(opcode
);
556 DBG("%s\n", __FUNCTION__
);
558 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
559 i915
->state
.Ctx
[I915_CTXREG_STATE4
] &= ~LOGICOP_MASK
;
560 i915
->state
.Ctx
[I915_CTXREG_STATE4
] |= LOGIC_OP_FUNC(tmp
);
566 i915CullFaceFrontFace(struct gl_context
* ctx
, GLenum unused
)
568 struct i915_context
*i915
= I915_CONTEXT(ctx
);
571 DBG("%s %d\n", __FUNCTION__
,
572 ctx
->DrawBuffer
? ctx
->DrawBuffer
->Name
: 0);
574 if (!ctx
->Polygon
.CullFlag
) {
575 mode
= S4_CULLMODE_NONE
;
577 else if (ctx
->Polygon
.CullFaceMode
!= GL_FRONT_AND_BACK
) {
578 mode
= S4_CULLMODE_CW
;
580 if (ctx
->DrawBuffer
&& ctx
->DrawBuffer
->Name
!= 0)
581 mode
^= (S4_CULLMODE_CW
^ S4_CULLMODE_CCW
);
582 if (ctx
->Polygon
.CullFaceMode
== GL_FRONT
)
583 mode
^= (S4_CULLMODE_CW
^ S4_CULLMODE_CCW
);
584 if (ctx
->Polygon
.FrontFace
!= GL_CCW
)
585 mode
^= (S4_CULLMODE_CW
^ S4_CULLMODE_CCW
);
588 mode
= S4_CULLMODE_BOTH
;
591 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
592 dw
&= ~S4_CULLMODE_MASK
;
594 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
595 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = dw
;
596 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
601 i915LineWidth(struct gl_context
* ctx
, GLfloat widthf
)
603 struct i915_context
*i915
= I915_CONTEXT(ctx
);
604 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
] & ~S4_LINE_WIDTH_MASK
;
607 DBG("%s\n", __FUNCTION__
);
609 width
= (int) (widthf
* 2);
610 width
= CLAMP(width
, 1, 0xf);
611 lis4
|= width
<< S4_LINE_WIDTH_SHIFT
;
613 if (lis4
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
614 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
615 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = lis4
;
620 i915PointSize(struct gl_context
* ctx
, GLfloat size
)
622 struct i915_context
*i915
= I915_CONTEXT(ctx
);
623 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
] & ~S4_POINT_WIDTH_MASK
;
624 GLint point_size
= (int) round(size
);
626 DBG("%s\n", __FUNCTION__
);
628 point_size
= CLAMP(point_size
, 1, 255);
629 lis4
|= point_size
<< S4_POINT_WIDTH_SHIFT
;
631 if (lis4
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
632 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
633 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = lis4
;
639 i915PointParameterfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
*params
)
641 struct i915_context
*i915
= I915_CONTEXT(ctx
);
644 case GL_POINT_SPRITE_COORD_ORIGIN
:
645 /* This could be supported, but it would require modifying the fragment
646 * program to invert the y component of the texture coordinate by
647 * inserting a 'SUB tc.y, {1.0}.xxxx, tc' instruction.
649 FALLBACK(&i915
->intel
, I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN
,
650 (params
[0] != GL_UPPER_LEFT
));
656 /* =============================================================
661 i915ColorMask(struct gl_context
* ctx
,
662 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
)
664 struct i915_context
*i915
= I915_CONTEXT(ctx
);
665 GLuint tmp
= i915
->state
.Ctx
[I915_CTXREG_LIS5
] & ~S5_WRITEDISABLE_MASK
;
667 DBG("%s r(%d) g(%d) b(%d) a(%d)\n", __FUNCTION__
, r
, g
, b
,
671 tmp
|= S5_WRITEDISABLE_RED
;
673 tmp
|= S5_WRITEDISABLE_GREEN
;
675 tmp
|= S5_WRITEDISABLE_BLUE
;
677 tmp
|= S5_WRITEDISABLE_ALPHA
;
679 if (tmp
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
]) {
680 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
681 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = tmp
;
686 update_specular(struct gl_context
* ctx
)
688 /* A hack to trigger the rebuild of the fragment program.
690 intel_context(ctx
)->NewGLState
|= _NEW_TEXTURE
;
694 i915LightModelfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
)
696 DBG("%s\n", __FUNCTION__
);
698 if (pname
== GL_LIGHT_MODEL_COLOR_CONTROL
) {
699 update_specular(ctx
);
704 i915ShadeModel(struct gl_context
* ctx
, GLenum mode
)
706 struct i915_context
*i915
= I915_CONTEXT(ctx
);
707 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
709 if (mode
== GL_SMOOTH
) {
710 i915
->state
.Ctx
[I915_CTXREG_LIS4
] &= ~(S4_FLATSHADE_ALPHA
|
712 S4_FLATSHADE_SPECULAR
);
715 i915
->state
.Ctx
[I915_CTXREG_LIS4
] |= (S4_FLATSHADE_ALPHA
|
717 S4_FLATSHADE_SPECULAR
);
721 /* =============================================================
724 * This empty function remains because _mesa_init_driver_state calls
725 * dd_function_table::Fogfv unconditionally. We have to have some function
726 * there so that it doesn't try to call a NULL pointer.
729 i915Fogfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
)
736 /* =============================================================
740 i915Enable(struct gl_context
* ctx
, GLenum cap
, GLboolean state
)
742 struct i915_context
*i915
= I915_CONTEXT(ctx
);
751 update_specular(ctx
);
755 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
757 dw
|= S6_ALPHA_TEST_ENABLE
;
759 dw
&= ~S6_ALPHA_TEST_ENABLE
;
760 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
761 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
762 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
767 i915EvalLogicOpBlendState(ctx
);
770 case GL_COLOR_LOGIC_OP
:
771 i915EvalLogicOpBlendState(ctx
);
773 /* Logicop doesn't seem to work at 16bpp:
775 if (ctx
->Visual
.rgbBits
== 16)
776 FALLBACK(&i915
->intel
, I915_FALLBACK_LOGICOP
, state
);
779 case GL_FRAGMENT_PROGRAM_ARB
:
783 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS5
];
785 dw
|= S5_COLOR_DITHER_ENABLE
;
787 dw
&= ~S5_COLOR_DITHER_ENABLE
;
788 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
]) {
789 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = dw
;
790 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
795 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
797 if (!ctx
->DrawBuffer
|| !ctx
->DrawBuffer
->Visual
.depthBits
)
801 dw
|= S6_DEPTH_TEST_ENABLE
;
803 dw
&= ~S6_DEPTH_TEST_ENABLE
;
804 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
805 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
806 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
809 i915DepthMask(ctx
, ctx
->Depth
.Mask
);
812 case GL_SCISSOR_TEST
:
813 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
815 i915
->state
.Buffer
[I915_DESTREG_SENABLE
] =
816 (_3DSTATE_SCISSOR_ENABLE_CMD
| ENABLE_SCISSOR_RECT
);
818 i915
->state
.Buffer
[I915_DESTREG_SENABLE
] =
819 (_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
823 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
825 dw
|= S4_LINE_ANTIALIAS_ENABLE
;
827 dw
&= ~S4_LINE_ANTIALIAS_ENABLE
;
828 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
829 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = dw
;
830 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
835 i915CullFaceFrontFace(ctx
, 0);
838 case GL_STENCIL_TEST
:
839 if (!ctx
->DrawBuffer
|| !ctx
->DrawBuffer
->Visual
.stencilBits
)
842 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS5
];
844 dw
|= (S5_STENCIL_TEST_ENABLE
| S5_STENCIL_WRITE_ENABLE
);
846 dw
&= ~(S5_STENCIL_TEST_ENABLE
| S5_STENCIL_WRITE_ENABLE
);
847 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
]) {
848 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = dw
;
849 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
853 case GL_POLYGON_STIPPLE
:
854 /* The stipple command worked on my 855GM box, but not my 845G.
855 * I'll do more testing later to find out exactly which hardware
856 * supports it. Disabled for now.
858 if (i915
->intel
.hw_stipple
&&
859 i915
->intel
.reduced_primitive
== GL_TRIANGLES
) {
860 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
862 i915
->state
.Stipple
[I915_STPREG_ST1
] |= ST1_ENABLE
;
864 i915
->state
.Stipple
[I915_STPREG_ST1
] &= ~ST1_ENABLE
;
868 case GL_POLYGON_SMOOTH
:
871 case GL_POINT_SPRITE
:
872 /* This state change is handled in i915_reduced_primitive_state because
873 * the hardware bit should only be set when rendering points.
875 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
877 dw
|= S4_SPRITE_POINT_ENABLE
;
879 dw
&= ~S4_SPRITE_POINT_ENABLE
;
880 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
881 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = dw
;
882 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
886 case GL_POINT_SMOOTH
:
896 i915_init_packets(struct i915_context
*i915
)
899 memset(&i915
->state
, 0, sizeof(i915
->state
));
903 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
904 I915_STATECHANGE(i915
, I915_UPLOAD_BLEND
);
905 /* Probably don't want to upload all this stuff every time one
908 i915
->state
.Ctx
[I915_CTXREG_LI
] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1
|
911 I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
912 i915
->state
.Ctx
[I915_CTXREG_LIS2
] = 0;
913 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = 0;
914 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = 0;
916 if (i915
->intel
.ctx
.Visual
.rgbBits
== 16)
917 i915
->state
.Ctx
[I915_CTXREG_LIS5
] |= S5_COLOR_DITHER_ENABLE
;
920 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = (S6_COLOR_WRITE_ENABLE
|
921 (2 << S6_TRISTRIP_PV_SHIFT
));
923 i915
->state
.Ctx
[I915_CTXREG_STATE4
] = (_3DSTATE_MODES_4_CMD
|
924 ENABLE_LOGIC_OP_FUNC
|
925 LOGIC_OP_FUNC(LOGICOP_COPY
) |
926 ENABLE_STENCIL_TEST_MASK
|
927 STENCIL_TEST_MASK(0xff) |
928 ENABLE_STENCIL_WRITE_MASK
|
929 STENCIL_WRITE_MASK(0xff));
931 i915
->state
.Blend
[I915_BLENDREG_IAB
] =
932 (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD
| IAB_MODIFY_ENABLE
|
933 IAB_MODIFY_FUNC
| IAB_MODIFY_SRC_FACTOR
| IAB_MODIFY_DST_FACTOR
);
935 i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR0
] =
936 _3DSTATE_CONST_BLEND_COLOR_CMD
;
937 i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR1
] = 0;
939 i915
->state
.Ctx
[I915_CTXREG_BF_STENCIL_MASKS
] =
940 _3DSTATE_BACKFACE_STENCIL_MASKS
|
941 BFM_ENABLE_STENCIL_TEST_MASK
|
942 BFM_ENABLE_STENCIL_WRITE_MASK
|
943 (0xff << BFM_STENCIL_WRITE_MASK_SHIFT
) |
944 (0xff << BFM_STENCIL_TEST_MASK_SHIFT
);
945 i915
->state
.Ctx
[I915_CTXREG_BF_STENCIL_OPS
] =
946 _3DSTATE_BACKFACE_STENCIL_OPS
|
947 BFO_ENABLE_STENCIL_REF
|
948 BFO_ENABLE_STENCIL_FUNCS
|
949 BFO_ENABLE_STENCIL_TWO_SIDE
;
953 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
954 i915
->state
.Stipple
[I915_STPREG_ST0
] = _3DSTATE_STIPPLE
;
958 i915
->state
.Buffer
[I915_DESTREG_DV0
] = _3DSTATE_DST_BUF_VARS_CMD
;
961 i915
->state
.Buffer
[I915_DESTREG_SENABLE
] =
962 (_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
963 i915
->state
.Buffer
[I915_DESTREG_SR0
] = _3DSTATE_SCISSOR_RECT_0_CMD
;
964 i915
->state
.Buffer
[I915_DESTREG_SR1
] = 0;
965 i915
->state
.Buffer
[I915_DESTREG_SR2
] = 0;
968 i915
->state
.RasterRules
[I915_RASTER_RULES
] = _3DSTATE_RASTER_RULES_CMD
|
969 ENABLE_POINT_RASTER_RULE
|
970 OGL_POINT_RASTER_RULE
|
971 ENABLE_LINE_STRIP_PROVOKE_VRTX
|
972 ENABLE_TRI_FAN_PROVOKE_VRTX
|
973 LINE_STRIP_PROVOKE_VRTX(1) |
974 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D
| TEXKILL_4D
;
978 I915_STATECHANGE(i915
, I915_UPLOAD_DEFAULTS
);
979 i915
->state
.Default
[I915_DEFREG_C0
] = _3DSTATE_DEFAULT_DIFFUSE
;
980 i915
->state
.Default
[I915_DEFREG_C1
] = 0;
981 i915
->state
.Default
[I915_DEFREG_S0
] = _3DSTATE_DEFAULT_SPECULAR
;
982 i915
->state
.Default
[I915_DEFREG_S1
] = 0;
983 i915
->state
.Default
[I915_DEFREG_Z0
] = _3DSTATE_DEFAULT_Z
;
984 i915
->state
.Default
[I915_DEFREG_Z1
] = 0;
989 /* These will be emitted every at the head of every buffer, unless
990 * we get hardware contexts working.
992 i915
->state
.active
= (I915_UPLOAD_PROGRAM
|
993 I915_UPLOAD_STIPPLE
|
996 I915_UPLOAD_BUFFERS
|
997 I915_UPLOAD_INVARIENT
|
998 I915_UPLOAD_RASTER_RULES
);
1002 i915_update_provoking_vertex(struct gl_context
* ctx
)
1004 struct i915_context
*i915
= I915_CONTEXT(ctx
);
1006 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
1007 i915
->state
.Ctx
[I915_CTXREG_LIS6
] &= ~(S6_TRISTRIP_PV_MASK
);
1009 I915_STATECHANGE(i915
, I915_UPLOAD_RASTER_RULES
);
1010 i915
->state
.RasterRules
[I915_RASTER_RULES
] &= ~(LINE_STRIP_PROVOKE_VRTX_MASK
|
1011 TRI_FAN_PROVOKE_VRTX_MASK
);
1014 if (ctx
->Light
.ProvokingVertex
== GL_LAST_VERTEX_CONVENTION
) {
1015 i915
->state
.RasterRules
[I915_RASTER_RULES
] |= (LINE_STRIP_PROVOKE_VRTX(1) |
1016 TRI_FAN_PROVOKE_VRTX(2));
1017 i915
->state
.Ctx
[I915_CTXREG_LIS6
] |= (2 << S6_TRISTRIP_PV_SHIFT
);
1019 i915
->state
.RasterRules
[I915_RASTER_RULES
] |= (LINE_STRIP_PROVOKE_VRTX(0) |
1020 TRI_FAN_PROVOKE_VRTX(1));
1021 i915
->state
.Ctx
[I915_CTXREG_LIS6
] |= (0 << S6_TRISTRIP_PV_SHIFT
);
1026 i915InitStateFunctions(struct dd_function_table
*functions
)
1028 functions
->AlphaFunc
= i915AlphaFunc
;
1029 functions
->BlendColor
= i915BlendColor
;
1030 functions
->BlendEquationSeparate
= i915BlendEquationSeparate
;
1031 functions
->BlendFuncSeparate
= i915BlendFuncSeparate
;
1032 functions
->ColorMask
= i915ColorMask
;
1033 functions
->CullFace
= i915CullFaceFrontFace
;
1034 functions
->DepthFunc
= i915DepthFunc
;
1035 functions
->DepthMask
= i915DepthMask
;
1036 functions
->Enable
= i915Enable
;
1037 functions
->Fogfv
= i915Fogfv
;
1038 functions
->FrontFace
= i915CullFaceFrontFace
;
1039 functions
->LightModelfv
= i915LightModelfv
;
1040 functions
->LineWidth
= i915LineWidth
;
1041 functions
->LogicOpcode
= i915LogicOp
;
1042 functions
->PointSize
= i915PointSize
;
1043 functions
->PointParameterfv
= i915PointParameterfv
;
1044 functions
->PolygonStipple
= i915PolygonStipple
;
1045 functions
->Scissor
= i915Scissor
;
1046 functions
->ShadeModel
= i915ShadeModel
;
1047 functions
->StencilFuncSeparate
= i915StencilFuncSeparate
;
1048 functions
->StencilMaskSeparate
= i915StencilMaskSeparate
;
1049 functions
->StencilOpSeparate
= i915StencilOpSeparate
;
1050 functions
->DepthRange
= i915DepthRange
;
1051 functions
->Viewport
= i915Viewport
;
1056 i915InitState(struct i915_context
*i915
)
1058 struct gl_context
*ctx
= &i915
->intel
.ctx
;
1060 i915_init_packets(i915
);
1062 _mesa_init_driver_state(ctx
);