mesa: Eliminate parameters to dd_function_table::Scissor
[mesa.git] / src / mesa / drivers / dri / i915 / i915_state.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "main/glheader.h"
30 #include "main/context.h"
31 #include "main/macros.h"
32 #include "main/enums.h"
33 #include "main/fbobject.h"
34 #include "main/dd.h"
35 #include "main/state.h"
36 #include "main/stencil.h"
37 #include "tnl/tnl.h"
38 #include "tnl/t_context.h"
39
40 #include "drivers/common/driverfuncs.h"
41
42 #include "intel_fbo.h"
43 #include "intel_screen.h"
44 #include "intel_batchbuffer.h"
45 #include "intel_buffers.h"
46
47 #include "i915_context.h"
48 #include "i915_reg.h"
49
50 #define FILE_DEBUG_FLAG DEBUG_STATE
51
52 void
53 i915_update_stencil(struct gl_context * ctx)
54 {
55 struct i915_context *i915 = I915_CONTEXT(ctx);
56 GLuint front_ref, front_writemask, front_mask;
57 GLenum front_func, front_fail, front_pass_z_fail, front_pass_z_pass;
58 GLuint back_ref, back_writemask, back_mask;
59 GLenum back_func, back_fail, back_pass_z_fail, back_pass_z_pass;
60 GLuint dirty = 0;
61
62 /* The 915 considers CW to be "front" for two-sided stencil, so choose
63 * appropriately.
64 */
65 /* _NEW_POLYGON | _NEW_STENCIL */
66 if (ctx->Polygon.FrontFace == GL_CW) {
67 front_ref = _mesa_get_stencil_ref(ctx, 0);
68 front_mask = ctx->Stencil.ValueMask[0];
69 front_writemask = ctx->Stencil.WriteMask[0];
70 front_func = ctx->Stencil.Function[0];
71 front_fail = ctx->Stencil.FailFunc[0];
72 front_pass_z_fail = ctx->Stencil.ZFailFunc[0];
73 front_pass_z_pass = ctx->Stencil.ZPassFunc[0];
74 back_ref = _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
75 back_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
76 back_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
77 back_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
78 back_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
79 back_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
80 back_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
81 } else {
82 front_ref = _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
83 front_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
84 front_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
85 front_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
86 front_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
87 front_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
88 front_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
89 back_ref = _mesa_get_stencil_ref(ctx, 0);
90 back_mask = ctx->Stencil.ValueMask[0];
91 back_writemask = ctx->Stencil.WriteMask[0];
92 back_func = ctx->Stencil.Function[0];
93 back_fail = ctx->Stencil.FailFunc[0];
94 back_pass_z_fail = ctx->Stencil.ZFailFunc[0];
95 back_pass_z_pass = ctx->Stencil.ZPassFunc[0];
96 }
97 #define set_ctx_bits(reg, mask, set) do{ \
98 GLuint dw = i915->state.Ctx[reg]; \
99 dw &= ~(mask); \
100 dw |= (set); \
101 dirty |= dw != i915->state.Ctx[reg]; \
102 i915->state.Ctx[reg] = dw; \
103 } while(0)
104
105 /* Set front state. */
106 set_ctx_bits(I915_CTXREG_STATE4,
107 MODE4_ENABLE_STENCIL_TEST_MASK |
108 MODE4_ENABLE_STENCIL_WRITE_MASK,
109 ENABLE_STENCIL_TEST_MASK |
110 ENABLE_STENCIL_WRITE_MASK |
111 STENCIL_TEST_MASK(front_mask) |
112 STENCIL_WRITE_MASK(front_writemask));
113
114 set_ctx_bits(I915_CTXREG_LIS5,
115 S5_STENCIL_REF_MASK |
116 S5_STENCIL_TEST_FUNC_MASK |
117 S5_STENCIL_FAIL_MASK |
118 S5_STENCIL_PASS_Z_FAIL_MASK |
119 S5_STENCIL_PASS_Z_PASS_MASK,
120 (front_ref << S5_STENCIL_REF_SHIFT) |
121 (intel_translate_compare_func(front_func) << S5_STENCIL_TEST_FUNC_SHIFT) |
122 (intel_translate_stencil_op(front_fail) << S5_STENCIL_FAIL_SHIFT) |
123 (intel_translate_stencil_op(front_pass_z_fail) <<
124 S5_STENCIL_PASS_Z_FAIL_SHIFT) |
125 (intel_translate_stencil_op(front_pass_z_pass) <<
126 S5_STENCIL_PASS_Z_PASS_SHIFT));
127
128 /* Set back state if different from front. */
129 if (ctx->Stencil._TestTwoSide) {
130 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS,
131 BFO_STENCIL_REF_MASK |
132 BFO_STENCIL_TEST_MASK |
133 BFO_STENCIL_FAIL_MASK |
134 BFO_STENCIL_PASS_Z_FAIL_MASK |
135 BFO_STENCIL_PASS_Z_PASS_MASK,
136 BFO_STENCIL_TWO_SIDE |
137 (back_ref << BFO_STENCIL_REF_SHIFT) |
138 (intel_translate_compare_func(back_func) << BFO_STENCIL_TEST_SHIFT) |
139 (intel_translate_stencil_op(back_fail) << BFO_STENCIL_FAIL_SHIFT) |
140 (intel_translate_stencil_op(back_pass_z_fail) <<
141 BFO_STENCIL_PASS_Z_FAIL_SHIFT) |
142 (intel_translate_stencil_op(back_pass_z_pass) <<
143 BFO_STENCIL_PASS_Z_PASS_SHIFT));
144
145 set_ctx_bits(I915_CTXREG_BF_STENCIL_MASKS,
146 BFM_STENCIL_TEST_MASK_MASK |
147 BFM_STENCIL_WRITE_MASK_MASK,
148 BFM_STENCIL_TEST_MASK(back_mask) |
149 BFM_STENCIL_WRITE_MASK(back_writemask));
150 } else {
151 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS,
152 BFO_STENCIL_TWO_SIDE, 0);
153 }
154
155 #undef set_ctx_bits
156
157 if (dirty)
158 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
159 }
160
161 static void
162 i915StencilFuncSeparate(struct gl_context * ctx, GLenum face, GLenum func, GLint ref,
163 GLuint mask)
164 {
165 }
166
167 static void
168 i915StencilMaskSeparate(struct gl_context * ctx, GLenum face, GLuint mask)
169 {
170 }
171
172 static void
173 i915StencilOpSeparate(struct gl_context * ctx, GLenum face, GLenum fail, GLenum zfail,
174 GLenum zpass)
175 {
176 }
177
178 static void
179 i915AlphaFunc(struct gl_context * ctx, GLenum func, GLfloat ref)
180 {
181 struct i915_context *i915 = I915_CONTEXT(ctx);
182 int test = intel_translate_compare_func(func);
183 GLubyte refByte;
184 GLuint dw;
185
186 UNCLAMPED_FLOAT_TO_UBYTE(refByte, ref);
187
188 dw = i915->state.Ctx[I915_CTXREG_LIS6];
189 dw &= ~(S6_ALPHA_TEST_FUNC_MASK | S6_ALPHA_REF_MASK);
190 dw |= ((test << S6_ALPHA_TEST_FUNC_SHIFT) |
191 (((GLuint) refByte) << S6_ALPHA_REF_SHIFT));
192 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
193 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
194 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
195 }
196 }
197
198 /* This function makes sure that the proper enables are
199 * set for LogicOp, Independant Alpha Blend, and Blending.
200 * It needs to be called from numerous places where we
201 * could change the LogicOp or Independant Alpha Blend without subsequent
202 * calls to glEnable.
203 */
204 static void
205 i915EvalLogicOpBlendState(struct gl_context * ctx)
206 {
207 struct i915_context *i915 = I915_CONTEXT(ctx);
208 GLuint dw0, dw1;
209
210 dw0 = i915->state.Ctx[I915_CTXREG_LIS5];
211 dw1 = i915->state.Ctx[I915_CTXREG_LIS6];
212
213 if (ctx->Color.ColorLogicOpEnabled) {
214 dw0 |= S5_LOGICOP_ENABLE;
215 dw1 &= ~S6_CBUF_BLEND_ENABLE;
216 }
217 else {
218 dw0 &= ~S5_LOGICOP_ENABLE;
219
220 if (ctx->Color.BlendEnabled) {
221 dw1 |= S6_CBUF_BLEND_ENABLE;
222 }
223 else {
224 dw1 &= ~S6_CBUF_BLEND_ENABLE;
225 }
226 }
227 if (dw0 != i915->state.Ctx[I915_CTXREG_LIS5] ||
228 dw1 != i915->state.Ctx[I915_CTXREG_LIS6]) {
229 i915->state.Ctx[I915_CTXREG_LIS5] = dw0;
230 i915->state.Ctx[I915_CTXREG_LIS6] = dw1;
231
232 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
233 }
234 }
235
236 static void
237 i915BlendColor(struct gl_context * ctx, const GLfloat color[4])
238 {
239 struct i915_context *i915 = I915_CONTEXT(ctx);
240 GLubyte r, g, b, a;
241 GLuint dw;
242
243 DBG("%s\n", __FUNCTION__);
244
245 UNCLAMPED_FLOAT_TO_UBYTE(r, color[RCOMP]);
246 UNCLAMPED_FLOAT_TO_UBYTE(g, color[GCOMP]);
247 UNCLAMPED_FLOAT_TO_UBYTE(b, color[BCOMP]);
248 UNCLAMPED_FLOAT_TO_UBYTE(a, color[ACOMP]);
249
250 dw = (a << 24) | (r << 16) | (g << 8) | b;
251 if (dw != i915->state.Blend[I915_BLENDREG_BLENDCOLOR1]) {
252 i915->state.Blend[I915_BLENDREG_BLENDCOLOR1] = dw;
253 I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
254 }
255 }
256
257
258 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
259 #define SRC_BLND_FACT(f) ((f)<<S6_CBUF_SRC_BLEND_FACT_SHIFT)
260 #define DST_ABLND_FACT(f) ((f)<<IAB_DST_FACTOR_SHIFT)
261 #define SRC_ABLND_FACT(f) ((f)<<IAB_SRC_FACTOR_SHIFT)
262
263
264
265 static GLuint
266 translate_blend_equation(GLenum mode)
267 {
268 switch (mode) {
269 case GL_FUNC_ADD:
270 return BLENDFUNC_ADD;
271 case GL_MIN:
272 return BLENDFUNC_MIN;
273 case GL_MAX:
274 return BLENDFUNC_MAX;
275 case GL_FUNC_SUBTRACT:
276 return BLENDFUNC_SUBTRACT;
277 case GL_FUNC_REVERSE_SUBTRACT:
278 return BLENDFUNC_REVERSE_SUBTRACT;
279 default:
280 return 0;
281 }
282 }
283
284 static void
285 i915UpdateBlendState(struct gl_context * ctx)
286 {
287 struct i915_context *i915 = I915_CONTEXT(ctx);
288 GLuint iab = (i915->state.Blend[I915_BLENDREG_IAB] &
289 ~(IAB_SRC_FACTOR_MASK |
290 IAB_DST_FACTOR_MASK |
291 (BLENDFUNC_MASK << IAB_FUNC_SHIFT) | IAB_ENABLE));
292
293 GLuint lis6 = (i915->state.Ctx[I915_CTXREG_LIS6] &
294 ~(S6_CBUF_SRC_BLEND_FACT_MASK |
295 S6_CBUF_DST_BLEND_FACT_MASK | S6_CBUF_BLEND_FUNC_MASK));
296
297 GLuint eqRGB = ctx->Color.Blend[0].EquationRGB;
298 GLuint eqA = ctx->Color.Blend[0].EquationA;
299 GLuint srcRGB = ctx->Color.Blend[0].SrcRGB;
300 GLuint dstRGB = ctx->Color.Blend[0].DstRGB;
301 GLuint srcA = ctx->Color.Blend[0].SrcA;
302 GLuint dstA = ctx->Color.Blend[0].DstA;
303
304 if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
305 srcRGB = dstRGB = GL_ONE;
306 }
307
308 if (eqA == GL_MIN || eqA == GL_MAX) {
309 srcA = dstA = GL_ONE;
310 }
311
312 lis6 |= SRC_BLND_FACT(intel_translate_blend_factor(srcRGB));
313 lis6 |= DST_BLND_FACT(intel_translate_blend_factor(dstRGB));
314 lis6 |= translate_blend_equation(eqRGB) << S6_CBUF_BLEND_FUNC_SHIFT;
315
316 iab |= SRC_ABLND_FACT(intel_translate_blend_factor(srcA));
317 iab |= DST_ABLND_FACT(intel_translate_blend_factor(dstA));
318 iab |= translate_blend_equation(eqA) << IAB_FUNC_SHIFT;
319
320 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB)
321 iab |= IAB_ENABLE;
322
323 if (iab != i915->state.Blend[I915_BLENDREG_IAB]) {
324 i915->state.Blend[I915_BLENDREG_IAB] = iab;
325 I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
326 }
327 if (lis6 != i915->state.Ctx[I915_CTXREG_LIS6]) {
328 i915->state.Ctx[I915_CTXREG_LIS6] = lis6;
329 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
330 }
331
332 /* This will catch a logicop blend equation */
333 i915EvalLogicOpBlendState(ctx);
334 }
335
336
337 static void
338 i915BlendFuncSeparate(struct gl_context * ctx, GLenum srcRGB,
339 GLenum dstRGB, GLenum srcA, GLenum dstA)
340 {
341 i915UpdateBlendState(ctx);
342 }
343
344
345 static void
346 i915BlendEquationSeparate(struct gl_context * ctx, GLenum eqRGB, GLenum eqA)
347 {
348 i915UpdateBlendState(ctx);
349 }
350
351
352 static void
353 i915DepthFunc(struct gl_context * ctx, GLenum func)
354 {
355 struct i915_context *i915 = I915_CONTEXT(ctx);
356 int test = intel_translate_compare_func(func);
357 GLuint dw;
358
359 DBG("%s\n", __FUNCTION__);
360
361 dw = i915->state.Ctx[I915_CTXREG_LIS6];
362 dw &= ~S6_DEPTH_TEST_FUNC_MASK;
363 dw |= test << S6_DEPTH_TEST_FUNC_SHIFT;
364 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
365 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
366 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
367 }
368 }
369
370 static void
371 i915DepthMask(struct gl_context * ctx, GLboolean flag)
372 {
373 struct i915_context *i915 = I915_CONTEXT(ctx);
374 GLuint dw;
375
376 DBG("%s flag (%d)\n", __FUNCTION__, flag);
377
378 if (!ctx->DrawBuffer || !ctx->DrawBuffer->Visual.depthBits)
379 flag = false;
380
381 dw = i915->state.Ctx[I915_CTXREG_LIS6];
382 if (flag && ctx->Depth.Test)
383 dw |= S6_DEPTH_WRITE_ENABLE;
384 else
385 dw &= ~S6_DEPTH_WRITE_ENABLE;
386 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
387 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
388 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
389 }
390 }
391
392
393
394 /**
395 * Update the viewport transformation matrix. Depends on:
396 * - viewport pos/size
397 * - depthrange
398 * - window pos/size or FBO size
399 */
400 void
401 intelCalcViewport(struct gl_context * ctx)
402 {
403 struct intel_context *intel = intel_context(ctx);
404
405 if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
406 _math_matrix_viewport(&intel->ViewportMatrix,
407 ctx->Viewport.X,
408 ctx->DrawBuffer->Height - ctx->Viewport.Y,
409 ctx->Viewport.Width,
410 -ctx->Viewport.Height,
411 ctx->Viewport.Near,
412 ctx->Viewport.Far,
413 1.0);
414 } else {
415 _math_matrix_viewport(&intel->ViewportMatrix,
416 ctx->Viewport.X,
417 ctx->Viewport.Y,
418 ctx->Viewport.Width,
419 ctx->Viewport.Height,
420 ctx->Viewport.Near,
421 ctx->Viewport.Far,
422 1.0);
423 }
424 }
425
426
427 /** Called from ctx->Driver.DepthRange() */
428 static void
429 i915DepthRange(struct gl_context *ctx)
430 {
431 intelCalcViewport(ctx);
432 }
433
434
435 /* =============================================================
436 * Polygon stipple
437 *
438 * The i915 supports a 4x4 stipple natively, GL wants 32x32.
439 * Fortunately stipple is usually a repeating pattern.
440 */
441 static void
442 i915PolygonStipple(struct gl_context * ctx, const GLubyte * mask)
443 {
444 struct i915_context *i915 = I915_CONTEXT(ctx);
445 const GLubyte *m;
446 GLubyte p[4];
447 int i, j, k;
448 int active = (ctx->Polygon.StippleFlag &&
449 i915->intel.reduced_primitive == GL_TRIANGLES);
450 GLuint newMask;
451
452 if (active) {
453 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
454 i915->state.Stipple[I915_STPREG_ST1] &= ~ST1_ENABLE;
455 }
456
457 /* Use the already unpacked stipple data from the context rather than the
458 * uninterpreted mask passed in.
459 */
460 mask = (const GLubyte *)ctx->PolygonStipple;
461 m = mask;
462
463 p[0] = mask[12] & 0xf;
464 p[0] |= p[0] << 4;
465 p[1] = mask[8] & 0xf;
466 p[1] |= p[1] << 4;
467 p[2] = mask[4] & 0xf;
468 p[2] |= p[2] << 4;
469 p[3] = mask[0] & 0xf;
470 p[3] |= p[3] << 4;
471
472 for (k = 0; k < 8; k++)
473 for (j = 3; j >= 0; j--)
474 for (i = 0; i < 4; i++, m++)
475 if (*m != p[j]) {
476 i915->intel.hw_stipple = 0;
477 return;
478 }
479
480 newMask = (((p[0] & 0xf) << 0) |
481 ((p[1] & 0xf) << 4) |
482 ((p[2] & 0xf) << 8) | ((p[3] & 0xf) << 12));
483
484
485 if (newMask == 0xffff || newMask == 0x0) {
486 /* this is needed to make conform pass */
487 i915->intel.hw_stipple = 0;
488 return;
489 }
490
491 i915->state.Stipple[I915_STPREG_ST1] &= ~0xffff;
492 i915->state.Stipple[I915_STPREG_ST1] |= newMask;
493 i915->intel.hw_stipple = 1;
494
495 if (active)
496 i915->state.Stipple[I915_STPREG_ST1] |= ST1_ENABLE;
497 }
498
499
500 /* =============================================================
501 * Hardware clipping
502 */
503 static void
504 i915Scissor(struct gl_context * ctx)
505 {
506 struct i915_context *i915 = I915_CONTEXT(ctx);
507 int x1, y1, x2, y2;
508
509 if (!ctx->DrawBuffer)
510 return;
511
512 DBG("%s %d,%d %dx%d\n", __FUNCTION__,
513 ctx->Scissor.X, ctx->Scissor.Y,
514 ctx->Scissor.Width, ctx->Scissor.Height);
515
516 if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
517 x1 = ctx->Scissor.X;
518 y1 = ctx->DrawBuffer->Height - (ctx->Scissor.Y + ctx->Scissor.Height);
519 x2 = ctx->Scissor.X + ctx->Scissor.Width - 1;
520 y2 = y1 + ctx->Scissor.Height - 1;
521 DBG("%s %d..%d,%d..%d (inverted)\n", __FUNCTION__, x1, x2, y1, y2);
522 }
523 else {
524 /* FBO - not inverted
525 */
526 x1 = ctx->Scissor.X;
527 y1 = ctx->Scissor.Y;
528 x2 = ctx->Scissor.X + ctx->Scissor.Width - 1;
529 y2 = ctx->Scissor.Y + ctx->Scissor.Height - 1;
530 DBG("%s %d..%d,%d..%d (not inverted)\n", __FUNCTION__, x1, x2, y1, y2);
531 }
532
533 x1 = CLAMP(x1, 0, ctx->DrawBuffer->Width - 1);
534 y1 = CLAMP(y1, 0, ctx->DrawBuffer->Height - 1);
535 x2 = CLAMP(x2, 0, ctx->DrawBuffer->Width - 1);
536 y2 = CLAMP(y2, 0, ctx->DrawBuffer->Height - 1);
537
538 DBG("%s %d..%d,%d..%d (clamped)\n", __FUNCTION__, x1, x2, y1, y2);
539
540 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
541 i915->state.Buffer[I915_DESTREG_SR1] = (y1 << 16) | (x1 & 0xffff);
542 i915->state.Buffer[I915_DESTREG_SR2] = (y2 << 16) | (x2 & 0xffff);
543 }
544
545 static void
546 i915LogicOp(struct gl_context * ctx, GLenum opcode)
547 {
548 struct i915_context *i915 = I915_CONTEXT(ctx);
549 int tmp = intel_translate_logic_op(opcode);
550
551 DBG("%s\n", __FUNCTION__);
552
553 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
554 i915->state.Ctx[I915_CTXREG_STATE4] &= ~LOGICOP_MASK;
555 i915->state.Ctx[I915_CTXREG_STATE4] |= LOGIC_OP_FUNC(tmp);
556 }
557
558
559
560 static void
561 i915CullFaceFrontFace(struct gl_context * ctx, GLenum unused)
562 {
563 struct i915_context *i915 = I915_CONTEXT(ctx);
564 GLuint mode, dw;
565
566 DBG("%s %d\n", __FUNCTION__,
567 ctx->DrawBuffer ? ctx->DrawBuffer->Name : 0);
568
569 if (!ctx->Polygon.CullFlag) {
570 mode = S4_CULLMODE_NONE;
571 }
572 else if (ctx->Polygon.CullFaceMode != GL_FRONT_AND_BACK) {
573 mode = S4_CULLMODE_CW;
574
575 if (ctx->DrawBuffer && _mesa_is_user_fbo(ctx->DrawBuffer))
576 mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
577 if (ctx->Polygon.CullFaceMode == GL_FRONT)
578 mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
579 if (ctx->Polygon.FrontFace != GL_CCW)
580 mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
581 }
582 else {
583 mode = S4_CULLMODE_BOTH;
584 }
585
586 dw = i915->state.Ctx[I915_CTXREG_LIS4];
587 dw &= ~S4_CULLMODE_MASK;
588 dw |= mode;
589 if (dw != i915->state.Ctx[I915_CTXREG_LIS4]) {
590 i915->state.Ctx[I915_CTXREG_LIS4] = dw;
591 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
592 }
593 }
594
595 static void
596 i915LineWidth(struct gl_context * ctx, GLfloat widthf)
597 {
598 struct i915_context *i915 = I915_CONTEXT(ctx);
599 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_LINE_WIDTH_MASK;
600 int width;
601
602 DBG("%s\n", __FUNCTION__);
603
604 width = (int) (widthf * 2);
605 width = CLAMP(width, 1, 0xf);
606 lis4 |= width << S4_LINE_WIDTH_SHIFT;
607
608 if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
609 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
610 i915->state.Ctx[I915_CTXREG_LIS4] = lis4;
611 }
612 }
613
614 static void
615 i915PointSize(struct gl_context * ctx, GLfloat size)
616 {
617 struct i915_context *i915 = I915_CONTEXT(ctx);
618 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_POINT_WIDTH_MASK;
619 GLint point_size = (int) round(size);
620
621 DBG("%s\n", __FUNCTION__);
622
623 point_size = CLAMP(point_size, 1, 255);
624 lis4 |= point_size << S4_POINT_WIDTH_SHIFT;
625
626 if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
627 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
628 i915->state.Ctx[I915_CTXREG_LIS4] = lis4;
629 }
630 }
631
632
633 static void
634 i915PointParameterfv(struct gl_context * ctx, GLenum pname, const GLfloat *params)
635 {
636 struct i915_context *i915 = I915_CONTEXT(ctx);
637
638 switch (pname) {
639 case GL_POINT_SPRITE_COORD_ORIGIN:
640 /* This could be supported, but it would require modifying the fragment
641 * program to invert the y component of the texture coordinate by
642 * inserting a 'SUB tc.y, {1.0}.xxxx, tc' instruction.
643 */
644 FALLBACK(&i915->intel, I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN,
645 (params[0] != GL_UPPER_LEFT));
646 break;
647 }
648 }
649
650 void
651 i915_update_sprite_point_enable(struct gl_context *ctx)
652 {
653 struct intel_context *intel = intel_context(ctx);
654 /* _NEW_PROGRAM */
655 struct i915_fragment_program *p =
656 (struct i915_fragment_program *) ctx->FragmentProgram._Current;
657 const GLbitfield64 inputsRead = p->FragProg.Base.InputsRead;
658 struct i915_context *i915 = i915_context(ctx);
659 GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
660 int i;
661 GLuint coord_replace_bits = 0x0;
662 GLuint tex_coord_unit_bits = 0x0;
663
664 for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
665 /* _NEW_POINT */
666 if (ctx->Point.CoordReplace[i] && ctx->Point.PointSprite)
667 coord_replace_bits |= (1 << i);
668 if (inputsRead & VARYING_BIT_TEX(i))
669 tex_coord_unit_bits |= (1 << i);
670 }
671
672 /*
673 * Here we can't enable the SPRITE_POINT_ENABLE bit when the mis-match
674 * of tex_coord_unit_bits and coord_replace_bits, or this will make all
675 * the other non-point-sprite coords(like varying inputs, as we now use
676 * tex coord to implement varying inputs) be replaced to value (0, 0)-(1, 1).
677 *
678 * Thus, do fallback when needed.
679 */
680 FALLBACK(intel, I915_FALLBACK_COORD_REPLACE,
681 coord_replace_bits && coord_replace_bits != tex_coord_unit_bits);
682
683 s4 &= ~S4_SPRITE_POINT_ENABLE;
684 s4 |= (coord_replace_bits && coord_replace_bits == tex_coord_unit_bits) ?
685 S4_SPRITE_POINT_ENABLE : 0;
686 if (s4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
687 i915->state.Ctx[I915_CTXREG_LIS4] = s4;
688 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
689 }
690 }
691
692
693 /* =============================================================
694 * Color masks
695 */
696
697 static void
698 i915ColorMask(struct gl_context * ctx,
699 GLboolean r, GLboolean g, GLboolean b, GLboolean a)
700 {
701 struct i915_context *i915 = I915_CONTEXT(ctx);
702 GLuint tmp = i915->state.Ctx[I915_CTXREG_LIS5] & ~S5_WRITEDISABLE_MASK;
703
704 DBG("%s r(%d) g(%d) b(%d) a(%d)\n", __FUNCTION__, r, g, b,
705 a);
706
707 if (!r)
708 tmp |= S5_WRITEDISABLE_RED;
709 if (!g)
710 tmp |= S5_WRITEDISABLE_GREEN;
711 if (!b)
712 tmp |= S5_WRITEDISABLE_BLUE;
713 if (!a)
714 tmp |= S5_WRITEDISABLE_ALPHA;
715
716 if (tmp != i915->state.Ctx[I915_CTXREG_LIS5]) {
717 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
718 i915->state.Ctx[I915_CTXREG_LIS5] = tmp;
719 }
720 }
721
722 static void
723 update_specular(struct gl_context * ctx)
724 {
725 /* A hack to trigger the rebuild of the fragment program.
726 */
727 intel_context(ctx)->NewGLState |= _NEW_TEXTURE;
728 }
729
730 static void
731 i915LightModelfv(struct gl_context * ctx, GLenum pname, const GLfloat * param)
732 {
733 DBG("%s\n", __FUNCTION__);
734
735 if (pname == GL_LIGHT_MODEL_COLOR_CONTROL) {
736 update_specular(ctx);
737 }
738 }
739
740 static void
741 i915ShadeModel(struct gl_context * ctx, GLenum mode)
742 {
743 struct i915_context *i915 = I915_CONTEXT(ctx);
744 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
745
746 if (mode == GL_SMOOTH) {
747 i915->state.Ctx[I915_CTXREG_LIS4] &= ~(S4_FLATSHADE_ALPHA |
748 S4_FLATSHADE_COLOR |
749 S4_FLATSHADE_SPECULAR);
750 }
751 else {
752 i915->state.Ctx[I915_CTXREG_LIS4] |= (S4_FLATSHADE_ALPHA |
753 S4_FLATSHADE_COLOR |
754 S4_FLATSHADE_SPECULAR);
755 }
756 }
757
758 /* =============================================================
759 * Fog
760 *
761 * This empty function remains because _mesa_init_driver_state calls
762 * dd_function_table::Fogfv unconditionally. We have to have some function
763 * there so that it doesn't try to call a NULL pointer.
764 */
765 static void
766 i915Fogfv(struct gl_context * ctx, GLenum pname, const GLfloat * param)
767 {
768 (void) ctx;
769 (void) pname;
770 (void) param;
771 }
772
773 /* =============================================================
774 */
775
776 static void
777 i915Enable(struct gl_context * ctx, GLenum cap, GLboolean state)
778 {
779 struct i915_context *i915 = I915_CONTEXT(ctx);
780 GLuint dw;
781
782 switch (cap) {
783 case GL_TEXTURE_2D:
784 break;
785
786 case GL_LIGHTING:
787 case GL_COLOR_SUM:
788 update_specular(ctx);
789 break;
790
791 case GL_ALPHA_TEST:
792 dw = i915->state.Ctx[I915_CTXREG_LIS6];
793 if (state)
794 dw |= S6_ALPHA_TEST_ENABLE;
795 else
796 dw &= ~S6_ALPHA_TEST_ENABLE;
797 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
798 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
799 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
800 }
801 break;
802
803 case GL_BLEND:
804 i915EvalLogicOpBlendState(ctx);
805 break;
806
807 case GL_COLOR_LOGIC_OP:
808 i915EvalLogicOpBlendState(ctx);
809
810 /* Logicop doesn't seem to work at 16bpp:
811 */
812 if (ctx->Visual.rgbBits == 16)
813 FALLBACK(&i915->intel, I915_FALLBACK_LOGICOP, state);
814 break;
815
816 case GL_FRAGMENT_PROGRAM_ARB:
817 break;
818
819 case GL_DITHER:
820 dw = i915->state.Ctx[I915_CTXREG_LIS5];
821 if (state)
822 dw |= S5_COLOR_DITHER_ENABLE;
823 else
824 dw &= ~S5_COLOR_DITHER_ENABLE;
825 if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
826 i915->state.Ctx[I915_CTXREG_LIS5] = dw;
827 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
828 }
829 break;
830
831 case GL_DEPTH_TEST:
832 dw = i915->state.Ctx[I915_CTXREG_LIS6];
833
834 if (!ctx->DrawBuffer || !ctx->DrawBuffer->Visual.depthBits)
835 state = false;
836
837 if (state)
838 dw |= S6_DEPTH_TEST_ENABLE;
839 else
840 dw &= ~S6_DEPTH_TEST_ENABLE;
841 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
842 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
843 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
844 }
845
846 i915DepthMask(ctx, ctx->Depth.Mask);
847 break;
848
849 case GL_SCISSOR_TEST:
850 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
851 if (state)
852 i915->state.Buffer[I915_DESTREG_SENABLE] =
853 (_3DSTATE_SCISSOR_ENABLE_CMD | ENABLE_SCISSOR_RECT);
854 else
855 i915->state.Buffer[I915_DESTREG_SENABLE] =
856 (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
857 break;
858
859 case GL_LINE_SMOOTH:
860 dw = i915->state.Ctx[I915_CTXREG_LIS4];
861 if (state)
862 dw |= S4_LINE_ANTIALIAS_ENABLE;
863 else
864 dw &= ~S4_LINE_ANTIALIAS_ENABLE;
865 if (dw != i915->state.Ctx[I915_CTXREG_LIS4]) {
866 i915->state.Ctx[I915_CTXREG_LIS4] = dw;
867 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
868 }
869 break;
870
871 case GL_CULL_FACE:
872 i915CullFaceFrontFace(ctx, 0);
873 break;
874
875 case GL_STENCIL_TEST:
876 if (!ctx->DrawBuffer || !ctx->DrawBuffer->Visual.stencilBits)
877 state = false;
878
879 dw = i915->state.Ctx[I915_CTXREG_LIS5];
880 if (state)
881 dw |= (S5_STENCIL_TEST_ENABLE | S5_STENCIL_WRITE_ENABLE);
882 else
883 dw &= ~(S5_STENCIL_TEST_ENABLE | S5_STENCIL_WRITE_ENABLE);
884 if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
885 i915->state.Ctx[I915_CTXREG_LIS5] = dw;
886 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
887 }
888 break;
889
890 case GL_POLYGON_STIPPLE:
891 /* The stipple command worked on my 855GM box, but not my 845G.
892 * I'll do more testing later to find out exactly which hardware
893 * supports it. Disabled for now.
894 */
895 if (i915->intel.hw_stipple &&
896 i915->intel.reduced_primitive == GL_TRIANGLES) {
897 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
898 if (state)
899 i915->state.Stipple[I915_STPREG_ST1] |= ST1_ENABLE;
900 else
901 i915->state.Stipple[I915_STPREG_ST1] &= ~ST1_ENABLE;
902 }
903 break;
904
905 case GL_POLYGON_SMOOTH:
906 break;
907
908 case GL_POINT_SPRITE:
909 /* Handle it at i915_update_sprite_point_enable () */
910 break;
911
912 case GL_POINT_SMOOTH:
913 break;
914
915 default:
916 ;
917 }
918 }
919
920
921 static void
922 i915_init_packets(struct i915_context *i915)
923 {
924 /* Zero all state */
925 memset(&i915->state, 0, sizeof(i915->state));
926
927
928 {
929 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
930 I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
931 /* Probably don't want to upload all this stuff every time one
932 * piece changes.
933 */
934 i915->state.Ctx[I915_CTXREG_LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
935 I1_LOAD_S(2) |
936 I1_LOAD_S(4) |
937 I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
938 i915->state.Ctx[I915_CTXREG_LIS2] = 0;
939 i915->state.Ctx[I915_CTXREG_LIS4] = 0;
940 i915->state.Ctx[I915_CTXREG_LIS5] = 0;
941
942 if (i915->intel.ctx.Visual.rgbBits == 16)
943 i915->state.Ctx[I915_CTXREG_LIS5] |= S5_COLOR_DITHER_ENABLE;
944
945
946 i915->state.Ctx[I915_CTXREG_LIS6] = (S6_COLOR_WRITE_ENABLE |
947 (2 << S6_TRISTRIP_PV_SHIFT));
948
949 i915->state.Ctx[I915_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
950 ENABLE_LOGIC_OP_FUNC |
951 LOGIC_OP_FUNC(LOGICOP_COPY) |
952 ENABLE_STENCIL_TEST_MASK |
953 STENCIL_TEST_MASK(0xff) |
954 ENABLE_STENCIL_WRITE_MASK |
955 STENCIL_WRITE_MASK(0xff));
956
957 i915->state.Blend[I915_BLENDREG_IAB] =
958 (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE |
959 IAB_MODIFY_FUNC | IAB_MODIFY_SRC_FACTOR | IAB_MODIFY_DST_FACTOR);
960
961 i915->state.Blend[I915_BLENDREG_BLENDCOLOR0] =
962 _3DSTATE_CONST_BLEND_COLOR_CMD;
963 i915->state.Blend[I915_BLENDREG_BLENDCOLOR1] = 0;
964
965 i915->state.Ctx[I915_CTXREG_BF_STENCIL_MASKS] =
966 _3DSTATE_BACKFACE_STENCIL_MASKS |
967 BFM_ENABLE_STENCIL_TEST_MASK |
968 BFM_ENABLE_STENCIL_WRITE_MASK |
969 (0xff << BFM_STENCIL_WRITE_MASK_SHIFT) |
970 (0xff << BFM_STENCIL_TEST_MASK_SHIFT);
971 i915->state.Ctx[I915_CTXREG_BF_STENCIL_OPS] =
972 _3DSTATE_BACKFACE_STENCIL_OPS |
973 BFO_ENABLE_STENCIL_REF |
974 BFO_ENABLE_STENCIL_FUNCS |
975 BFO_ENABLE_STENCIL_TWO_SIDE;
976 }
977
978 {
979 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
980 i915->state.Stipple[I915_STPREG_ST0] = _3DSTATE_STIPPLE;
981 }
982
983 {
984 i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
985
986 /* scissor */
987 i915->state.Buffer[I915_DESTREG_SENABLE] =
988 (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
989 i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
990 i915->state.Buffer[I915_DESTREG_SR1] = 0;
991 i915->state.Buffer[I915_DESTREG_SR2] = 0;
992 }
993
994 i915->state.RasterRules[I915_RASTER_RULES] = _3DSTATE_RASTER_RULES_CMD |
995 ENABLE_POINT_RASTER_RULE |
996 OGL_POINT_RASTER_RULE |
997 ENABLE_LINE_STRIP_PROVOKE_VRTX |
998 ENABLE_TRI_FAN_PROVOKE_VRTX |
999 LINE_STRIP_PROVOKE_VRTX(1) |
1000 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D;
1001
1002 #if 0
1003 {
1004 I915_STATECHANGE(i915, I915_UPLOAD_DEFAULTS);
1005 i915->state.Default[I915_DEFREG_C0] = _3DSTATE_DEFAULT_DIFFUSE;
1006 i915->state.Default[I915_DEFREG_C1] = 0;
1007 i915->state.Default[I915_DEFREG_S0] = _3DSTATE_DEFAULT_SPECULAR;
1008 i915->state.Default[I915_DEFREG_S1] = 0;
1009 i915->state.Default[I915_DEFREG_Z0] = _3DSTATE_DEFAULT_Z;
1010 i915->state.Default[I915_DEFREG_Z1] = 0;
1011 }
1012 #endif
1013
1014
1015 /* These will be emitted every at the head of every buffer, unless
1016 * we get hardware contexts working.
1017 */
1018 i915->state.active = (I915_UPLOAD_PROGRAM |
1019 I915_UPLOAD_STIPPLE |
1020 I915_UPLOAD_CTX |
1021 I915_UPLOAD_BLEND |
1022 I915_UPLOAD_BUFFERS |
1023 I915_UPLOAD_INVARIENT |
1024 I915_UPLOAD_RASTER_RULES);
1025 }
1026
1027 void
1028 i915_update_provoking_vertex(struct gl_context * ctx)
1029 {
1030 struct i915_context *i915 = I915_CONTEXT(ctx);
1031
1032 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
1033 i915->state.Ctx[I915_CTXREG_LIS6] &= ~(S6_TRISTRIP_PV_MASK);
1034
1035 I915_STATECHANGE(i915, I915_UPLOAD_RASTER_RULES);
1036 i915->state.RasterRules[I915_RASTER_RULES] &= ~(LINE_STRIP_PROVOKE_VRTX_MASK |
1037 TRI_FAN_PROVOKE_VRTX_MASK);
1038
1039 /* _NEW_LIGHT */
1040 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION) {
1041 i915->state.RasterRules[I915_RASTER_RULES] |= (LINE_STRIP_PROVOKE_VRTX(1) |
1042 TRI_FAN_PROVOKE_VRTX(2));
1043 i915->state.Ctx[I915_CTXREG_LIS6] |= (2 << S6_TRISTRIP_PV_SHIFT);
1044 } else {
1045 i915->state.RasterRules[I915_RASTER_RULES] |= (LINE_STRIP_PROVOKE_VRTX(0) |
1046 TRI_FAN_PROVOKE_VRTX(1));
1047 i915->state.Ctx[I915_CTXREG_LIS6] |= (0 << S6_TRISTRIP_PV_SHIFT);
1048 }
1049 }
1050
1051 /* Fallback to swrast for select and feedback.
1052 */
1053 static void
1054 i915RenderMode(struct gl_context *ctx, GLenum mode)
1055 {
1056 struct intel_context *intel = intel_context(ctx);
1057 FALLBACK(intel, INTEL_FALLBACK_RENDERMODE, (mode != GL_RENDER));
1058 }
1059
1060 void
1061 i915InitStateFunctions(struct dd_function_table *functions)
1062 {
1063 functions->AlphaFunc = i915AlphaFunc;
1064 functions->BlendColor = i915BlendColor;
1065 functions->BlendEquationSeparate = i915BlendEquationSeparate;
1066 functions->BlendFuncSeparate = i915BlendFuncSeparate;
1067 functions->ColorMask = i915ColorMask;
1068 functions->CullFace = i915CullFaceFrontFace;
1069 functions->DepthFunc = i915DepthFunc;
1070 functions->DepthMask = i915DepthMask;
1071 functions->Enable = i915Enable;
1072 functions->Fogfv = i915Fogfv;
1073 functions->FrontFace = i915CullFaceFrontFace;
1074 functions->LightModelfv = i915LightModelfv;
1075 functions->LineWidth = i915LineWidth;
1076 functions->LogicOpcode = i915LogicOp;
1077 functions->PointSize = i915PointSize;
1078 functions->PointParameterfv = i915PointParameterfv;
1079 functions->PolygonStipple = i915PolygonStipple;
1080 functions->RenderMode = i915RenderMode;
1081 functions->Scissor = i915Scissor;
1082 functions->ShadeModel = i915ShadeModel;
1083 functions->StencilFuncSeparate = i915StencilFuncSeparate;
1084 functions->StencilMaskSeparate = i915StencilMaskSeparate;
1085 functions->StencilOpSeparate = i915StencilOpSeparate;
1086 functions->DepthRange = i915DepthRange;
1087 }
1088
1089
1090 void
1091 i915InitState(struct i915_context *i915)
1092 {
1093 struct gl_context *ctx = &i915->intel.ctx;
1094
1095 i915_init_packets(i915);
1096
1097 _mesa_init_driver_state(ctx);
1098 }