1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/glheader.h"
30 #include "main/context.h"
31 #include "main/macros.h"
32 #include "main/enums.h"
33 #include "main/fbobject.h"
35 #include "main/state.h"
36 #include "main/stencil.h"
38 #include "tnl/t_context.h"
40 #include "drivers/common/driverfuncs.h"
42 #include "intel_fbo.h"
43 #include "intel_screen.h"
44 #include "intel_batchbuffer.h"
45 #include "intel_buffers.h"
47 #include "i915_context.h"
50 #define FILE_DEBUG_FLAG DEBUG_STATE
53 i915_update_stencil(struct gl_context
* ctx
)
55 struct i915_context
*i915
= I915_CONTEXT(ctx
);
56 GLuint front_ref
, front_writemask
, front_mask
;
57 GLenum front_func
, front_fail
, front_pass_z_fail
, front_pass_z_pass
;
58 GLuint back_ref
, back_writemask
, back_mask
;
59 GLenum back_func
, back_fail
, back_pass_z_fail
, back_pass_z_pass
;
62 /* The 915 considers CW to be "front" for two-sided stencil, so choose
65 /* _NEW_POLYGON | _NEW_STENCIL */
66 if (ctx
->Polygon
.FrontFace
== GL_CW
) {
67 front_ref
= _mesa_get_stencil_ref(ctx
, 0);
68 front_mask
= ctx
->Stencil
.ValueMask
[0];
69 front_writemask
= ctx
->Stencil
.WriteMask
[0];
70 front_func
= ctx
->Stencil
.Function
[0];
71 front_fail
= ctx
->Stencil
.FailFunc
[0];
72 front_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[0];
73 front_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[0];
74 back_ref
= _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
75 back_mask
= ctx
->Stencil
.ValueMask
[ctx
->Stencil
._BackFace
];
76 back_writemask
= ctx
->Stencil
.WriteMask
[ctx
->Stencil
._BackFace
];
77 back_func
= ctx
->Stencil
.Function
[ctx
->Stencil
._BackFace
];
78 back_fail
= ctx
->Stencil
.FailFunc
[ctx
->Stencil
._BackFace
];
79 back_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[ctx
->Stencil
._BackFace
];
80 back_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[ctx
->Stencil
._BackFace
];
82 front_ref
= _mesa_get_stencil_ref(ctx
, ctx
->Stencil
._BackFace
);
83 front_mask
= ctx
->Stencil
.ValueMask
[ctx
->Stencil
._BackFace
];
84 front_writemask
= ctx
->Stencil
.WriteMask
[ctx
->Stencil
._BackFace
];
85 front_func
= ctx
->Stencil
.Function
[ctx
->Stencil
._BackFace
];
86 front_fail
= ctx
->Stencil
.FailFunc
[ctx
->Stencil
._BackFace
];
87 front_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[ctx
->Stencil
._BackFace
];
88 front_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[ctx
->Stencil
._BackFace
];
89 back_ref
= _mesa_get_stencil_ref(ctx
, 0);
90 back_mask
= ctx
->Stencil
.ValueMask
[0];
91 back_writemask
= ctx
->Stencil
.WriteMask
[0];
92 back_func
= ctx
->Stencil
.Function
[0];
93 back_fail
= ctx
->Stencil
.FailFunc
[0];
94 back_pass_z_fail
= ctx
->Stencil
.ZFailFunc
[0];
95 back_pass_z_pass
= ctx
->Stencil
.ZPassFunc
[0];
97 #define set_ctx_bits(reg, mask, set) do{ \
98 GLuint dw = i915->state.Ctx[reg]; \
101 dirty |= dw != i915->state.Ctx[reg]; \
102 i915->state.Ctx[reg] = dw; \
105 /* Set front state. */
106 set_ctx_bits(I915_CTXREG_STATE4
,
107 MODE4_ENABLE_STENCIL_TEST_MASK
|
108 MODE4_ENABLE_STENCIL_WRITE_MASK
,
109 ENABLE_STENCIL_TEST_MASK
|
110 ENABLE_STENCIL_WRITE_MASK
|
111 STENCIL_TEST_MASK(front_mask
) |
112 STENCIL_WRITE_MASK(front_writemask
));
114 set_ctx_bits(I915_CTXREG_LIS5
,
115 S5_STENCIL_REF_MASK
|
116 S5_STENCIL_TEST_FUNC_MASK
|
117 S5_STENCIL_FAIL_MASK
|
118 S5_STENCIL_PASS_Z_FAIL_MASK
|
119 S5_STENCIL_PASS_Z_PASS_MASK
,
120 (front_ref
<< S5_STENCIL_REF_SHIFT
) |
121 (intel_translate_compare_func(front_func
) << S5_STENCIL_TEST_FUNC_SHIFT
) |
122 (intel_translate_stencil_op(front_fail
) << S5_STENCIL_FAIL_SHIFT
) |
123 (intel_translate_stencil_op(front_pass_z_fail
) <<
124 S5_STENCIL_PASS_Z_FAIL_SHIFT
) |
125 (intel_translate_stencil_op(front_pass_z_pass
) <<
126 S5_STENCIL_PASS_Z_PASS_SHIFT
));
128 /* Set back state if different from front. */
129 if (ctx
->Stencil
._TestTwoSide
) {
130 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS
,
131 BFO_STENCIL_REF_MASK
|
132 BFO_STENCIL_TEST_MASK
|
133 BFO_STENCIL_FAIL_MASK
|
134 BFO_STENCIL_PASS_Z_FAIL_MASK
|
135 BFO_STENCIL_PASS_Z_PASS_MASK
,
136 BFO_STENCIL_TWO_SIDE
|
137 (back_ref
<< BFO_STENCIL_REF_SHIFT
) |
138 (intel_translate_compare_func(back_func
) << BFO_STENCIL_TEST_SHIFT
) |
139 (intel_translate_stencil_op(back_fail
) << BFO_STENCIL_FAIL_SHIFT
) |
140 (intel_translate_stencil_op(back_pass_z_fail
) <<
141 BFO_STENCIL_PASS_Z_FAIL_SHIFT
) |
142 (intel_translate_stencil_op(back_pass_z_pass
) <<
143 BFO_STENCIL_PASS_Z_PASS_SHIFT
));
145 set_ctx_bits(I915_CTXREG_BF_STENCIL_MASKS
,
146 BFM_STENCIL_TEST_MASK_MASK
|
147 BFM_STENCIL_WRITE_MASK_MASK
,
148 BFM_STENCIL_TEST_MASK(back_mask
) |
149 BFM_STENCIL_WRITE_MASK(back_writemask
));
151 set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS
,
152 BFO_STENCIL_TWO_SIDE
, 0);
158 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
162 i915StencilFuncSeparate(struct gl_context
* ctx
, GLenum face
, GLenum func
, GLint ref
,
168 i915StencilMaskSeparate(struct gl_context
* ctx
, GLenum face
, GLuint mask
)
173 i915StencilOpSeparate(struct gl_context
* ctx
, GLenum face
, GLenum fail
, GLenum zfail
,
179 i915AlphaFunc(struct gl_context
* ctx
, GLenum func
, GLfloat ref
)
181 struct i915_context
*i915
= I915_CONTEXT(ctx
);
182 int test
= intel_translate_compare_func(func
);
186 UNCLAMPED_FLOAT_TO_UBYTE(refByte
, ref
);
188 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
189 dw
&= ~(S6_ALPHA_TEST_FUNC_MASK
| S6_ALPHA_REF_MASK
);
190 dw
|= ((test
<< S6_ALPHA_TEST_FUNC_SHIFT
) |
191 (((GLuint
) refByte
) << S6_ALPHA_REF_SHIFT
));
192 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
193 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
194 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
198 /* This function makes sure that the proper enables are
199 * set for LogicOp, Independant Alpha Blend, and Blending.
200 * It needs to be called from numerous places where we
201 * could change the LogicOp or Independant Alpha Blend without subsequent
205 i915EvalLogicOpBlendState(struct gl_context
* ctx
)
207 struct i915_context
*i915
= I915_CONTEXT(ctx
);
210 dw0
= i915
->state
.Ctx
[I915_CTXREG_LIS5
];
211 dw1
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
213 if (ctx
->Color
.ColorLogicOpEnabled
) {
214 dw0
|= S5_LOGICOP_ENABLE
;
215 dw1
&= ~S6_CBUF_BLEND_ENABLE
;
218 dw0
&= ~S5_LOGICOP_ENABLE
;
220 if (ctx
->Color
.BlendEnabled
) {
221 dw1
|= S6_CBUF_BLEND_ENABLE
;
224 dw1
&= ~S6_CBUF_BLEND_ENABLE
;
227 if (dw0
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
] ||
228 dw1
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
229 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = dw0
;
230 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw1
;
232 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
237 i915BlendColor(struct gl_context
* ctx
, const GLfloat color
[4])
239 struct i915_context
*i915
= I915_CONTEXT(ctx
);
243 DBG("%s\n", __FUNCTION__
);
245 UNCLAMPED_FLOAT_TO_UBYTE(r
, color
[RCOMP
]);
246 UNCLAMPED_FLOAT_TO_UBYTE(g
, color
[GCOMP
]);
247 UNCLAMPED_FLOAT_TO_UBYTE(b
, color
[BCOMP
]);
248 UNCLAMPED_FLOAT_TO_UBYTE(a
, color
[ACOMP
]);
250 dw
= (a
<< 24) | (r
<< 16) | (g
<< 8) | b
;
251 if (dw
!= i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR1
]) {
252 i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR1
] = dw
;
253 I915_STATECHANGE(i915
, I915_UPLOAD_BLEND
);
258 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
259 #define SRC_BLND_FACT(f) ((f)<<S6_CBUF_SRC_BLEND_FACT_SHIFT)
260 #define DST_ABLND_FACT(f) ((f)<<IAB_DST_FACTOR_SHIFT)
261 #define SRC_ABLND_FACT(f) ((f)<<IAB_SRC_FACTOR_SHIFT)
266 translate_blend_equation(GLenum mode
)
270 return BLENDFUNC_ADD
;
272 return BLENDFUNC_MIN
;
274 return BLENDFUNC_MAX
;
275 case GL_FUNC_SUBTRACT
:
276 return BLENDFUNC_SUBTRACT
;
277 case GL_FUNC_REVERSE_SUBTRACT
:
278 return BLENDFUNC_REVERSE_SUBTRACT
;
285 i915UpdateBlendState(struct gl_context
* ctx
)
287 struct i915_context
*i915
= I915_CONTEXT(ctx
);
288 GLuint iab
= (i915
->state
.Blend
[I915_BLENDREG_IAB
] &
289 ~(IAB_SRC_FACTOR_MASK
|
290 IAB_DST_FACTOR_MASK
|
291 (BLENDFUNC_MASK
<< IAB_FUNC_SHIFT
) | IAB_ENABLE
));
293 GLuint lis6
= (i915
->state
.Ctx
[I915_CTXREG_LIS6
] &
294 ~(S6_CBUF_SRC_BLEND_FACT_MASK
|
295 S6_CBUF_DST_BLEND_FACT_MASK
| S6_CBUF_BLEND_FUNC_MASK
));
297 GLuint eqRGB
= ctx
->Color
.Blend
[0].EquationRGB
;
298 GLuint eqA
= ctx
->Color
.Blend
[0].EquationA
;
299 GLuint srcRGB
= ctx
->Color
.Blend
[0].SrcRGB
;
300 GLuint dstRGB
= ctx
->Color
.Blend
[0].DstRGB
;
301 GLuint srcA
= ctx
->Color
.Blend
[0].SrcA
;
302 GLuint dstA
= ctx
->Color
.Blend
[0].DstA
;
304 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
) {
305 srcRGB
= dstRGB
= GL_ONE
;
308 if (eqA
== GL_MIN
|| eqA
== GL_MAX
) {
309 srcA
= dstA
= GL_ONE
;
312 lis6
|= SRC_BLND_FACT(intel_translate_blend_factor(srcRGB
));
313 lis6
|= DST_BLND_FACT(intel_translate_blend_factor(dstRGB
));
314 lis6
|= translate_blend_equation(eqRGB
) << S6_CBUF_BLEND_FUNC_SHIFT
;
316 iab
|= SRC_ABLND_FACT(intel_translate_blend_factor(srcA
));
317 iab
|= DST_ABLND_FACT(intel_translate_blend_factor(dstA
));
318 iab
|= translate_blend_equation(eqA
) << IAB_FUNC_SHIFT
;
320 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
)
323 if (iab
!= i915
->state
.Blend
[I915_BLENDREG_IAB
]) {
324 i915
->state
.Blend
[I915_BLENDREG_IAB
] = iab
;
325 I915_STATECHANGE(i915
, I915_UPLOAD_BLEND
);
327 if (lis6
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
328 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = lis6
;
329 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
332 /* This will catch a logicop blend equation */
333 i915EvalLogicOpBlendState(ctx
);
338 i915BlendFuncSeparate(struct gl_context
* ctx
, GLenum srcRGB
,
339 GLenum dstRGB
, GLenum srcA
, GLenum dstA
)
341 i915UpdateBlendState(ctx
);
346 i915BlendEquationSeparate(struct gl_context
* ctx
, GLenum eqRGB
, GLenum eqA
)
348 i915UpdateBlendState(ctx
);
353 i915DepthFunc(struct gl_context
* ctx
, GLenum func
)
355 struct i915_context
*i915
= I915_CONTEXT(ctx
);
356 int test
= intel_translate_compare_func(func
);
359 DBG("%s\n", __FUNCTION__
);
361 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
362 dw
&= ~S6_DEPTH_TEST_FUNC_MASK
;
363 dw
|= test
<< S6_DEPTH_TEST_FUNC_SHIFT
;
364 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
365 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
366 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
371 i915DepthMask(struct gl_context
* ctx
, GLboolean flag
)
373 struct i915_context
*i915
= I915_CONTEXT(ctx
);
376 DBG("%s flag (%d)\n", __FUNCTION__
, flag
);
378 if (!ctx
->DrawBuffer
|| !ctx
->DrawBuffer
->Visual
.depthBits
)
381 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
382 if (flag
&& ctx
->Depth
.Test
)
383 dw
|= S6_DEPTH_WRITE_ENABLE
;
385 dw
&= ~S6_DEPTH_WRITE_ENABLE
;
386 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
387 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
388 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
395 * Update the viewport transformation matrix. Depends on:
396 * - viewport pos/size
398 * - window pos/size or FBO size
401 intelCalcViewport(struct gl_context
* ctx
)
403 struct intel_context
*intel
= intel_context(ctx
);
405 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
406 _math_matrix_viewport(&intel
->ViewportMatrix
,
407 ctx
->ViewportArray
[0].X
,
408 ctx
->DrawBuffer
->Height
- ctx
->ViewportArray
[0].Y
,
409 ctx
->ViewportArray
[0].Width
,
410 -ctx
->ViewportArray
[0].Height
,
411 ctx
->ViewportArray
[0].Near
,
412 ctx
->ViewportArray
[0].Far
,
415 _math_matrix_viewport(&intel
->ViewportMatrix
,
416 ctx
->ViewportArray
[0].X
,
417 ctx
->ViewportArray
[0].Y
,
418 ctx
->ViewportArray
[0].Width
,
419 ctx
->ViewportArray
[0].Height
,
420 ctx
->ViewportArray
[0].Near
,
421 ctx
->ViewportArray
[0].Far
,
427 /** Called from ctx->Driver.DepthRange() */
429 i915DepthRange(struct gl_context
*ctx
)
431 intelCalcViewport(ctx
);
435 /* =============================================================
438 * The i915 supports a 4x4 stipple natively, GL wants 32x32.
439 * Fortunately stipple is usually a repeating pattern.
442 i915PolygonStipple(struct gl_context
* ctx
, const GLubyte
* mask
)
444 struct i915_context
*i915
= I915_CONTEXT(ctx
);
448 int active
= (ctx
->Polygon
.StippleFlag
&&
449 i915
->intel
.reduced_primitive
== GL_TRIANGLES
);
453 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
454 i915
->state
.Stipple
[I915_STPREG_ST1
] &= ~ST1_ENABLE
;
457 /* Use the already unpacked stipple data from the context rather than the
458 * uninterpreted mask passed in.
460 mask
= (const GLubyte
*)ctx
->PolygonStipple
;
463 p
[0] = mask
[12] & 0xf;
465 p
[1] = mask
[8] & 0xf;
467 p
[2] = mask
[4] & 0xf;
469 p
[3] = mask
[0] & 0xf;
472 for (k
= 0; k
< 8; k
++)
473 for (j
= 3; j
>= 0; j
--)
474 for (i
= 0; i
< 4; i
++, m
++)
476 i915
->intel
.hw_stipple
= 0;
480 newMask
= (((p
[0] & 0xf) << 0) |
481 ((p
[1] & 0xf) << 4) |
482 ((p
[2] & 0xf) << 8) | ((p
[3] & 0xf) << 12));
485 if (newMask
== 0xffff || newMask
== 0x0) {
486 /* this is needed to make conform pass */
487 i915
->intel
.hw_stipple
= 0;
491 i915
->state
.Stipple
[I915_STPREG_ST1
] &= ~0xffff;
492 i915
->state
.Stipple
[I915_STPREG_ST1
] |= newMask
;
493 i915
->intel
.hw_stipple
= 1;
496 i915
->state
.Stipple
[I915_STPREG_ST1
] |= ST1_ENABLE
;
500 /* =============================================================
504 i915Scissor(struct gl_context
* ctx
)
506 struct i915_context
*i915
= I915_CONTEXT(ctx
);
509 if (!ctx
->DrawBuffer
)
512 DBG("%s %d,%d %dx%d\n", __FUNCTION__
,
513 ctx
->Scissor
.ScissorArray
[0].X
, ctx
->Scissor
.ScissorArray
[0].Y
,
514 ctx
->Scissor
.ScissorArray
[0].Width
, ctx
->Scissor
.ScissorArray
[0].Height
);
516 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
517 x1
= ctx
->Scissor
.ScissorArray
[0].X
;
518 y1
= ctx
->DrawBuffer
->Height
- (ctx
->Scissor
.ScissorArray
[0].Y
519 + ctx
->Scissor
.ScissorArray
[0].Height
);
520 x2
= ctx
->Scissor
.ScissorArray
[0].X
521 + ctx
->Scissor
.ScissorArray
[0].Width
- 1;
522 y2
= y1
+ ctx
->Scissor
.ScissorArray
[0].Height
- 1;
523 DBG("%s %d..%d,%d..%d (inverted)\n", __FUNCTION__
, x1
, x2
, y1
, y2
);
526 /* FBO - not inverted
528 x1
= ctx
->Scissor
.ScissorArray
[0].X
;
529 y1
= ctx
->Scissor
.ScissorArray
[0].Y
;
530 x2
= ctx
->Scissor
.ScissorArray
[0].X
531 + ctx
->Scissor
.ScissorArray
[0].Width
- 1;
532 y2
= ctx
->Scissor
.ScissorArray
[0].Y
533 + ctx
->Scissor
.ScissorArray
[0].Height
- 1;
534 DBG("%s %d..%d,%d..%d (not inverted)\n", __FUNCTION__
, x1
, x2
, y1
, y2
);
537 x1
= CLAMP(x1
, 0, ctx
->DrawBuffer
->Width
- 1);
538 y1
= CLAMP(y1
, 0, ctx
->DrawBuffer
->Height
- 1);
539 x2
= CLAMP(x2
, 0, ctx
->DrawBuffer
->Width
- 1);
540 y2
= CLAMP(y2
, 0, ctx
->DrawBuffer
->Height
- 1);
542 DBG("%s %d..%d,%d..%d (clamped)\n", __FUNCTION__
, x1
, x2
, y1
, y2
);
544 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
545 i915
->state
.Buffer
[I915_DESTREG_SR1
] = (y1
<< 16) | (x1
& 0xffff);
546 i915
->state
.Buffer
[I915_DESTREG_SR2
] = (y2
<< 16) | (x2
& 0xffff);
550 i915LogicOp(struct gl_context
* ctx
, GLenum opcode
)
552 struct i915_context
*i915
= I915_CONTEXT(ctx
);
553 int tmp
= intel_translate_logic_op(opcode
);
555 DBG("%s\n", __FUNCTION__
);
557 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
558 i915
->state
.Ctx
[I915_CTXREG_STATE4
] &= ~LOGICOP_MASK
;
559 i915
->state
.Ctx
[I915_CTXREG_STATE4
] |= LOGIC_OP_FUNC(tmp
);
565 i915CullFaceFrontFace(struct gl_context
* ctx
, GLenum unused
)
567 struct i915_context
*i915
= I915_CONTEXT(ctx
);
570 DBG("%s %d\n", __FUNCTION__
,
571 ctx
->DrawBuffer
? ctx
->DrawBuffer
->Name
: 0);
573 if (!ctx
->Polygon
.CullFlag
) {
574 mode
= S4_CULLMODE_NONE
;
576 else if (ctx
->Polygon
.CullFaceMode
!= GL_FRONT_AND_BACK
) {
577 mode
= S4_CULLMODE_CW
;
579 if (ctx
->DrawBuffer
&& _mesa_is_user_fbo(ctx
->DrawBuffer
))
580 mode
^= (S4_CULLMODE_CW
^ S4_CULLMODE_CCW
);
581 if (ctx
->Polygon
.CullFaceMode
== GL_FRONT
)
582 mode
^= (S4_CULLMODE_CW
^ S4_CULLMODE_CCW
);
583 if (ctx
->Polygon
.FrontFace
!= GL_CCW
)
584 mode
^= (S4_CULLMODE_CW
^ S4_CULLMODE_CCW
);
587 mode
= S4_CULLMODE_BOTH
;
590 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
591 dw
&= ~S4_CULLMODE_MASK
;
593 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
594 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = dw
;
595 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
600 i915LineWidth(struct gl_context
* ctx
, GLfloat widthf
)
602 struct i915_context
*i915
= I915_CONTEXT(ctx
);
603 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
] & ~S4_LINE_WIDTH_MASK
;
606 DBG("%s\n", __FUNCTION__
);
608 width
= (int) (widthf
* 2);
609 width
= CLAMP(width
, 1, 0xf);
610 lis4
|= width
<< S4_LINE_WIDTH_SHIFT
;
612 if (lis4
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
613 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
614 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = lis4
;
619 i915PointSize(struct gl_context
* ctx
, GLfloat size
)
621 struct i915_context
*i915
= I915_CONTEXT(ctx
);
622 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
] & ~S4_POINT_WIDTH_MASK
;
623 GLint point_size
= (int) round(size
);
625 DBG("%s\n", __FUNCTION__
);
627 point_size
= CLAMP(point_size
, 1, 255);
628 lis4
|= point_size
<< S4_POINT_WIDTH_SHIFT
;
630 if (lis4
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
631 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
632 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = lis4
;
638 i915PointParameterfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
*params
)
640 struct i915_context
*i915
= I915_CONTEXT(ctx
);
643 case GL_POINT_SPRITE_COORD_ORIGIN
:
644 /* This could be supported, but it would require modifying the fragment
645 * program to invert the y component of the texture coordinate by
646 * inserting a 'SUB tc.y, {1.0}.xxxx, tc' instruction.
648 FALLBACK(&i915
->intel
, I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN
,
649 (params
[0] != GL_UPPER_LEFT
));
655 i915_update_sprite_point_enable(struct gl_context
*ctx
)
657 struct intel_context
*intel
= intel_context(ctx
);
659 struct i915_fragment_program
*p
=
660 (struct i915_fragment_program
*) ctx
->FragmentProgram
._Current
;
661 const GLbitfield64 inputsRead
= p
->FragProg
.Base
.InputsRead
;
662 struct i915_context
*i915
= i915_context(ctx
);
663 GLuint s4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
] & ~S4_VFMT_MASK
;
665 GLuint coord_replace_bits
= 0x0;
666 GLuint tex_coord_unit_bits
= 0x0;
668 for (i
= 0; i
< ctx
->Const
.MaxTextureCoordUnits
; i
++) {
670 if (ctx
->Point
.CoordReplace
[i
] && ctx
->Point
.PointSprite
)
671 coord_replace_bits
|= (1 << i
);
672 if (inputsRead
& VARYING_BIT_TEX(i
))
673 tex_coord_unit_bits
|= (1 << i
);
677 * Here we can't enable the SPRITE_POINT_ENABLE bit when the mis-match
678 * of tex_coord_unit_bits and coord_replace_bits, or this will make all
679 * the other non-point-sprite coords(like varying inputs, as we now use
680 * tex coord to implement varying inputs) be replaced to value (0, 0)-(1, 1).
682 * Thus, do fallback when needed.
684 FALLBACK(intel
, I915_FALLBACK_COORD_REPLACE
,
685 coord_replace_bits
&& coord_replace_bits
!= tex_coord_unit_bits
);
687 s4
&= ~S4_SPRITE_POINT_ENABLE
;
688 s4
|= (coord_replace_bits
&& coord_replace_bits
== tex_coord_unit_bits
) ?
689 S4_SPRITE_POINT_ENABLE
: 0;
690 if (s4
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
691 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = s4
;
692 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
697 /* =============================================================
702 i915ColorMask(struct gl_context
* ctx
,
703 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
)
705 struct i915_context
*i915
= I915_CONTEXT(ctx
);
706 GLuint tmp
= i915
->state
.Ctx
[I915_CTXREG_LIS5
] & ~S5_WRITEDISABLE_MASK
;
708 DBG("%s r(%d) g(%d) b(%d) a(%d)\n", __FUNCTION__
, r
, g
, b
,
712 tmp
|= S5_WRITEDISABLE_RED
;
714 tmp
|= S5_WRITEDISABLE_GREEN
;
716 tmp
|= S5_WRITEDISABLE_BLUE
;
718 tmp
|= S5_WRITEDISABLE_ALPHA
;
720 if (tmp
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
]) {
721 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
722 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = tmp
;
727 update_specular(struct gl_context
* ctx
)
729 /* A hack to trigger the rebuild of the fragment program.
731 intel_context(ctx
)->NewGLState
|= _NEW_TEXTURE
;
735 i915LightModelfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
)
737 DBG("%s\n", __FUNCTION__
);
739 if (pname
== GL_LIGHT_MODEL_COLOR_CONTROL
) {
740 update_specular(ctx
);
745 i915ShadeModel(struct gl_context
* ctx
, GLenum mode
)
747 struct i915_context
*i915
= I915_CONTEXT(ctx
);
748 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
750 if (mode
== GL_SMOOTH
) {
751 i915
->state
.Ctx
[I915_CTXREG_LIS4
] &= ~(S4_FLATSHADE_ALPHA
|
753 S4_FLATSHADE_SPECULAR
);
756 i915
->state
.Ctx
[I915_CTXREG_LIS4
] |= (S4_FLATSHADE_ALPHA
|
758 S4_FLATSHADE_SPECULAR
);
762 /* =============================================================
765 * This empty function remains because _mesa_init_driver_state calls
766 * dd_function_table::Fogfv unconditionally. We have to have some function
767 * there so that it doesn't try to call a NULL pointer.
770 i915Fogfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
)
777 /* =============================================================
781 i915Enable(struct gl_context
* ctx
, GLenum cap
, GLboolean state
)
783 struct i915_context
*i915
= I915_CONTEXT(ctx
);
792 update_specular(ctx
);
796 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
798 dw
|= S6_ALPHA_TEST_ENABLE
;
800 dw
&= ~S6_ALPHA_TEST_ENABLE
;
801 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
802 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
803 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
808 i915EvalLogicOpBlendState(ctx
);
811 case GL_COLOR_LOGIC_OP
:
812 i915EvalLogicOpBlendState(ctx
);
814 /* Logicop doesn't seem to work at 16bpp:
816 if (ctx
->Visual
.rgbBits
== 16)
817 FALLBACK(&i915
->intel
, I915_FALLBACK_LOGICOP
, state
);
820 case GL_FRAGMENT_PROGRAM_ARB
:
824 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS5
];
826 dw
|= S5_COLOR_DITHER_ENABLE
;
828 dw
&= ~S5_COLOR_DITHER_ENABLE
;
829 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
]) {
830 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = dw
;
831 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
836 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
838 if (!ctx
->DrawBuffer
|| !ctx
->DrawBuffer
->Visual
.depthBits
)
842 dw
|= S6_DEPTH_TEST_ENABLE
;
844 dw
&= ~S6_DEPTH_TEST_ENABLE
;
845 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
846 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
847 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
850 i915DepthMask(ctx
, ctx
->Depth
.Mask
);
853 case GL_SCISSOR_TEST
:
854 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
856 i915
->state
.Buffer
[I915_DESTREG_SENABLE
] =
857 (_3DSTATE_SCISSOR_ENABLE_CMD
| ENABLE_SCISSOR_RECT
);
859 i915
->state
.Buffer
[I915_DESTREG_SENABLE
] =
860 (_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
864 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
866 dw
|= S4_LINE_ANTIALIAS_ENABLE
;
868 dw
&= ~S4_LINE_ANTIALIAS_ENABLE
;
869 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS4
]) {
870 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = dw
;
871 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
876 i915CullFaceFrontFace(ctx
, 0);
879 case GL_STENCIL_TEST
:
880 if (!ctx
->DrawBuffer
|| !ctx
->DrawBuffer
->Visual
.stencilBits
)
883 dw
= i915
->state
.Ctx
[I915_CTXREG_LIS5
];
885 dw
|= (S5_STENCIL_TEST_ENABLE
| S5_STENCIL_WRITE_ENABLE
);
887 dw
&= ~(S5_STENCIL_TEST_ENABLE
| S5_STENCIL_WRITE_ENABLE
);
888 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS5
]) {
889 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = dw
;
890 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
894 case GL_POLYGON_STIPPLE
:
895 /* The stipple command worked on my 855GM box, but not my 845G.
896 * I'll do more testing later to find out exactly which hardware
897 * supports it. Disabled for now.
899 if (i915
->intel
.hw_stipple
&&
900 i915
->intel
.reduced_primitive
== GL_TRIANGLES
) {
901 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
903 i915
->state
.Stipple
[I915_STPREG_ST1
] |= ST1_ENABLE
;
905 i915
->state
.Stipple
[I915_STPREG_ST1
] &= ~ST1_ENABLE
;
909 case GL_POLYGON_SMOOTH
:
912 case GL_POINT_SPRITE
:
913 /* Handle it at i915_update_sprite_point_enable () */
916 case GL_POINT_SMOOTH
:
926 i915_init_packets(struct i915_context
*i915
)
929 memset(&i915
->state
, 0, sizeof(i915
->state
));
933 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
934 I915_STATECHANGE(i915
, I915_UPLOAD_BLEND
);
935 /* Probably don't want to upload all this stuff every time one
938 i915
->state
.Ctx
[I915_CTXREG_LI
] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1
|
941 I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
942 i915
->state
.Ctx
[I915_CTXREG_LIS2
] = 0;
943 i915
->state
.Ctx
[I915_CTXREG_LIS4
] = 0;
944 i915
->state
.Ctx
[I915_CTXREG_LIS5
] = 0;
946 if (i915
->intel
.ctx
.Visual
.rgbBits
== 16)
947 i915
->state
.Ctx
[I915_CTXREG_LIS5
] |= S5_COLOR_DITHER_ENABLE
;
950 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = (S6_COLOR_WRITE_ENABLE
|
951 (2 << S6_TRISTRIP_PV_SHIFT
));
953 i915
->state
.Ctx
[I915_CTXREG_STATE4
] = (_3DSTATE_MODES_4_CMD
|
954 ENABLE_LOGIC_OP_FUNC
|
955 LOGIC_OP_FUNC(LOGICOP_COPY
) |
956 ENABLE_STENCIL_TEST_MASK
|
957 STENCIL_TEST_MASK(0xff) |
958 ENABLE_STENCIL_WRITE_MASK
|
959 STENCIL_WRITE_MASK(0xff));
961 i915
->state
.Blend
[I915_BLENDREG_IAB
] =
962 (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD
| IAB_MODIFY_ENABLE
|
963 IAB_MODIFY_FUNC
| IAB_MODIFY_SRC_FACTOR
| IAB_MODIFY_DST_FACTOR
);
965 i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR0
] =
966 _3DSTATE_CONST_BLEND_COLOR_CMD
;
967 i915
->state
.Blend
[I915_BLENDREG_BLENDCOLOR1
] = 0;
969 i915
->state
.Ctx
[I915_CTXREG_BF_STENCIL_MASKS
] =
970 _3DSTATE_BACKFACE_STENCIL_MASKS
|
971 BFM_ENABLE_STENCIL_TEST_MASK
|
972 BFM_ENABLE_STENCIL_WRITE_MASK
|
973 (0xff << BFM_STENCIL_WRITE_MASK_SHIFT
) |
974 (0xff << BFM_STENCIL_TEST_MASK_SHIFT
);
975 i915
->state
.Ctx
[I915_CTXREG_BF_STENCIL_OPS
] =
976 _3DSTATE_BACKFACE_STENCIL_OPS
|
977 BFO_ENABLE_STENCIL_REF
|
978 BFO_ENABLE_STENCIL_FUNCS
|
979 BFO_ENABLE_STENCIL_TWO_SIDE
;
983 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
984 i915
->state
.Stipple
[I915_STPREG_ST0
] = _3DSTATE_STIPPLE
;
988 i915
->state
.Buffer
[I915_DESTREG_DV0
] = _3DSTATE_DST_BUF_VARS_CMD
;
991 i915
->state
.Buffer
[I915_DESTREG_SENABLE
] =
992 (_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
993 i915
->state
.Buffer
[I915_DESTREG_SR0
] = _3DSTATE_SCISSOR_RECT_0_CMD
;
994 i915
->state
.Buffer
[I915_DESTREG_SR1
] = 0;
995 i915
->state
.Buffer
[I915_DESTREG_SR2
] = 0;
998 i915
->state
.RasterRules
[I915_RASTER_RULES
] = _3DSTATE_RASTER_RULES_CMD
|
999 ENABLE_POINT_RASTER_RULE
|
1000 OGL_POINT_RASTER_RULE
|
1001 ENABLE_LINE_STRIP_PROVOKE_VRTX
|
1002 ENABLE_TRI_FAN_PROVOKE_VRTX
|
1003 LINE_STRIP_PROVOKE_VRTX(1) |
1004 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D
| TEXKILL_4D
;
1008 I915_STATECHANGE(i915
, I915_UPLOAD_DEFAULTS
);
1009 i915
->state
.Default
[I915_DEFREG_C0
] = _3DSTATE_DEFAULT_DIFFUSE
;
1010 i915
->state
.Default
[I915_DEFREG_C1
] = 0;
1011 i915
->state
.Default
[I915_DEFREG_S0
] = _3DSTATE_DEFAULT_SPECULAR
;
1012 i915
->state
.Default
[I915_DEFREG_S1
] = 0;
1013 i915
->state
.Default
[I915_DEFREG_Z0
] = _3DSTATE_DEFAULT_Z
;
1014 i915
->state
.Default
[I915_DEFREG_Z1
] = 0;
1019 /* These will be emitted every at the head of every buffer, unless
1020 * we get hardware contexts working.
1022 i915
->state
.active
= (I915_UPLOAD_PROGRAM
|
1023 I915_UPLOAD_STIPPLE
|
1026 I915_UPLOAD_BUFFERS
|
1027 I915_UPLOAD_INVARIENT
|
1028 I915_UPLOAD_RASTER_RULES
);
1032 i915_update_provoking_vertex(struct gl_context
* ctx
)
1034 struct i915_context
*i915
= I915_CONTEXT(ctx
);
1036 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
1037 i915
->state
.Ctx
[I915_CTXREG_LIS6
] &= ~(S6_TRISTRIP_PV_MASK
);
1039 I915_STATECHANGE(i915
, I915_UPLOAD_RASTER_RULES
);
1040 i915
->state
.RasterRules
[I915_RASTER_RULES
] &= ~(LINE_STRIP_PROVOKE_VRTX_MASK
|
1041 TRI_FAN_PROVOKE_VRTX_MASK
);
1044 if (ctx
->Light
.ProvokingVertex
== GL_LAST_VERTEX_CONVENTION
) {
1045 i915
->state
.RasterRules
[I915_RASTER_RULES
] |= (LINE_STRIP_PROVOKE_VRTX(1) |
1046 TRI_FAN_PROVOKE_VRTX(2));
1047 i915
->state
.Ctx
[I915_CTXREG_LIS6
] |= (2 << S6_TRISTRIP_PV_SHIFT
);
1049 i915
->state
.RasterRules
[I915_RASTER_RULES
] |= (LINE_STRIP_PROVOKE_VRTX(0) |
1050 TRI_FAN_PROVOKE_VRTX(1));
1051 i915
->state
.Ctx
[I915_CTXREG_LIS6
] |= (0 << S6_TRISTRIP_PV_SHIFT
);
1055 /* Fallback to swrast for select and feedback.
1058 i915RenderMode(struct gl_context
*ctx
, GLenum mode
)
1060 struct intel_context
*intel
= intel_context(ctx
);
1061 FALLBACK(intel
, INTEL_FALLBACK_RENDERMODE
, (mode
!= GL_RENDER
));
1065 i915InitStateFunctions(struct dd_function_table
*functions
)
1067 functions
->AlphaFunc
= i915AlphaFunc
;
1068 functions
->BlendColor
= i915BlendColor
;
1069 functions
->BlendEquationSeparate
= i915BlendEquationSeparate
;
1070 functions
->BlendFuncSeparate
= i915BlendFuncSeparate
;
1071 functions
->ColorMask
= i915ColorMask
;
1072 functions
->CullFace
= i915CullFaceFrontFace
;
1073 functions
->DepthFunc
= i915DepthFunc
;
1074 functions
->DepthMask
= i915DepthMask
;
1075 functions
->Enable
= i915Enable
;
1076 functions
->Fogfv
= i915Fogfv
;
1077 functions
->FrontFace
= i915CullFaceFrontFace
;
1078 functions
->LightModelfv
= i915LightModelfv
;
1079 functions
->LineWidth
= i915LineWidth
;
1080 functions
->LogicOpcode
= i915LogicOp
;
1081 functions
->PointSize
= i915PointSize
;
1082 functions
->PointParameterfv
= i915PointParameterfv
;
1083 functions
->PolygonStipple
= i915PolygonStipple
;
1084 functions
->RenderMode
= i915RenderMode
;
1085 functions
->Scissor
= i915Scissor
;
1086 functions
->ShadeModel
= i915ShadeModel
;
1087 functions
->StencilFuncSeparate
= i915StencilFuncSeparate
;
1088 functions
->StencilMaskSeparate
= i915StencilMaskSeparate
;
1089 functions
->StencilOpSeparate
= i915StencilOpSeparate
;
1090 functions
->DepthRange
= i915DepthRange
;
1095 i915InitState(struct i915_context
*i915
)
1097 struct gl_context
*ctx
= &i915
->intel
.ctx
;
1099 i915_init_packets(i915
);
1101 _mesa_init_driver_state(ctx
);