Merge branch 'mesa_7_5_branch'
[mesa.git] / src / mesa / drivers / dri / i915 / i915_tex_layout.c
1 /**************************************************************************
2 *
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /** @file i915_tex_layout.c
29 * Code to layout images in a mipmap tree for i830M-GM915 and G945 and beyond.
30 */
31
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex_layout.h"
34 #include "main/macros.h"
35 #include "intel_context.h"
36
37 #define FILE_DEBUG_FLAG DEBUG_TEXTURE
38
39 static GLint initial_offsets[6][2] = {
40 [FACE_POS_X] = {0, 0},
41 [FACE_POS_Y] = {1, 0},
42 [FACE_POS_Z] = {1, 1},
43 [FACE_NEG_X] = {0, 2},
44 [FACE_NEG_Y] = {1, 2},
45 [FACE_NEG_Z] = {1, 3},
46 };
47
48
49 static GLint step_offsets[6][2] = {
50 [FACE_POS_X] = {0, 2},
51 [FACE_POS_Y] = {-1, 2},
52 [FACE_POS_Z] = {-1, 1},
53 [FACE_NEG_X] = {0, 2},
54 [FACE_NEG_Y] = {-1, 2},
55 [FACE_NEG_Z] = {-1, 1},
56 };
57
58
59 static GLint bottom_offsets[6] = {
60 [FACE_POS_X] = 16 + 0 * 8,
61 [FACE_POS_Y] = 16 + 1 * 8,
62 [FACE_POS_Z] = 16 + 2 * 8,
63 [FACE_NEG_X] = 16 + 3 * 8,
64 [FACE_NEG_Y] = 16 + 4 * 8,
65 [FACE_NEG_Z] = 16 + 5 * 8,
66 };
67
68
69 /**
70 * Cube texture map layout for i830M-GM915.
71 *
72 * Hardware layout looks like:
73 *
74 * +-------+-------+
75 * | | |
76 * | | |
77 * | | |
78 * | +x | +y |
79 * | | |
80 * | | |
81 * | | |
82 * | | |
83 * +---+---+-------+
84 * | | | |
85 * | +x| +y| |
86 * | | | |
87 * | | | |
88 * +-+-+---+ +z |
89 * | | | | |
90 * +-+-+ +z| |
91 * | | | |
92 * +-+-+---+-------+
93 * | | |
94 * | | |
95 * | | |
96 * | -x | -y |
97 * | | |
98 * | | |
99 * | | |
100 * | | |
101 * +---+---+-------+
102 * | | | |
103 * | -x| -y| |
104 * | | | |
105 * | | | |
106 * +-+-+---+ -z |
107 * | | | | |
108 * +-+-+ -z| |
109 * | | | |
110 * +-+---+-------+
111 *
112 */
113 static void
114 i915_miptree_layout_cube(struct intel_context *intel,
115 struct intel_mipmap_tree * mt,
116 uint32_t tiling)
117 {
118 const GLuint dim = mt->width0;
119 GLuint face;
120 GLuint lvlWidth = mt->width0, lvlHeight = mt->height0;
121 GLint level;
122
123 assert(lvlWidth == lvlHeight); /* cubemap images are square */
124
125 /* double pitch for cube layouts */
126 mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, dim * 2);
127 mt->total_height = dim * 4;
128
129 for (level = mt->first_level; level <= mt->last_level; level++) {
130 intel_miptree_set_level_info(mt, level, 6,
131 0, 0,
132 /*OLD: mt->pitch, mt->total_height,*/
133 lvlWidth, lvlHeight,
134 1);
135 lvlWidth /= 2;
136 lvlHeight /= 2;
137 }
138
139 for (face = 0; face < 6; face++) {
140 GLuint x = initial_offsets[face][0] * dim;
141 GLuint y = initial_offsets[face][1] * dim;
142 GLuint d = dim;
143
144 for (level = mt->first_level; level <= mt->last_level; level++) {
145 intel_miptree_set_image_offset(mt, level, face, x, y);
146
147 if (d == 0)
148 _mesa_printf("cube mipmap %d/%d (%d..%d) is 0x0\n",
149 face, level, mt->first_level, mt->last_level);
150
151 d >>= 1;
152 x += step_offsets[face][0] * d;
153 y += step_offsets[face][1] * d;
154 }
155 }
156 }
157
158 static void
159 i915_miptree_layout_3d(struct intel_context *intel,
160 struct intel_mipmap_tree * mt,
161 uint32_t tiling)
162 {
163 GLuint width = mt->width0;
164 GLuint height = mt->height0;
165 GLuint depth = mt->depth0;
166 GLuint stack_height = 0;
167 GLint level;
168
169 /* Calculate the size of a single slice. */
170 mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
171
172 /* XXX: hardware expects/requires 9 levels at minimum. */
173 for (level = mt->first_level; level <= MAX2(8, mt->last_level); level++) {
174 intel_miptree_set_level_info(mt, level, depth, 0, mt->total_height,
175 width, height, depth);
176
177 stack_height += MAX2(2, height);
178
179 width = minify(width);
180 height = minify(height);
181 depth = minify(depth);
182 }
183
184 /* Fixup depth image_offsets: */
185 depth = mt->depth0;
186 for (level = mt->first_level; level <= mt->last_level; level++) {
187 GLuint i;
188 for (i = 0; i < depth; i++) {
189 intel_miptree_set_image_offset(mt, level, i,
190 0, i * stack_height);
191 }
192
193 depth = minify(depth);
194 }
195
196 /* Multiply slice size by texture depth for total size. It's
197 * remarkable how wasteful of memory the i915 texture layouts
198 * are. They are largely fixed in the i945.
199 */
200 mt->total_height = stack_height * mt->depth0;
201 }
202
203 static void
204 i915_miptree_layout_2d(struct intel_context *intel,
205 struct intel_mipmap_tree * mt,
206 uint32_t tiling)
207 {
208 GLuint width = mt->width0;
209 GLuint height = mt->height0;
210 GLuint img_height;
211 GLint level;
212
213 mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
214 mt->total_height = 0;
215
216 for (level = mt->first_level; level <= mt->last_level; level++) {
217 intel_miptree_set_level_info(mt, level, 1,
218 0, mt->total_height,
219 width, height, 1);
220
221 if (mt->compressed)
222 img_height = MAX2(1, height / 4);
223 else
224 img_height = (MAX2(2, height) + 1) & ~1;
225
226 mt->total_height += img_height;
227
228 width = minify(width);
229 height = minify(height);
230 }
231 }
232
233 GLboolean
234 i915_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt,
235 uint32_t tiling)
236 {
237 switch (mt->target) {
238 case GL_TEXTURE_CUBE_MAP:
239 i915_miptree_layout_cube(intel, mt, tiling);
240 break;
241 case GL_TEXTURE_3D:
242 i915_miptree_layout_3d(intel, mt, tiling);
243 break;
244 case GL_TEXTURE_1D:
245 case GL_TEXTURE_2D:
246 case GL_TEXTURE_RECTANGLE_ARB:
247 i915_miptree_layout_2d(intel, mt, tiling);
248 break;
249 default:
250 _mesa_problem(NULL, "Unexpected tex target in i915_miptree_layout()");
251 break;
252 }
253
254 DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
255 mt->pitch,
256 mt->total_height, mt->cpp, mt->pitch * mt->total_height * mt->cpp);
257
258 return GL_TRUE;
259 }
260
261
262 /**
263 * Cube texture map layout for GM945 and later.
264 *
265 * The hardware layout looks like the 830-915 layout, except for the small
266 * sizes. A zoomed in view of the layout for 945 is:
267 *
268 * +-------+-------+
269 * | 8x8 | 8x8 |
270 * | | |
271 * | | |
272 * | +x | +y |
273 * | | |
274 * | | |
275 * | | |
276 * | | |
277 * +---+---+-------+
278 * |4x4| | 8x8 |
279 * | +x| | |
280 * | | | |
281 * | | | |
282 * +---+ | +z |
283 * |4x4| | |
284 * | +y| | |
285 * | | | |
286 * +---+ +-------+
287 *
288 * ...
289 *
290 * +-------+-------+
291 * | 8x8 | 8x8 |
292 * | | |
293 * | | |
294 * | -x | -y |
295 * | | |
296 * | | |
297 * | | |
298 * | | |
299 * +---+---+-------+
300 * |4x4| | 8x8 |
301 * | -x| | |
302 * | | | |
303 * | | | |
304 * +---+ | -z |
305 * |4x4| | |
306 * | -y| | |
307 * | | | |
308 * +---+ +---+---+---+---+---+---+---+---+---+
309 * |4x4| |4x4| |2x2| |2x2| |2x2| |2x2|
310 * | +z| | -z| | +x| | +y| | +z| | -x| ...
311 * | | | | | | | | | | | |
312 * +---+ +---+ +---+ +---+ +---+ +---+
313 *
314 * The bottom row continues with the remaining 2x2 then the 1x1 mip contents
315 * in order, with each of them aligned to a 8x8 block boundary. Thus, for
316 * 32x32 cube maps and smaller, the bottom row layout is going to dictate the
317 * pitch of the tree. For a tree with 4x4 images, the pitch is at least
318 * 14 * 8 = 112 texels, for 2x2 it is at least 12 * 8 texels, and for 1x1
319 * it is 6 * 8 texels.
320 */
321
322 static void
323 i945_miptree_layout_cube(struct intel_context *intel,
324 struct intel_mipmap_tree * mt,
325 uint32_t tiling)
326 {
327 const GLuint dim = mt->width0;
328 GLuint face;
329 GLuint lvlWidth = mt->width0, lvlHeight = mt->height0;
330 GLint level;
331
332 assert(lvlWidth == lvlHeight); /* cubemap images are square */
333
334 /* Depending on the size of the largest images, pitch can be
335 * determined either by the old-style packing of cubemap faces,
336 * or the final row of 4x4, 2x2 and 1x1 faces below this.
337 */
338 if (dim > 32)
339 mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, dim * 2);
340 else
341 mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, 14 * 8);
342
343 if (dim >= 4)
344 mt->total_height = dim * 4 + 4;
345 else
346 mt->total_height = 4;
347
348 /* Set all the levels to effectively occupy the whole rectangular region. */
349 for (level = mt->first_level; level <= mt->last_level; level++) {
350 intel_miptree_set_level_info(mt, level, 6,
351 0, 0,
352 lvlWidth, lvlHeight, 1);
353 lvlWidth /= 2;
354 lvlHeight /= 2;
355 }
356
357 for (face = 0; face < 6; face++) {
358 GLuint x = initial_offsets[face][0] * dim;
359 GLuint y = initial_offsets[face][1] * dim;
360 GLuint d = dim;
361
362 if (dim == 4 && face >= 4) {
363 y = mt->total_height - 4;
364 x = (face - 4) * 8;
365 } else if (dim < 4 && (face > 0 || mt->first_level > 0)) {
366 y = mt->total_height - 4;
367 x = face * 8;
368 }
369
370 for (level = mt->first_level; level <= mt->last_level; level++) {
371 intel_miptree_set_image_offset(mt, level, face, x, y);
372
373 d >>= 1;
374
375 switch (d) {
376 case 4:
377 switch (face) {
378 case FACE_POS_X:
379 case FACE_NEG_X:
380 x += step_offsets[face][0] * d;
381 y += step_offsets[face][1] * d;
382 break;
383 case FACE_POS_Y:
384 case FACE_NEG_Y:
385 y += 12;
386 x -= 8;
387 break;
388 case FACE_POS_Z:
389 case FACE_NEG_Z:
390 y = mt->total_height - 4;
391 x = (face - 4) * 8;
392 break;
393 }
394 break;
395
396 case 2:
397 y = mt->total_height - 4;
398 x = bottom_offsets[face];
399 break;
400
401 case 1:
402 x += 48;
403 break;
404
405 default:
406 x += step_offsets[face][0] * d;
407 y += step_offsets[face][1] * d;
408 break;
409 }
410 }
411 }
412 }
413
414 static void
415 i945_miptree_layout_3d(struct intel_context *intel,
416 struct intel_mipmap_tree * mt,
417 uint32_t tiling)
418 {
419 GLuint width = mt->width0;
420 GLuint height = mt->height0;
421 GLuint depth = mt->depth0;
422 GLuint pack_x_pitch, pack_x_nr;
423 GLuint pack_y_pitch;
424 GLuint level;
425
426 mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
427 mt->total_height = 0;
428
429 pack_y_pitch = MAX2(mt->height0, 2);
430 pack_x_pitch = mt->pitch;
431 pack_x_nr = 1;
432
433 for (level = mt->first_level; level <= mt->last_level; level++) {
434 GLint x = 0;
435 GLint y = 0;
436 GLint q, j;
437
438 intel_miptree_set_level_info(mt, level, depth,
439 0, mt->total_height,
440 width, height, depth);
441
442 for (q = 0; q < depth;) {
443 for (j = 0; j < pack_x_nr && q < depth; j++, q++) {
444 intel_miptree_set_image_offset(mt, level, q, x, y);
445 x += pack_x_pitch;
446 }
447
448 x = 0;
449 y += pack_y_pitch;
450 }
451
452 mt->total_height += y;
453
454 if (pack_x_pitch > 4) {
455 pack_x_pitch >>= 1;
456 pack_x_nr <<= 1;
457 assert(pack_x_pitch * pack_x_nr <= mt->pitch);
458 }
459
460 if (pack_y_pitch > 2) {
461 pack_y_pitch >>= 1;
462 }
463
464 width = minify(width);
465 height = minify(height);
466 depth = minify(depth);
467 }
468 }
469
470 GLboolean
471 i945_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt,
472 uint32_t tiling)
473 {
474 switch (mt->target) {
475 case GL_TEXTURE_CUBE_MAP:
476 if (mt->compressed)
477 i945_miptree_layout_cube(intel, mt, tiling);
478 else
479 i915_miptree_layout_cube(intel, mt, tiling);
480 break;
481 case GL_TEXTURE_3D:
482 i945_miptree_layout_3d(intel, mt, tiling);
483 break;
484 case GL_TEXTURE_1D:
485 case GL_TEXTURE_2D:
486 case GL_TEXTURE_RECTANGLE_ARB:
487 i945_miptree_layout_2d(intel, mt, tiling);
488 break;
489 default:
490 _mesa_problem(NULL, "Unexpected tex target in i945_miptree_layout()");
491 break;
492 }
493
494 DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
495 mt->pitch,
496 mt->total_height, mt->cpp, mt->pitch * mt->total_height * mt->cpp);
497
498 return GL_TRUE;
499 }