src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "glheader.h"
  31 #include "mtypes.h"
  32 #include "imports.h"
  33 #include "macros.h"
  34 #include "colormac.h"
  35
  36 #include "tnl/t_context.h"
  37 #include "tnl/t_vertex.h"
  38
  39 #include "intel_batchbuffer.h"
  40 #include "intel_tex.h"
  41 #include "intel_regions.h"
  42
  43 #include "i915_reg.h"
  44 #include "i915_context.h"
  45
  46 static void
  47 i915_render_prevalidate(struct intel_context *intel)
  48 {
  49    struct i915_context *i915 = i915_context(&intel->ctx);
  50
  51    if (!intel->Fallback)
  52        i915ValidateFragmentProgram(i915);
  53 }
  54
  55 static void
  56 i915_render_start(struct intel_context *intel)
  57 {
  58 }
  59
  60
  61 static void
  62 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  63 {
  64    struct i915_context *i915 = i915_context(&intel->ctx);
  65    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  66
  67    st1 &= ~ST1_ENABLE;
  68
  69    switch (rprim) {
  70    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  71    case GL_TRIANGLES:
  72       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  73          st1 |= ST1_ENABLE;
  74       break;
  75    case GL_LINES:
  76    case GL_POINTS:
  77    default:
  78       break;
  79    }
  80
  81    i915->intel.reduced_primitive = rprim;
  82
  83    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  84       INTEL_FIREVERTICES(intel);
  85
  86       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  87       i915->state.Stipple[I915_STPREG_ST1] = st1;
  88    }
  89 }
  90
  91
  92 /* Pull apart the vertex format registers and figure out how large a
  93  * vertex is supposed to be.
  94  */
  95 static GLboolean
  96 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
  97 {
  98    struct i915_context *i915 = i915_context(&intel->ctx);
  99    int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
 100    int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
 101    int i, sz = 0;
 102
 103    switch (lis4 & S4_VFMT_XYZW_MASK) {
 104    case S4_VFMT_XY:
 105       sz = 2;
 106       break;
 107    case S4_VFMT_XYZ:
 108       sz = 3;
 109       break;
 110    case S4_VFMT_XYW:
 111       sz = 3;
 112       break;
 113    case S4_VFMT_XYZW:
 114       sz = 4;
 115       break;
 116    default:
 117       fprintf(stderr, "no xyzw specified\n");
 118       return 0;
 119    }
 120
 121    if (lis4 & S4_VFMT_SPEC_FOG)
 122       sz++;
 123    if (lis4 & S4_VFMT_COLOR)
 124       sz++;
 125    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 126       sz++;
 127    if (lis4 & S4_VFMT_POINT_WIDTH)
 128       sz++;
 129    if (lis4 & S4_VFMT_FOG_PARAM)
 130       sz++;
 131
 132    for (i = 0; i < 8; i++) {
 133       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 134       case TEXCOORDFMT_2D:
 135          sz += 2;
 136          break;
 137       case TEXCOORDFMT_3D:
 138          sz += 3;
 139          break;
 140       case TEXCOORDFMT_4D:
 141          sz += 4;
 142          break;
 143       case TEXCOORDFMT_1D:
 144          sz += 1;
 145          break;
 146       case TEXCOORDFMT_2D_16:
 147          sz += 1;
 148          break;
 149       case TEXCOORDFMT_4D_16:
 150          sz += 2;
 151          break;
 152       case TEXCOORDFMT_NOT_PRESENT:
 153          break;
 154       default:
 155          fprintf(stderr, "bad texcoord fmt %d\n", i);
 156          return GL_FALSE;
 157       }
 158       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 159    }
 160
 161    if (sz != expected)
 162       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 163
 164    return sz == expected;
 165 }
 166
 167
 168 static void
 169 i915_emit_invarient_state(struct intel_context *intel)
 170 {
 171    BATCH_LOCALS;
 172
 173    BEGIN_BATCH(200, IGNORE_CLIPRECTS);
 174
 175    OUT_BATCH(_3DSTATE_AA_CMD |
 176              AA_LINE_ECAAR_WIDTH_ENABLE |
 177              AA_LINE_ECAAR_WIDTH_1_0 |
 178              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 179
 180    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 181    OUT_BATCH(0);
 182
 183    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 184    OUT_BATCH(0);
 185
 186    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 187    OUT_BATCH(0);
 188
 189    /* Don't support texture crossbar yet */
 190    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 191              CSB_TCB(0, 0) |
 192              CSB_TCB(1, 1) |
 193              CSB_TCB(2, 2) |
 194              CSB_TCB(3, 3) |
 195              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 196
 197    OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 198              ENABLE_POINT_RASTER_RULE |
 199              OGL_POINT_RASTER_RULE |
 200              ENABLE_LINE_STRIP_PROVOKE_VRTX |
 201              ENABLE_TRI_FAN_PROVOKE_VRTX |
 202              LINE_STRIP_PROVOKE_VRTX(1) |
 203              TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
 204
 205    /* Need to initialize this to zero.
 206     */
 207    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 208    OUT_BATCH(0);
 209
 210    /* XXX: Use this */
 211    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 212
 213    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 214    OUT_BATCH(0);
 215    OUT_BATCH(0);
 216
 217    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 218
 219    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 220    OUT_BATCH(0);
 221
 222
 223    /* Don't support twosided stencil yet */
 224    OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
 225    OUT_BATCH(0);
 226
 227    ADVANCE_BATCH();
 228 }
 229
 230
 231 #define emit(intel, state, size )                    \
 232    intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
 233
 234 static GLuint
 235 get_dirty(struct i915_hw_state *state)
 236 {
 237    GLuint dirty;
 238
 239    /* Workaround the multitex hang - if one texture unit state is
 240     * modified, emit all texture units.
 241     */
 242    dirty = state->active & ~state->emitted;
 243    if (dirty & I915_UPLOAD_TEX_ALL)
 244       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 245    dirty = state->active & ~state->emitted;
 246    return dirty;
 247 }
 248
 249
 250 static GLuint
 251 get_state_size(struct i915_hw_state *state)
 252 {
 253    GLuint dirty = get_dirty(state);
 254    GLuint i;
 255    GLuint sz = 0;
 256
 257    if (dirty & I915_UPLOAD_INVARIENT)
 258       sz += 30 * 4;
 259
 260    if (dirty & I915_UPLOAD_CTX)
 261       sz += sizeof(state->Ctx);
 262
 263    if (dirty & I915_UPLOAD_BUFFERS)
 264       sz += sizeof(state->Buffer);
 265
 266    if (dirty & I915_UPLOAD_STIPPLE)
 267       sz += sizeof(state->Stipple);
 268
 269    if (dirty & I915_UPLOAD_FOG)
 270       sz += sizeof(state->Fog);
 271
 272    if (dirty & I915_UPLOAD_TEX_ALL) {
 273       int nr = 0;
 274       for (i = 0; i < I915_TEX_UNITS; i++)
 275          if (dirty & I915_UPLOAD_TEX(i))
 276             nr++;
 277
 278       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 279    }
 280
 281    if (dirty & I915_UPLOAD_CONSTANTS)
 282       sz += state->ConstantSize * sizeof(GLuint);
 283
 284    if (dirty & I915_UPLOAD_PROGRAM)
 285       sz += state->ProgramSize * sizeof(GLuint);
 286
 287    return sz;
 288 }
 289
 290 /* Push the state into the sarea and/or texture memory.
 291  */
 292 static void
 293 i915_emit_state(struct intel_context *intel)
 294 {
 295    struct i915_context *i915 = i915_context(&intel->ctx);
 296    struct i915_hw_state *state = i915->current;
 297    int i;
 298    int ret, count;
 299    GLuint dirty;
 300    BATCH_LOCALS;
 301
 302    /* We don't hold the lock at this point, so want to make sure that
 303     * there won't be a buffer wrap between the state emits and the primitive
 304     * emit header.
 305     *
 306     * It might be better to talk about explicit places where
 307     * scheduling is allowed, rather than assume that it is whenever a
 308     * batchbuffer fills up.
 309     *
 310     * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
 311     * will be emitted under.
 312     */
 313    intel_batchbuffer_require_space(intel->batch, get_state_size(state) + 8,
 314                                    LOOP_CLIPRECTS);
 315    count = 0;
 316  again:
 317    dirty = get_dirty(state);
 318
 319    ret = 0;
 320    if (dirty & I915_UPLOAD_BUFFERS) {
 321      ret |= dri_bufmgr_check_aperture_space(state->draw_region->buffer);
 322      ret |= dri_bufmgr_check_aperture_space(state->depth_region->buffer);
 323    }
 324
 325    if (dirty & I915_UPLOAD_TEX_ALL) {
 326      for (i = 0; i < I915_TEX_UNITS; i++)
 327        if (dirty & I915_UPLOAD_TEX(i)) {
 328            if (state->tex_buffer[i]) {
 329                ret |= dri_bufmgr_check_aperture_space(state->tex_buffer[i]);
 330            }
 331        }
 332    }
 333    if (ret) {
 334        if (count == 0) {
 335            count++;
 336            intel_batchbuffer_flush(intel->batch);
 337            goto again;
 338        } else {
 339            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 340            assert(0);
 341        }
 342    }
 343
 344    /* work out list of buffers to emit */
 345
 346    /* Do this here as we may have flushed the batchbuffer above,
 347     * causing more state to be dirty!
 348     */
 349    dirty = get_dirty(state);
 350    state->emitted |= dirty;
 351    assert(get_dirty(state) == 0);
 352
 353    if (INTEL_DEBUG & DEBUG_STATE)
 354       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 355
 356    if (dirty & I915_UPLOAD_INVARIENT) {
 357       if (INTEL_DEBUG & DEBUG_STATE)
 358          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 359       i915_emit_invarient_state(intel);
 360    }
 361
 362    if (dirty & I915_UPLOAD_CTX) {
 363       if (INTEL_DEBUG & DEBUG_STATE)
 364          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 365
 366       emit(intel, state->Ctx, sizeof(state->Ctx));
 367    }
 368
 369    if (dirty & I915_UPLOAD_BUFFERS) {
 370       if (INTEL_DEBUG & DEBUG_STATE)
 371          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 372       BEGIN_BATCH(I915_DEST_SETUP_SIZE + 2, IGNORE_CLIPRECTS);
 373       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 374       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 375       OUT_RELOC(state->draw_region->buffer,
 376                 DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
 377                 state->draw_region->draw_offset);
 378
 379       if (state->depth_region) {
 380          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 381          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 382          OUT_RELOC(state->depth_region->buffer,
 383                    DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
 384                    state->depth_region->draw_offset);
 385       }
 386
 387       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 388       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 389       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 390       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 391       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 392       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 393       ADVANCE_BATCH();
 394    }
 395
 396    if (dirty & I915_UPLOAD_STIPPLE) {
 397       if (INTEL_DEBUG & DEBUG_STATE)
 398          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 399       emit(intel, state->Stipple, sizeof(state->Stipple));
 400    }
 401
 402    if (dirty & I915_UPLOAD_FOG) {
 403       if (INTEL_DEBUG & DEBUG_STATE)
 404          fprintf(stderr, "I915_UPLOAD_FOG:\n");
 405       emit(intel, state->Fog, sizeof(state->Fog));
 406    }
 407
 408    /* Combine all the dirty texture state into a single command to
 409     * avoid lockups on I915 hardware.
 410     */
 411    if (dirty & I915_UPLOAD_TEX_ALL) {
 412       int nr = 0;
 413
 414       for (i = 0; i < I915_TEX_UNITS; i++)
 415          if (dirty & I915_UPLOAD_TEX(i))
 416             nr++;
 417
 418       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 419       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 420       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 421       for (i = 0; i < I915_TEX_UNITS; i++)
 422          if (dirty & I915_UPLOAD_TEX(i)) {
 423
 424             if (state->tex_buffer[i]) {
 425                OUT_RELOC(state->tex_buffer[i],
 426                          DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
 427                          state->tex_offset[i]);
 428             }
 429             else if (state == &i915->meta) {
 430                assert(i == 0);
 431                OUT_BATCH(0);
 432             }
 433             else {
 434                OUT_BATCH(state->tex_offset[i]);
 435             }
 436
 437             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 438             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 439          }
 440       ADVANCE_BATCH();
 441
 442       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 443       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 444       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 445       for (i = 0; i < I915_TEX_UNITS; i++)
 446          if (dirty & I915_UPLOAD_TEX(i)) {
 447             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 448             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 449             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 450          }
 451       ADVANCE_BATCH();
 452    }
 453
 454    if (dirty & I915_UPLOAD_CONSTANTS) {
 455       if (INTEL_DEBUG & DEBUG_STATE)
 456          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 457       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 458    }
 459
 460    if (dirty & I915_UPLOAD_PROGRAM) {
 461       if (state->ProgramSize) {
 462          if (INTEL_DEBUG & DEBUG_STATE)
 463             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 464
 465          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 466
 467          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 468          if (INTEL_DEBUG & DEBUG_STATE)
 469             i915_disassemble_program(state->Program, state->ProgramSize);
 470       }
 471    }
 472
 473    intel->batch->dirty_state &= ~dirty;
 474    assert(get_dirty(state) == 0);
 475    assert((intel->batch->dirty_state & (1<<1)) == 0);
 476 }
 477
 478 static void
 479 i915_destroy_context(struct intel_context *intel)
 480 {
 481    GLuint i;
 482    struct i915_context *i915 = i915_context(&intel->ctx);
 483
 484    for (i = 0; i < I915_TEX_UNITS; i++) {
 485       if (i915->state.tex_buffer[i] != NULL) {
 486          dri_bo_unreference(i915->state.tex_buffer[i]);
 487          i915->state.tex_buffer[i] = NULL;
 488       }
 489    }
 490
 491    _tnl_free_vertices(&intel->ctx);
 492 }
 493
 494
 495 /**
 496  * Set the drawing regions for the color and depth/stencil buffers.
 497  * This involves setting the pitch, cpp and buffer ID/location.
 498  * Also set pixel format for color and Z rendering
 499  * Used for setting both regular and meta state.
 500  */
 501 void
 502 i915_state_draw_region(struct intel_context *intel,
 503                        struct i915_hw_state *state,
 504                        struct intel_region *color_region,
 505                        struct intel_region *depth_region)
 506 {
 507    struct i915_context *i915 = i915_context(&intel->ctx);
 508    GLuint value;
 509
 510    ASSERT(state == &i915->state || state == &i915->meta);
 511
 512    if (state->draw_region != color_region) {
 513       intel_region_release(&state->draw_region);
 514       intel_region_reference(&state->draw_region, color_region);
 515    }
 516    if (state->depth_region != depth_region) {
 517       intel_region_release(&state->depth_region);
 518       intel_region_reference(&state->depth_region, depth_region);
 519    }
 520
 521    /*
 522     * Set stride/cpp values
 523     */
 524    if (color_region) {
 525       state->Buffer[I915_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 526       state->Buffer[I915_DESTREG_CBUFADDR1] =
 527          (BUF_3D_ID_COLOR_BACK |
 528           BUF_3D_PITCH(color_region->pitch * color_region->cpp) |
 529           BUF_3D_USE_FENCE);
 530    }
 531
 532    if (depth_region) {
 533       state->Buffer[I915_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 534       state->Buffer[I915_DESTREG_DBUFADDR1] =
 535          (BUF_3D_ID_DEPTH |
 536           BUF_3D_PITCH(depth_region->pitch * depth_region->cpp) |
 537           BUF_3D_USE_FENCE);
 538    }
 539
 540    /*
 541     * Compute/set I915_DESTREG_DV1 value
 542     */
 543    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 544             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 545             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 546    if (color_region && color_region->cpp == 4) {
 547       value |= DV_PF_8888;
 548    }
 549    else {
 550       value |= (DITHER_FULL_ALWAYS | DV_PF_565);
 551    }
 552    if (depth_region && depth_region->cpp == 4) {
 553       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 554    }
 555    else {
 556       value |= DEPTH_FRMT_16_FIXED;
 557    }
 558    state->Buffer[I915_DESTREG_DV1] = value;
 559
 560    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 561 }
 562
 563
 564 static void
 565 i915_set_draw_region(struct intel_context *intel,
 566                      struct intel_region *color_regions[],
 567                      struct intel_region *depth_region,
 568                      GLuint num_regions)
 569 {
 570    struct i915_context *i915 = i915_context(&intel->ctx);
 571    i915_state_draw_region(intel, &i915->state, color_regions[0], depth_region);
 572 }
 573
 574
 575
 576 static void
 577 i915_new_batch(struct intel_context *intel)
 578 {
 579    struct i915_context *i915 = i915_context(&intel->ctx);
 580
 581    /* Mark all state as needing to be emitted when starting a new batchbuffer.
 582     * Using hardware contexts would be an alternative, but they have some
 583     * difficulties associated with them (physical address requirements).
 584     */
 585    i915->state.emitted = 0;
 586
 587    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 588    assert(!intel->no_batch_wrap);
 589 }
 590
 591 static GLuint
 592 i915_flush_cmd(void)
 593 {
 594    return MI_FLUSH | FLUSH_MAP_CACHE;
 595 }
 596
 597 static void
 598 i915_assert_not_dirty( struct intel_context *intel )
 599 {
 600    struct i915_context *i915 = i915_context(&intel->ctx);
 601    struct i915_hw_state *state = i915->current;
 602    GLuint dirty = get_dirty(state);
 603    assert(!dirty);
 604 }
 605
 606 static void
 607 i915_note_unlock( struct intel_context *intel )
 608 {
 609     /* nothing */
 610 }
 611
 612
 613 void
 614 i915InitVtbl(struct i915_context *i915)
 615 {
 616    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 617    i915->intel.vtbl.destroy = i915_destroy_context;
 618    i915->intel.vtbl.emit_state = i915_emit_state;
 619    i915->intel.vtbl.new_batch = i915_new_batch;
 620    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 621    i915->intel.vtbl.render_start = i915_render_start;
 622    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 623    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 624    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 625    i915->intel.vtbl.flush_cmd = i915_flush_cmd;
 626    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 627    i915->intel.vtbl.note_unlock = i915_note_unlock;
 628 }