src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "main/glheader.h"
  31 #include "main/mtypes.h"
  32 #include "main/imports.h"
  33 #include "main/macros.h"
  34 #include "main/colormac.h"
  35 #include "main/texformat.h"
  36
  37 #include "tnl/t_context.h"
  38 #include "tnl/t_vertex.h"
  39
  40 #include "intel_batchbuffer.h"
  41 #include "intel_tex.h"
  42 #include "intel_regions.h"
  43 #include "intel_tris.h"
  44 #include "intel_fbo.h"
  45
  46 #include "i915_reg.h"
  47 #include "i915_context.h"
  48
  49 #include "glapi/glapi.h"
  50
  51 static void
  52 i915_render_prevalidate(struct intel_context *intel)
  53 {
  54    struct i915_context *i915 = i915_context(&intel->ctx);
  55
  56    if (!intel->Fallback)
  57        i915ValidateFragmentProgram(i915);
  58 }
  59
  60 static void
  61 i915_render_start(struct intel_context *intel)
  62 {
  63 }
  64
  65
  66 static void
  67 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  68 {
  69    struct i915_context *i915 = i915_context(&intel->ctx);
  70    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  71
  72    st1 &= ~ST1_ENABLE;
  73
  74    switch (rprim) {
  75    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  76    case GL_TRIANGLES:
  77       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  78          st1 |= ST1_ENABLE;
  79       break;
  80    case GL_LINES:
  81    case GL_POINTS:
  82    default:
  83       break;
  84    }
  85
  86    i915->intel.reduced_primitive = rprim;
  87
  88    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  89       INTEL_FIREVERTICES(intel);
  90
  91       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  92       i915->state.Stipple[I915_STPREG_ST1] = st1;
  93    }
  94 }
  95
  96
  97 /* Pull apart the vertex format registers and figure out how large a
  98  * vertex is supposed to be.
  99  */
 100 static GLboolean
 101 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
 102 {
 103    struct i915_context *i915 = i915_context(&intel->ctx);
 104    int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
 105    int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
 106    int i, sz = 0;
 107
 108    switch (lis4 & S4_VFMT_XYZW_MASK) {
 109    case S4_VFMT_XY:
 110       sz = 2;
 111       break;
 112    case S4_VFMT_XYZ:
 113       sz = 3;
 114       break;
 115    case S4_VFMT_XYW:
 116       sz = 3;
 117       break;
 118    case S4_VFMT_XYZW:
 119       sz = 4;
 120       break;
 121    default:
 122       fprintf(stderr, "no xyzw specified\n");
 123       return 0;
 124    }
 125
 126    if (lis4 & S4_VFMT_SPEC_FOG)
 127       sz++;
 128    if (lis4 & S4_VFMT_COLOR)
 129       sz++;
 130    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 131       sz++;
 132    if (lis4 & S4_VFMT_POINT_WIDTH)
 133       sz++;
 134    if (lis4 & S4_VFMT_FOG_PARAM)
 135       sz++;
 136
 137    for (i = 0; i < 8; i++) {
 138       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 139       case TEXCOORDFMT_2D:
 140          sz += 2;
 141          break;
 142       case TEXCOORDFMT_3D:
 143          sz += 3;
 144          break;
 145       case TEXCOORDFMT_4D:
 146          sz += 4;
 147          break;
 148       case TEXCOORDFMT_1D:
 149          sz += 1;
 150          break;
 151       case TEXCOORDFMT_2D_16:
 152          sz += 1;
 153          break;
 154       case TEXCOORDFMT_4D_16:
 155          sz += 2;
 156          break;
 157       case TEXCOORDFMT_NOT_PRESENT:
 158          break;
 159       default:
 160          fprintf(stderr, "bad texcoord fmt %d\n", i);
 161          return GL_FALSE;
 162       }
 163       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 164    }
 165
 166    if (sz != expected)
 167       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 168
 169    return sz == expected;
 170 }
 171
 172
 173 static void
 174 i915_emit_invarient_state(struct intel_context *intel)
 175 {
 176    BATCH_LOCALS;
 177
 178    BEGIN_BATCH(20, IGNORE_CLIPRECTS);
 179
 180    OUT_BATCH(_3DSTATE_AA_CMD |
 181              AA_LINE_ECAAR_WIDTH_ENABLE |
 182              AA_LINE_ECAAR_WIDTH_1_0 |
 183              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 184
 185    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 186    OUT_BATCH(0);
 187
 188    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 189    OUT_BATCH(0);
 190
 191    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 192    OUT_BATCH(0);
 193
 194    /* Don't support texture crossbar yet */
 195    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 196              CSB_TCB(0, 0) |
 197              CSB_TCB(1, 1) |
 198              CSB_TCB(2, 2) |
 199              CSB_TCB(3, 3) |
 200              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 201
 202    OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 203              ENABLE_POINT_RASTER_RULE |
 204              OGL_POINT_RASTER_RULE |
 205              ENABLE_LINE_STRIP_PROVOKE_VRTX |
 206              ENABLE_TRI_FAN_PROVOKE_VRTX |
 207              LINE_STRIP_PROVOKE_VRTX(1) |
 208              TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
 209
 210    /* Need to initialize this to zero.
 211     */
 212    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 213    OUT_BATCH(0);
 214
 215    /* XXX: Use this */
 216    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 217
 218    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 219    OUT_BATCH(0);
 220    OUT_BATCH(0);
 221
 222    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 223
 224    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 225    OUT_BATCH(0);
 226
 227
 228    /* Don't support twosided stencil yet */
 229    OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
 230    OUT_BATCH(0);
 231
 232    ADVANCE_BATCH();
 233 }
 234
 235
 236 #define emit(intel, state, size )                    \
 237    intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
 238
 239 static GLuint
 240 get_dirty(struct i915_hw_state *state)
 241 {
 242    GLuint dirty;
 243
 244    /* Workaround the multitex hang - if one texture unit state is
 245     * modified, emit all texture units.
 246     */
 247    dirty = state->active & ~state->emitted;
 248    if (dirty & I915_UPLOAD_TEX_ALL)
 249       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 250    dirty = state->active & ~state->emitted;
 251    return dirty;
 252 }
 253
 254
 255 static GLuint
 256 get_state_size(struct i915_hw_state *state)
 257 {
 258    GLuint dirty = get_dirty(state);
 259    GLuint i;
 260    GLuint sz = 0;
 261
 262    if (dirty & I915_UPLOAD_INVARIENT)
 263       sz += 30 * 4;
 264
 265    if (dirty & I915_UPLOAD_CTX)
 266       sz += sizeof(state->Ctx);
 267
 268    if (dirty & I915_UPLOAD_BUFFERS)
 269       sz += sizeof(state->Buffer);
 270
 271    if (dirty & I915_UPLOAD_STIPPLE)
 272       sz += sizeof(state->Stipple);
 273
 274    if (dirty & I915_UPLOAD_FOG)
 275       sz += sizeof(state->Fog);
 276
 277    if (dirty & I915_UPLOAD_TEX_ALL) {
 278       int nr = 0;
 279       for (i = 0; i < I915_TEX_UNITS; i++)
 280          if (dirty & I915_UPLOAD_TEX(i))
 281             nr++;
 282
 283       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 284    }
 285
 286    if (dirty & I915_UPLOAD_CONSTANTS)
 287       sz += state->ConstantSize * sizeof(GLuint);
 288
 289    if (dirty & I915_UPLOAD_PROGRAM)
 290       sz += state->ProgramSize * sizeof(GLuint);
 291
 292    return sz;
 293 }
 294
 295 /* Push the state into the sarea and/or texture memory.
 296  */
 297 static void
 298 i915_emit_state(struct intel_context *intel)
 299 {
 300    struct i915_context *i915 = i915_context(&intel->ctx);
 301    struct i915_hw_state *state = i915->current;
 302    int i, count, aper_count;
 303    GLuint dirty;
 304    dri_bo *aper_array[3 + I915_TEX_UNITS];
 305    GET_CURRENT_CONTEXT(ctx);
 306    BATCH_LOCALS;
 307
 308    /* We don't hold the lock at this point, so want to make sure that
 309     * there won't be a buffer wrap between the state emits and the primitive
 310     * emit header.
 311     *
 312     * It might be better to talk about explicit places where
 313     * scheduling is allowed, rather than assume that it is whenever a
 314     * batchbuffer fills up.
 315     *
 316     * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
 317     * will be emitted under.
 318     */
 319    intel_batchbuffer_require_space(intel->batch,
 320                                    get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
 321                                    LOOP_CLIPRECTS);
 322    count = 0;
 323  again:
 324    aper_count = 0;
 325    dirty = get_dirty(state);
 326
 327    aper_array[aper_count++] = intel->batch->buf;
 328    if (dirty & I915_UPLOAD_BUFFERS) {
 329       aper_array[aper_count++] = state->draw_region->buffer;
 330       if (state->depth_region)
 331          aper_array[aper_count++] = state->depth_region->buffer;
 332    }
 333
 334    if (dirty & I915_UPLOAD_TEX_ALL) {
 335       for (i = 0; i < I915_TEX_UNITS; i++) {
 336          if (dirty & I915_UPLOAD_TEX(i)) {
 337             if (state->tex_buffer[i]) {
 338                aper_array[aper_count++] = state->tex_buffer[i];
 339             }
 340          }
 341       }
 342    }
 343
 344    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
 345        if (count == 0) {
 346            count++;
 347            intel_batchbuffer_flush(intel->batch);
 348            goto again;
 349        } else {
 350            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 351            assert(0);
 352        }
 353    }
 354
 355    /* work out list of buffers to emit */
 356
 357    /* Do this here as we may have flushed the batchbuffer above,
 358     * causing more state to be dirty!
 359     */
 360    dirty = get_dirty(state);
 361    state->emitted |= dirty;
 362    assert(get_dirty(state) == 0);
 363
 364    if (INTEL_DEBUG & DEBUG_STATE)
 365       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 366
 367    if (dirty & I915_UPLOAD_INVARIENT) {
 368       if (INTEL_DEBUG & DEBUG_STATE)
 369          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 370       i915_emit_invarient_state(intel);
 371    }
 372
 373    if (dirty & I915_UPLOAD_CTX) {
 374       if (INTEL_DEBUG & DEBUG_STATE)
 375          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 376
 377       emit(intel, state->Ctx, sizeof(state->Ctx));
 378    }
 379
 380    if (dirty & I915_UPLOAD_BUFFERS) {
 381       GLuint count = 9;
 382
 383       if (INTEL_DEBUG & DEBUG_STATE)
 384          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 385
 386       if (state->depth_region)
 387           count += 3;
 388
 389       if (intel->constant_cliprect)
 390           count += 6;
 391
 392       BEGIN_BATCH(count, IGNORE_CLIPRECTS);
 393       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 394       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 395       OUT_RELOC(state->draw_region->buffer,
 396                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 397                 state->draw_region->draw_offset);
 398
 399       if (state->depth_region) {
 400          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 401          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 402          OUT_RELOC(state->depth_region->buffer,
 403                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 404                    state->depth_region->draw_offset);
 405       }
 406
 407       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 408       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 409       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 410       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 411       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 412       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 413
 414       if (intel->constant_cliprect) {
 415          assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
 416          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
 417          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
 418          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
 419          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
 420          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
 421          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
 422       }
 423
 424       ADVANCE_BATCH();
 425    }
 426
 427    if (dirty & I915_UPLOAD_STIPPLE) {
 428       if (INTEL_DEBUG & DEBUG_STATE)
 429          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 430       emit(intel, state->Stipple, sizeof(state->Stipple));
 431    }
 432
 433    if (dirty & I915_UPLOAD_FOG) {
 434       if (INTEL_DEBUG & DEBUG_STATE)
 435          fprintf(stderr, "I915_UPLOAD_FOG:\n");
 436       emit(intel, state->Fog, sizeof(state->Fog));
 437    }
 438
 439    /* Combine all the dirty texture state into a single command to
 440     * avoid lockups on I915 hardware.
 441     */
 442    if (dirty & I915_UPLOAD_TEX_ALL) {
 443       int nr = 0;
 444
 445       for (i = 0; i < I915_TEX_UNITS; i++)
 446          if (dirty & I915_UPLOAD_TEX(i))
 447             nr++;
 448
 449       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 450       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 451       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 452       for (i = 0; i < I915_TEX_UNITS; i++)
 453          if (dirty & I915_UPLOAD_TEX(i)) {
 454
 455             if (state->tex_buffer[i]) {
 456                OUT_RELOC(state->tex_buffer[i],
 457                          I915_GEM_DOMAIN_SAMPLER, 0,
 458                          state->tex_offset[i]);
 459             }
 460             else if (state == &i915->meta) {
 461                assert(i == 0);
 462                OUT_BATCH(0);
 463             }
 464             else {
 465                OUT_BATCH(state->tex_offset[i]);
 466             }
 467
 468             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 469             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 470          }
 471       ADVANCE_BATCH();
 472
 473       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 474       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 475       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 476       for (i = 0; i < I915_TEX_UNITS; i++)
 477          if (dirty & I915_UPLOAD_TEX(i)) {
 478             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 479             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 480             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 481          }
 482       ADVANCE_BATCH();
 483    }
 484
 485    if (dirty & I915_UPLOAD_CONSTANTS) {
 486       if (INTEL_DEBUG & DEBUG_STATE)
 487          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 488       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 489    }
 490
 491    if (dirty & I915_UPLOAD_PROGRAM) {
 492       if (state->ProgramSize) {
 493          if (INTEL_DEBUG & DEBUG_STATE)
 494             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 495
 496          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 497
 498          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 499          if (INTEL_DEBUG & DEBUG_STATE)
 500             i915_disassemble_program(state->Program, state->ProgramSize);
 501       }
 502    }
 503
 504    intel->batch->dirty_state &= ~dirty;
 505    assert(get_dirty(state) == 0);
 506    assert((intel->batch->dirty_state & (1<<1)) == 0);
 507 }
 508
 509 static void
 510 i915_destroy_context(struct intel_context *intel)
 511 {
 512    GLuint i;
 513    struct i915_context *i915 = i915_context(&intel->ctx);
 514
 515    intel_region_release(&i915->state.draw_region);
 516    intel_region_release(&i915->state.depth_region);
 517    intel_region_release(&i915->meta.draw_region);
 518    intel_region_release(&i915->meta.depth_region);
 519    intel_region_release(&i915->initial.draw_region);
 520    intel_region_release(&i915->initial.depth_region);
 521
 522    for (i = 0; i < I915_TEX_UNITS; i++) {
 523       if (i915->state.tex_buffer[i] != NULL) {
 524          dri_bo_unreference(i915->state.tex_buffer[i]);
 525          i915->state.tex_buffer[i] = NULL;
 526       }
 527    }
 528
 529    _tnl_free_vertices(&intel->ctx);
 530 }
 531
 532
 533 /**
 534  * Set the drawing regions for the color and depth/stencil buffers.
 535  * This involves setting the pitch, cpp and buffer ID/location.
 536  * Also set pixel format for color and Z rendering
 537  * Used for setting both regular and meta state.
 538  */
 539 void
 540 i915_state_draw_region(struct intel_context *intel,
 541                        struct i915_hw_state *state,
 542                        struct intel_region *color_region,
 543                        struct intel_region *depth_region)
 544 {
 545    struct i915_context *i915 = i915_context(&intel->ctx);
 546    GLcontext *ctx = &intel->ctx;
 547    struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
 548    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 549    GLuint value;
 550
 551    ASSERT(state == &i915->state || state == &i915->meta);
 552
 553    if (state->draw_region != color_region) {
 554       intel_region_release(&state->draw_region);
 555       intel_region_reference(&state->draw_region, color_region);
 556    }
 557    if (state->depth_region != depth_region) {
 558       intel_region_release(&state->depth_region);
 559       intel_region_reference(&state->depth_region, depth_region);
 560    }
 561
 562    /*
 563     * Set stride/cpp values
 564     */
 565    if (color_region) {
 566       state->Buffer[I915_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 567       state->Buffer[I915_DESTREG_CBUFADDR1] =
 568          (BUF_3D_ID_COLOR_BACK |
 569           BUF_3D_PITCH(color_region->pitch * color_region->cpp) |
 570           BUF_3D_USE_FENCE);
 571    }
 572
 573    if (depth_region) {
 574       state->Buffer[I915_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 575       state->Buffer[I915_DESTREG_DBUFADDR1] =
 576          (BUF_3D_ID_DEPTH |
 577           BUF_3D_PITCH(depth_region->pitch * depth_region->cpp) |
 578           BUF_3D_USE_FENCE);
 579    }
 580
 581    /*
 582     * Compute/set I915_DESTREG_DV1 value
 583     */
 584    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 585             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 586             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 587    if (irb != NULL) {
 588       switch (irb->texformat->MesaFormat) {
 589       case MESA_FORMAT_ARGB8888:
 590          value |= DV_PF_8888;
 591          break;
 592       case MESA_FORMAT_RGB565:
 593          value |= DV_PF_565 | DITHER_FULL_ALWAYS;
 594          break;
 595       case MESA_FORMAT_ARGB1555:
 596          value |= DV_PF_1555 | DITHER_FULL_ALWAYS;
 597          break;
 598       case MESA_FORMAT_ARGB4444:
 599          value |= DV_PF_4444 | DITHER_FULL_ALWAYS;
 600          break;
 601       default:
 602          _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
 603                        irb->texformat->MesaFormat);
 604       }
 605    }
 606
 607    if (depth_region && depth_region->cpp == 4) {
 608       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 609    }
 610    else {
 611       value |= DEPTH_FRMT_16_FIXED;
 612    }
 613    state->Buffer[I915_DESTREG_DV1] = value;
 614
 615    if (intel->constant_cliprect) {
 616       state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
 617       state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
 618       state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
 619       state->Buffer[I915_DESTREG_DRAWRECT3] =
 620          (ctx->DrawBuffer->Width & 0xffff) |
 621          (ctx->DrawBuffer->Height << 16);
 622       state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
 623       state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
 624    } else {
 625       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
 626       state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP;
 627       state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP;
 628       state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP;
 629       state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP;
 630       state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP;
 631    }
 632
 633    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 634 }
 635
 636
 637 static void
 638 i915_set_draw_region(struct intel_context *intel,
 639                      struct intel_region *color_regions[],
 640                      struct intel_region *depth_region,
 641                      GLuint num_regions)
 642 {
 643    struct i915_context *i915 = i915_context(&intel->ctx);
 644    i915_state_draw_region(intel, &i915->state, color_regions[0], depth_region);
 645 }
 646
 647
 648
 649 static void
 650 i915_new_batch(struct intel_context *intel)
 651 {
 652    struct i915_context *i915 = i915_context(&intel->ctx);
 653
 654    /* Mark all state as needing to be emitted when starting a new batchbuffer.
 655     * Using hardware contexts would be an alternative, but they have some
 656     * difficulties associated with them (physical address requirements).
 657     */
 658    i915->state.emitted = 0;
 659
 660    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 661    assert(!intel->no_batch_wrap);
 662 }
 663
 664 static GLuint
 665 i915_flush_cmd(void)
 666 {
 667    return MI_FLUSH | FLUSH_MAP_CACHE;
 668 }
 669
 670 static void
 671 i915_assert_not_dirty( struct intel_context *intel )
 672 {
 673    struct i915_context *i915 = i915_context(&intel->ctx);
 674    struct i915_hw_state *state = i915->current;
 675    GLuint dirty = get_dirty(state);
 676    assert(!dirty);
 677 }
 678
 679 static void
 680 i915_note_unlock( struct intel_context *intel )
 681 {
 682     /* nothing */
 683 }
 684
 685
 686 void
 687 i915InitVtbl(struct i915_context *i915)
 688 {
 689    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 690    i915->intel.vtbl.destroy = i915_destroy_context;
 691    i915->intel.vtbl.emit_state = i915_emit_state;
 692    i915->intel.vtbl.new_batch = i915_new_batch;
 693    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 694    i915->intel.vtbl.render_start = i915_render_start;
 695    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 696    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 697    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 698    i915->intel.vtbl.flush_cmd = i915_flush_cmd;
 699    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 700    i915->intel.vtbl.note_unlock = i915_note_unlock;
 701    i915->intel.vtbl.finish_batch = intel_finish_vb;
 702 }