1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
35 #include "main/texformat.h"
37 #include "tnl/t_context.h"
38 #include "tnl/t_vertex.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_tex.h"
42 #include "intel_regions.h"
43 #include "intel_tris.h"
44 #include "intel_fbo.h"
45 #include "intel_chipset.h"
48 #include "i915_context.h"
50 #include "glapi/glapi.h"
53 i915_render_prevalidate(struct intel_context
*intel
)
55 struct i915_context
*i915
= i915_context(&intel
->ctx
);
58 i915ValidateFragmentProgram(i915
);
62 i915_render_start(struct intel_context
*intel
)
68 i915_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
70 struct i915_context
*i915
= i915_context(&intel
->ctx
);
71 GLuint st1
= i915
->state
.Stipple
[I915_STPREG_ST1
];
76 case GL_QUADS
: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
78 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
87 i915
->intel
.reduced_primitive
= rprim
;
89 if (st1
!= i915
->state
.Stipple
[I915_STPREG_ST1
]) {
90 INTEL_FIREVERTICES(intel
);
92 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
93 i915
->state
.Stipple
[I915_STPREG_ST1
] = st1
;
98 /* Pull apart the vertex format registers and figure out how large a
99 * vertex is supposed to be.
102 i915_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
104 struct i915_context
*i915
= i915_context(&intel
->ctx
);
105 int lis2
= i915
->current
->Ctx
[I915_CTXREG_LIS2
];
106 int lis4
= i915
->current
->Ctx
[I915_CTXREG_LIS4
];
109 switch (lis4
& S4_VFMT_XYZW_MASK
) {
123 fprintf(stderr
, "no xyzw specified\n");
127 if (lis4
& S4_VFMT_SPEC_FOG
)
129 if (lis4
& S4_VFMT_COLOR
)
131 if (lis4
& S4_VFMT_DEPTH_OFFSET
)
133 if (lis4
& S4_VFMT_POINT_WIDTH
)
135 if (lis4
& S4_VFMT_FOG_PARAM
)
138 for (i
= 0; i
< 8; i
++) {
139 switch (lis2
& S2_TEXCOORD_FMT0_MASK
) {
152 case TEXCOORDFMT_2D_16
:
155 case TEXCOORDFMT_4D_16
:
158 case TEXCOORDFMT_NOT_PRESENT
:
161 fprintf(stderr
, "bad texcoord fmt %d\n", i
);
164 lis2
>>= S2_TEXCOORD_FMT1_SHIFT
;
168 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
170 return sz
== expected
;
175 i915_emit_invarient_state(struct intel_context
*intel
)
179 BEGIN_BATCH(17, IGNORE_CLIPRECTS
);
181 OUT_BATCH(_3DSTATE_AA_CMD
|
182 AA_LINE_ECAAR_WIDTH_ENABLE
|
183 AA_LINE_ECAAR_WIDTH_1_0
|
184 AA_LINE_REGION_WIDTH_ENABLE
| AA_LINE_REGION_WIDTH_1_0
);
186 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
189 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
192 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
195 /* Don't support texture crossbar yet */
196 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS
|
201 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
203 /* Need to initialize this to zero.
205 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1
| I1_LOAD_S(3) | (0));
209 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
211 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD
);
215 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE
);
217 OUT_BATCH(_3DSTATE_LOAD_INDIRECT
| 0); /* disable indirect state */
224 #define emit(intel, state, size ) \
225 intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
228 get_dirty(struct i915_hw_state
*state
)
232 /* Workaround the multitex hang - if one texture unit state is
233 * modified, emit all texture units.
235 dirty
= state
->active
& ~state
->emitted
;
236 if (dirty
& I915_UPLOAD_TEX_ALL
)
237 state
->emitted
&= ~I915_UPLOAD_TEX_ALL
;
238 dirty
= state
->active
& ~state
->emitted
;
244 get_state_size(struct i915_hw_state
*state
)
246 GLuint dirty
= get_dirty(state
);
250 if (dirty
& I915_UPLOAD_INVARIENT
)
253 if (dirty
& I915_UPLOAD_RASTER_RULES
)
254 sz
+= sizeof(state
->RasterRules
);
256 if (dirty
& I915_UPLOAD_CTX
)
257 sz
+= sizeof(state
->Ctx
);
259 if (dirty
& I915_UPLOAD_BUFFERS
)
260 sz
+= sizeof(state
->Buffer
);
262 if (dirty
& I915_UPLOAD_STIPPLE
)
263 sz
+= sizeof(state
->Stipple
);
265 if (dirty
& I915_UPLOAD_FOG
)
266 sz
+= sizeof(state
->Fog
);
268 if (dirty
& I915_UPLOAD_TEX_ALL
) {
270 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
271 if (dirty
& I915_UPLOAD_TEX(i
))
274 sz
+= (2 + nr
* 3) * sizeof(GLuint
) * 2;
277 if (dirty
& I915_UPLOAD_CONSTANTS
)
278 sz
+= state
->ConstantSize
* sizeof(GLuint
);
280 if (dirty
& I915_UPLOAD_PROGRAM
)
281 sz
+= state
->ProgramSize
* sizeof(GLuint
);
286 /* Push the state into the sarea and/or texture memory.
289 i915_emit_state(struct intel_context
*intel
)
291 struct i915_context
*i915
= i915_context(&intel
->ctx
);
292 struct i915_hw_state
*state
= i915
->current
;
293 int i
, count
, aper_count
;
295 dri_bo
*aper_array
[3 + I915_TEX_UNITS
];
296 GET_CURRENT_CONTEXT(ctx
);
299 /* We don't hold the lock at this point, so want to make sure that
300 * there won't be a buffer wrap between the state emits and the primitive
303 * It might be better to talk about explicit places where
304 * scheduling is allowed, rather than assume that it is whenever a
305 * batchbuffer fills up.
307 * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
308 * will be emitted under.
310 intel_batchbuffer_require_space(intel
->batch
,
311 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
316 dirty
= get_dirty(state
);
318 aper_array
[aper_count
++] = intel
->batch
->buf
;
319 if (dirty
& I915_UPLOAD_BUFFERS
) {
320 aper_array
[aper_count
++] = state
->draw_region
->buffer
;
321 if (state
->depth_region
)
322 aper_array
[aper_count
++] = state
->depth_region
->buffer
;
325 if (dirty
& I915_UPLOAD_TEX_ALL
) {
326 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
327 if (dirty
& I915_UPLOAD_TEX(i
)) {
328 if (state
->tex_buffer
[i
]) {
329 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
335 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
338 intel_batchbuffer_flush(intel
->batch
);
341 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i915 emit state");
346 /* work out list of buffers to emit */
348 /* Do this here as we may have flushed the batchbuffer above,
349 * causing more state to be dirty!
351 dirty
= get_dirty(state
);
352 state
->emitted
|= dirty
;
353 assert(get_dirty(state
) == 0);
355 if (INTEL_DEBUG
& DEBUG_STATE
)
356 fprintf(stderr
, "%s dirty: %x\n", __FUNCTION__
, dirty
);
358 if (dirty
& I915_UPLOAD_INVARIENT
) {
359 if (INTEL_DEBUG
& DEBUG_STATE
)
360 fprintf(stderr
, "I915_UPLOAD_INVARIENT:\n");
361 i915_emit_invarient_state(intel
);
364 if (dirty
& I915_UPLOAD_RASTER_RULES
) {
365 if (INTEL_DEBUG
& DEBUG_STATE
)
366 fprintf(stderr
, "I915_UPLOAD_RASTER_RULES:\n");
367 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
370 if (dirty
& I915_UPLOAD_CTX
) {
371 if (INTEL_DEBUG
& DEBUG_STATE
)
372 fprintf(stderr
, "I915_UPLOAD_CTX:\n");
374 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
377 if (dirty
& I915_UPLOAD_BUFFERS
) {
380 if (INTEL_DEBUG
& DEBUG_STATE
)
381 fprintf(stderr
, "I915_UPLOAD_BUFFERS:\n");
383 if (state
->depth_region
)
386 if (intel
->constant_cliprect
)
389 BEGIN_BATCH(count
, IGNORE_CLIPRECTS
);
390 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR0
]);
391 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR1
]);
392 OUT_RELOC(state
->draw_region
->buffer
,
393 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
394 state
->draw_region
->draw_offset
);
396 if (state
->depth_region
) {
397 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR0
]);
398 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR1
]);
399 OUT_RELOC(state
->depth_region
->buffer
,
400 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
401 state
->depth_region
->draw_offset
);
404 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV0
]);
405 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV1
]);
406 OUT_BATCH(state
->Buffer
[I915_DESTREG_SENABLE
]);
407 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR0
]);
408 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR1
]);
409 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR2
]);
411 if (intel
->constant_cliprect
) {
412 assert(state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
);
413 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT0
]);
414 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT1
]);
415 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT2
]);
416 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT3
]);
417 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT4
]);
418 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT5
]);
424 if (dirty
& I915_UPLOAD_STIPPLE
) {
425 if (INTEL_DEBUG
& DEBUG_STATE
)
426 fprintf(stderr
, "I915_UPLOAD_STIPPLE:\n");
427 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
430 if (dirty
& I915_UPLOAD_FOG
) {
431 if (INTEL_DEBUG
& DEBUG_STATE
)
432 fprintf(stderr
, "I915_UPLOAD_FOG:\n");
433 emit(intel
, state
->Fog
, sizeof(state
->Fog
));
436 /* Combine all the dirty texture state into a single command to
437 * avoid lockups on I915 hardware.
439 if (dirty
& I915_UPLOAD_TEX_ALL
) {
442 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
443 if (dirty
& I915_UPLOAD_TEX(i
))
446 BEGIN_BATCH(2 + nr
* 3, IGNORE_CLIPRECTS
);
447 OUT_BATCH(_3DSTATE_MAP_STATE
| (3 * nr
));
448 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
449 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
450 if (dirty
& I915_UPLOAD_TEX(i
)) {
452 if (state
->tex_buffer
[i
]) {
453 OUT_RELOC(state
->tex_buffer
[i
],
454 I915_GEM_DOMAIN_SAMPLER
, 0,
455 state
->tex_offset
[i
]);
457 else if (state
== &i915
->meta
) {
462 OUT_BATCH(state
->tex_offset
[i
]);
465 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS3
]);
466 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS4
]);
470 BEGIN_BATCH(2 + nr
* 3, IGNORE_CLIPRECTS
);
471 OUT_BATCH(_3DSTATE_SAMPLER_STATE
| (3 * nr
));
472 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
473 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
474 if (dirty
& I915_UPLOAD_TEX(i
)) {
475 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS2
]);
476 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS3
]);
477 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS4
]);
482 if (dirty
& I915_UPLOAD_CONSTANTS
) {
483 if (INTEL_DEBUG
& DEBUG_STATE
)
484 fprintf(stderr
, "I915_UPLOAD_CONSTANTS:\n");
485 emit(intel
, state
->Constant
, state
->ConstantSize
* sizeof(GLuint
));
488 if (dirty
& I915_UPLOAD_PROGRAM
) {
489 if (state
->ProgramSize
) {
490 if (INTEL_DEBUG
& DEBUG_STATE
)
491 fprintf(stderr
, "I915_UPLOAD_PROGRAM:\n");
493 assert((state
->Program
[0] & 0x1ff) + 2 == state
->ProgramSize
);
495 emit(intel
, state
->Program
, state
->ProgramSize
* sizeof(GLuint
));
496 if (INTEL_DEBUG
& DEBUG_STATE
)
497 i915_disassemble_program(state
->Program
, state
->ProgramSize
);
501 intel
->batch
->dirty_state
&= ~dirty
;
502 assert(get_dirty(state
) == 0);
503 assert((intel
->batch
->dirty_state
& (1<<1)) == 0);
507 i915_destroy_context(struct intel_context
*intel
)
510 struct i915_context
*i915
= i915_context(&intel
->ctx
);
512 intel_region_release(&i915
->state
.draw_region
);
513 intel_region_release(&i915
->state
.depth_region
);
514 intel_region_release(&i915
->meta
.draw_region
);
515 intel_region_release(&i915
->meta
.depth_region
);
516 intel_region_release(&i915
->initial
.draw_region
);
517 intel_region_release(&i915
->initial
.depth_region
);
519 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
520 if (i915
->state
.tex_buffer
[i
] != NULL
) {
521 dri_bo_unreference(i915
->state
.tex_buffer
[i
]);
522 i915
->state
.tex_buffer
[i
] = NULL
;
526 _tnl_free_vertices(&intel
->ctx
);
530 i915_set_buf_info_for_region(uint32_t *state
, struct intel_region
*region
,
533 state
[0] = _3DSTATE_BUF_INFO_CMD
;
534 state
[1] = buffer_id
;
536 if (region
!= NULL
) {
537 state
[1] |= BUF_3D_PITCH(region
->pitch
* region
->cpp
);
539 if (region
->tiling
!= I915_TILING_NONE
) {
540 state
[1] |= BUF_3D_TILED_SURFACE
;
541 if (region
->tiling
== I915_TILING_Y
)
542 state
[1] |= BUF_3D_TILE_WALK_Y
;
548 * Set the drawing regions for the color and depth/stencil buffers.
549 * This involves setting the pitch, cpp and buffer ID/location.
550 * Also set pixel format for color and Z rendering
551 * Used for setting both regular and meta state.
554 i915_state_draw_region(struct intel_context
*intel
,
555 struct i915_hw_state
*state
,
556 struct intel_region
*color_region
,
557 struct intel_region
*depth_region
)
559 struct i915_context
*i915
= i915_context(&intel
->ctx
);
560 GLcontext
*ctx
= &intel
->ctx
;
561 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
562 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
565 ASSERT(state
== &i915
->state
|| state
== &i915
->meta
);
567 if (state
->draw_region
!= color_region
) {
568 intel_region_release(&state
->draw_region
);
569 intel_region_reference(&state
->draw_region
, color_region
);
571 if (state
->depth_region
!= depth_region
) {
572 intel_region_release(&state
->depth_region
);
573 intel_region_reference(&state
->depth_region
, depth_region
);
577 * Set stride/cpp values
579 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_CBUFADDR0
],
580 color_region
, BUF_3D_ID_COLOR_BACK
);
582 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_DBUFADDR0
],
583 depth_region
, BUF_3D_ID_DEPTH
);
586 * Compute/set I915_DESTREG_DV1 value
588 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
589 DSTORG_VERT_BIAS(0x8) | /* .5 */
590 LOD_PRECLAMP_OGL
| TEX_DEFAULT_COLOR_OGL
);
592 switch (irb
->texformat
) {
593 case MESA_FORMAT_ARGB8888
:
596 case MESA_FORMAT_RGB565
:
597 value
|= DV_PF_565
| DITHER_FULL_ALWAYS
;
599 case MESA_FORMAT_ARGB1555
:
600 value
|= DV_PF_1555
| DITHER_FULL_ALWAYS
;
602 case MESA_FORMAT_ARGB4444
:
603 value
|= DV_PF_4444
| DITHER_FULL_ALWAYS
;
606 _mesa_problem(ctx
, "Bad renderbuffer format: %d\n",
611 /* This isn't quite safe, thus being hidden behind an option. When changing
612 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
613 * can only be set when a depth buffer is already defined.
615 if (IS_945(intel
->intelScreen
->deviceID
) && intel
->use_early_z
&&
616 depth_region
->tiling
!= I915_TILING_NONE
)
617 value
|= CLASSIC_EARLY_DEPTH
;
619 if (depth_region
&& depth_region
->cpp
== 4) {
620 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
623 value
|= DEPTH_FRMT_16_FIXED
;
625 state
->Buffer
[I915_DESTREG_DV1
] = value
;
627 if (intel
->constant_cliprect
) {
628 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = _3DSTATE_DRAWRECT_INFO
;
629 state
->Buffer
[I915_DESTREG_DRAWRECT1
] = 0;
630 state
->Buffer
[I915_DESTREG_DRAWRECT2
] = 0; /* xmin, ymin */
631 state
->Buffer
[I915_DESTREG_DRAWRECT3
] =
632 (ctx
->DrawBuffer
->Width
& 0xffff) |
633 (ctx
->DrawBuffer
->Height
<< 16);
634 state
->Buffer
[I915_DESTREG_DRAWRECT4
] = 0; /* xoff, yoff */
635 state
->Buffer
[I915_DESTREG_DRAWRECT5
] = 0;
637 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_NOOP
;
638 state
->Buffer
[I915_DESTREG_DRAWRECT1
] = MI_NOOP
;
639 state
->Buffer
[I915_DESTREG_DRAWRECT2
] = MI_NOOP
;
640 state
->Buffer
[I915_DESTREG_DRAWRECT3
] = MI_NOOP
;
641 state
->Buffer
[I915_DESTREG_DRAWRECT4
] = MI_NOOP
;
642 state
->Buffer
[I915_DESTREG_DRAWRECT5
] = MI_NOOP
;
645 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
650 i915_set_draw_region(struct intel_context
*intel
,
651 struct intel_region
*color_regions
[],
652 struct intel_region
*depth_region
,
655 struct i915_context
*i915
= i915_context(&intel
->ctx
);
656 i915_state_draw_region(intel
, &i915
->state
, color_regions
[0], depth_region
);
662 i915_new_batch(struct intel_context
*intel
)
664 struct i915_context
*i915
= i915_context(&intel
->ctx
);
666 /* Mark all state as needing to be emitted when starting a new batchbuffer.
667 * Using hardware contexts would be an alternative, but they have some
668 * difficulties associated with them (physical address requirements).
670 i915
->state
.emitted
= 0;
672 /* Check that we didn't just wrap our batchbuffer at a bad time. */
673 assert(!intel
->no_batch_wrap
);
679 return MI_FLUSH
| FLUSH_MAP_CACHE
;
683 i915_assert_not_dirty( struct intel_context
*intel
)
685 struct i915_context
*i915
= i915_context(&intel
->ctx
);
686 struct i915_hw_state
*state
= i915
->current
;
687 GLuint dirty
= get_dirty(state
);
692 i915InitVtbl(struct i915_context
*i915
)
694 i915
->intel
.vtbl
.check_vertex_size
= i915_check_vertex_size
;
695 i915
->intel
.vtbl
.destroy
= i915_destroy_context
;
696 i915
->intel
.vtbl
.emit_state
= i915_emit_state
;
697 i915
->intel
.vtbl
.new_batch
= i915_new_batch
;
698 i915
->intel
.vtbl
.reduced_primitive_state
= i915_reduced_primitive_state
;
699 i915
->intel
.vtbl
.render_start
= i915_render_start
;
700 i915
->intel
.vtbl
.render_prevalidate
= i915_render_prevalidate
;
701 i915
->intel
.vtbl
.set_draw_region
= i915_set_draw_region
;
702 i915
->intel
.vtbl
.update_texture_state
= i915UpdateTextureState
;
703 i915
->intel
.vtbl
.flush_cmd
= i915_flush_cmd
;
704 i915
->intel
.vtbl
.assert_not_dirty
= i915_assert_not_dirty
;
705 i915
->intel
.vtbl
.finish_batch
= intel_finish_vb
;