src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "glheader.h"
  31 #include "mtypes.h"
  32 #include "imports.h"
  33 #include "macros.h"
  34 #include "colormac.h"
  35
  36 #include "tnl/t_context.h"
  37 #include "tnl/t_vertex.h"
  38
  39 #include "intel_batchbuffer.h"
  40
  41 #include "i915_reg.h"
  42 #include "i915_context.h"
  43
  44 static void i915_render_start( intelContextPtr intel )
  45 {
  46    GLcontext *ctx = &intel->ctx;
  47    i915ContextPtr i915 = I915_CONTEXT(intel);
  48
  49    if (ctx->FragmentProgram.Enabled && ctx->FragmentProgram.Current)
  50       i915ValidateFragmentProgram( i915 );
  51    else
  52       i915ValidateTextureProgram( i915 );
  53 }
  54
  55
  56 static void i915_reduced_primitive_state( intelContextPtr intel,
  57                                           GLenum rprim )
  58 {
  59     i915ContextPtr i915 = I915_CONTEXT(intel);
  60     GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  61
  62     st1 &= ~ST1_ENABLE;
  63
  64     switch (rprim) {
  65     case GL_TRIANGLES:
  66        if (intel->ctx.Polygon.StippleFlag &&
  67            intel->hw_stipple)
  68           st1 |= ST1_ENABLE;
  69        break;
  70     case GL_LINES:
  71     case GL_POINTS:
  72     default:
  73        break;
  74     }
  75
  76     i915->intel.reduced_primitive = rprim;
  77
  78     if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  79        I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  80        i915->state.Stipple[I915_STPREG_ST1] = st1;
  81     }
  82 }
  83
  84
  85 /* Pull apart the vertex format registers and figure out how large a
  86  * vertex is supposed to be.
  87  */
  88 static GLboolean i915_check_vertex_size( intelContextPtr intel,
  89                                          GLuint expected )
  90 {
  91    i915ContextPtr i915 = I915_CONTEXT(intel);
  92    int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
  93    int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
  94    int i, sz = 0;
  95
  96    switch (lis4 & S4_VFMT_XYZW_MASK) {
  97    case S4_VFMT_XY: sz = 2; break;
  98    case S4_VFMT_XYZ: sz = 3; break;
  99    case S4_VFMT_XYW: sz = 3; break;
 100    case S4_VFMT_XYZW: sz = 4; break;
 101    default:
 102       fprintf(stderr, "no xyzw specified\n");
 103       return 0;
 104    }
 105
 106    if (lis4 & S4_VFMT_SPEC_FOG) sz++;
 107    if (lis4 & S4_VFMT_COLOR) sz++;
 108    if (lis4 & S4_VFMT_DEPTH_OFFSET) sz++;
 109    if (lis4 & S4_VFMT_POINT_WIDTH) sz++;
 110
 111    for (i = 0 ; i < 8 ; i++) {
 112       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 113       case TEXCOORDFMT_2D: sz += 2; break;
 114       case TEXCOORDFMT_3D: sz += 3; break;
 115       case TEXCOORDFMT_4D: sz += 4; break;
 116       case TEXCOORDFMT_1D: sz += 1; break;
 117       case TEXCOORDFMT_2D_16: sz += 1; break;
 118       case TEXCOORDFMT_4D_16: sz += 2; break;
 119       case TEXCOORDFMT_NOT_PRESENT: break;
 120       default:
 121          fprintf(stderr, "bad texcoord fmt %d\n", i);
 122          return GL_FALSE;
 123       }
 124       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 125    }
 126
 127    if (sz != expected)
 128       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 129
 130    return sz == expected;
 131 }
 132
 133
 134 static void i915_emit_invarient_state( intelContextPtr intel )
 135 {
 136    BATCH_LOCALS;
 137
 138    BEGIN_BATCH( 200 );
 139
 140    OUT_BATCH(_3DSTATE_AA_CMD |
 141              AA_LINE_ECAAR_WIDTH_ENABLE |
 142              AA_LINE_ECAAR_WIDTH_1_0 |
 143              AA_LINE_REGION_WIDTH_ENABLE |
 144              AA_LINE_REGION_WIDTH_1_0);
 145
 146    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 147    OUT_BATCH(0);
 148
 149    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 150    OUT_BATCH(0);
 151
 152    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 153    OUT_BATCH(0);
 154
 155    /* Don't support texture crossbar yet */
 156    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 157              CSB_TCB(0, 0) |
 158              CSB_TCB(1, 1) |
 159              CSB_TCB(2, 2) |
 160              CSB_TCB(3, 3) |
 161              CSB_TCB(4, 4) |
 162              CSB_TCB(5, 5) |
 163              CSB_TCB(6, 6) |
 164              CSB_TCB(7, 7));
 165
 166    OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 167              ENABLE_POINT_RASTER_RULE |
 168              OGL_POINT_RASTER_RULE |
 169              ENABLE_LINE_STRIP_PROVOKE_VRTX |
 170              ENABLE_TRI_FAN_PROVOKE_VRTX |
 171              LINE_STRIP_PROVOKE_VRTX(1) |
 172              TRI_FAN_PROVOKE_VRTX(2) |
 173              ENABLE_TEXKILL_3D_4D |
 174              TEXKILL_4D);
 175
 176    /* Need to initialize this to zero.
 177     */
 178    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
 179              I1_LOAD_S(3) |
 180              (1));
 181    OUT_BATCH(0);
 182
 183    /* XXX: Use this */
 184    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD |
 185              DISABLE_SCISSOR_RECT);
 186
 187    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 188    OUT_BATCH(0);
 189    OUT_BATCH(0);
 190
 191    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 192
 193    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
 194    OUT_BATCH(0);
 195
 196
 197    /* Don't support twosided stencil yet */
 198    OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS |
 199              BFO_ENABLE_STENCIL_TWO_SIDE |
 200              0 );
 201
 202    ADVANCE_BATCH();
 203 }
 204
 205
 206 #define emit( intel, state, size )                      \
 207 do {                                                    \
 208    int k;                                               \
 209    BEGIN_BATCH( (size) / sizeof(GLuint));               \
 210    for (k = 0 ; k < (size) / sizeof(GLuint) ; k++)      \
 211       OUT_BATCH((state)[k]);                            \
 212    ADVANCE_BATCH();                                     \
 213 } while (0);
 214
 215
 216 /* Push the state into the sarea and/or texture memory.
 217  */
 218 static void i915_emit_state( intelContextPtr intel )
 219 {
 220    i915ContextPtr i915 = I915_CONTEXT(intel);
 221    struct i915_hw_state *state = i915->current;
 222    int i;
 223    GLuint dirty;
 224    BATCH_LOCALS;
 225
 226    /* More to workaround the multitex hang - if one texture unit state
 227     * is modified, emit all texture units.
 228     */
 229    dirty = state->active & ~state->emitted;
 230    if (dirty & I915_UPLOAD_TEX_ALL)
 231       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 232    dirty = state->active & ~state->emitted;
 233
 234
 235    if (VERBOSE)
 236       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 237
 238    if (dirty & I915_UPLOAD_CTX) {
 239       if (VERBOSE) fprintf(stderr, "I915_UPLOAD_CTX:\n");
 240       emit( i915, state->Ctx, sizeof(state->Ctx) );
 241    }
 242
 243    if (dirty & I915_UPLOAD_BUFFERS) {
 244       if (VERBOSE) fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 245       emit( i915, state->Buffer, sizeof(state->Buffer) );
 246    }
 247
 248    if (dirty & I915_UPLOAD_STIPPLE) {
 249       if (VERBOSE) fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 250       emit( i915, state->Stipple, sizeof(state->Stipple) );
 251    }
 252
 253    if (dirty & I915_UPLOAD_FOG) {
 254       if (VERBOSE) fprintf(stderr, "I915_UPLOAD_FOG:\n");
 255       emit( i915, state->Fog, sizeof(state->Fog) );
 256    }
 257
 258    /* Combine all the dirty texture state into a single command to
 259     * avoid lockups on I915 hardware.
 260     */
 261    if (dirty & I915_UPLOAD_TEX_ALL) {
 262       int nr = 0;
 263
 264       for (i = 0; i < I915_TEX_UNITS; i++)
 265          if (dirty & I915_UPLOAD_TEX(i))
 266             nr++;
 267
 268       BEGIN_BATCH(2+nr*3);
 269       OUT_BATCH(_3DSTATE_MAP_STATE | (3*nr));
 270       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 271       for (i = 0 ; i < I915_TEX_UNITS ; i++)
 272          if (dirty & I915_UPLOAD_TEX(i)) {
 273             OUT_BATCH(state->Tex[i][I915_TEXREG_MS2]);
 274             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 275             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 276          }
 277       ADVANCE_BATCH();
 278
 279       BEGIN_BATCH(2+nr*3);
 280       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3*nr));
 281       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 282       for (i = 0 ; i < I915_TEX_UNITS ; i++)
 283          if (dirty & I915_UPLOAD_TEX(i)) {
 284             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 285             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 286             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 287          }
 288       ADVANCE_BATCH();
 289    }
 290
 291    if (dirty & I915_UPLOAD_CONSTANTS) {
 292       if (VERBOSE) fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 293       emit( i915, state->Constant, state->ConstantSize * sizeof(GLuint) );
 294    }
 295
 296    if (dirty & I915_UPLOAD_PROGRAM) {
 297       if (VERBOSE) fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 298
 299       assert((state->Program[0] & 0x1ff)+2 == state->ProgramSize);
 300
 301       emit( i915, state->Program, state->ProgramSize * sizeof(GLuint) );
 302       if (VERBOSE)
 303          i915_disassemble_program( state->Program, state->ProgramSize );
 304    }
 305
 306    state->emitted |= dirty;
 307 }
 308
 309 static void i915_destroy_context( intelContextPtr intel )
 310 {
 311    _tnl_free_vertices(&intel->ctx);
 312 }
 313
 314 static void i915_set_draw_offset( intelContextPtr intel, int offset )
 315 {
 316    i915ContextPtr i915 = I915_CONTEXT(intel);
 317    I915_STATECHANGE( i915, I915_UPLOAD_BUFFERS );
 318    i915->state.Buffer[I915_DESTREG_CBUFADDR2] = offset;
 319 }
 320
 321 static void i915_lost_hardware( intelContextPtr intel )
 322 {
 323    I915_CONTEXT(intel)->state.emitted = 0;
 324 }
 325
 326 static void i915_emit_flush( intelContextPtr intel )
 327 {
 328    BATCH_LOCALS;
 329
 330    BEGIN_BATCH(2);
 331    OUT_BATCH( MI_FLUSH | FLUSH_MAP_CACHE | FLUSH_RENDER_CACHE );
 332    OUT_BATCH( 0 );
 333    ADVANCE_BATCH();
 334 }
 335
 336
 337 void i915InitVtbl( i915ContextPtr i915 )
 338 {
 339    i915->intel.vtbl.alloc_tex_obj = i915AllocTexObj;
 340    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 341    i915->intel.vtbl.clear_with_tris = i915ClearWithTris;
 342    i915->intel.vtbl.destroy = i915_destroy_context;
 343    i915->intel.vtbl.emit_invarient_state = i915_emit_invarient_state;
 344    i915->intel.vtbl.emit_state = i915_emit_state;
 345    i915->intel.vtbl.lost_hardware = i915_lost_hardware;
 346    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 347    i915->intel.vtbl.render_start = i915_render_start;
 348    i915->intel.vtbl.set_draw_offset = i915_set_draw_offset;
 349    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 350    i915->intel.vtbl.emit_flush = i915_emit_flush;
 351 }
 352