1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/renderbuffer.h"
35 #include "main/framebuffer.h"
38 #include "tnl/t_context.h"
39 #include "tnl/t_vertex.h"
40 #include "swrast_setup/swrast_setup.h"
42 #include "intel_batchbuffer.h"
43 #include "intel_mipmap_tree.h"
44 #include "intel_regions.h"
45 #include "intel_tris.h"
46 #include "intel_fbo.h"
47 #include "intel_buffers.h"
50 #include "i915_context.h"
53 i915_render_prevalidate(struct intel_context
*intel
)
55 struct i915_context
*i915
= i915_context(&intel
->ctx
);
57 i915ValidateFragmentProgram(i915
);
61 i915_render_start(struct intel_context
*intel
)
63 intel_prepare_render(intel
);
68 i915_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
70 struct i915_context
*i915
= i915_context(&intel
->ctx
);
71 GLuint st1
= i915
->state
.Stipple
[I915_STPREG_ST1
];
76 case GL_QUADS
: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
78 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
87 i915
->intel
.reduced_primitive
= rprim
;
89 if (st1
!= i915
->state
.Stipple
[I915_STPREG_ST1
]) {
90 INTEL_FIREVERTICES(intel
);
92 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
93 i915
->state
.Stipple
[I915_STPREG_ST1
] = st1
;
98 /* Pull apart the vertex format registers and figure out how large a
99 * vertex is supposed to be.
102 i915_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
104 struct i915_context
*i915
= i915_context(&intel
->ctx
);
105 int lis2
= i915
->state
.Ctx
[I915_CTXREG_LIS2
];
106 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
109 switch (lis4
& S4_VFMT_XYZW_MASK
) {
123 fprintf(stderr
, "no xyzw specified\n");
127 if (lis4
& S4_VFMT_SPEC_FOG
)
129 if (lis4
& S4_VFMT_COLOR
)
131 if (lis4
& S4_VFMT_DEPTH_OFFSET
)
133 if (lis4
& S4_VFMT_POINT_WIDTH
)
135 if (lis4
& S4_VFMT_FOG_PARAM
)
138 for (i
= 0; i
< 8; i
++) {
139 switch (lis2
& S2_TEXCOORD_FMT0_MASK
) {
152 case TEXCOORDFMT_2D_16
:
155 case TEXCOORDFMT_4D_16
:
158 case TEXCOORDFMT_NOT_PRESENT
:
161 fprintf(stderr
, "bad texcoord fmt %d\n", i
);
164 lis2
>>= S2_TEXCOORD_FMT1_SHIFT
;
168 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
170 return sz
== expected
;
175 i915_emit_invarient_state(struct intel_context
*intel
)
181 OUT_BATCH(_3DSTATE_AA_CMD
|
182 AA_LINE_ECAAR_WIDTH_ENABLE
|
183 AA_LINE_ECAAR_WIDTH_1_0
|
184 AA_LINE_REGION_WIDTH_ENABLE
| AA_LINE_REGION_WIDTH_1_0
);
186 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
189 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
192 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
195 /* Don't support texture crossbar yet */
196 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS
|
201 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
203 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD
);
208 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
210 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE
);
212 OUT_BATCH(_3DSTATE_LOAD_INDIRECT
| 0); /* disable indirect state */
219 #define emit(intel, state, size ) \
220 intel_batchbuffer_data(intel, state, size)
223 get_dirty(struct i915_hw_state
*state
)
227 /* Workaround the multitex hang - if one texture unit state is
228 * modified, emit all texture units.
230 dirty
= state
->active
& ~state
->emitted
;
231 if (dirty
& I915_UPLOAD_TEX_ALL
)
232 state
->emitted
&= ~I915_UPLOAD_TEX_ALL
;
233 dirty
= state
->active
& ~state
->emitted
;
239 get_state_size(struct i915_hw_state
*state
)
241 GLuint dirty
= get_dirty(state
);
245 if (dirty
& I915_UPLOAD_INVARIENT
)
248 if (dirty
& I915_UPLOAD_RASTER_RULES
)
249 sz
+= sizeof(state
->RasterRules
);
251 if (dirty
& I915_UPLOAD_CTX
)
252 sz
+= sizeof(state
->Ctx
);
254 if (dirty
& I915_UPLOAD_BLEND
)
255 sz
+= sizeof(state
->Blend
);
257 if (dirty
& I915_UPLOAD_BUFFERS
)
258 sz
+= sizeof(state
->Buffer
);
260 if (dirty
& I915_UPLOAD_STIPPLE
)
261 sz
+= sizeof(state
->Stipple
);
263 if (dirty
& I915_UPLOAD_TEX_ALL
) {
265 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
266 if (dirty
& I915_UPLOAD_TEX(i
))
269 sz
+= (2 + nr
* 3) * sizeof(GLuint
) * 2;
272 if (dirty
& I915_UPLOAD_CONSTANTS
)
273 sz
+= state
->ConstantSize
* sizeof(GLuint
);
275 if (dirty
& I915_UPLOAD_PROGRAM
)
276 sz
+= state
->ProgramSize
* sizeof(GLuint
);
281 /* Push the state into the sarea and/or texture memory.
284 i915_emit_state(struct intel_context
*intel
)
286 struct i915_context
*i915
= i915_context(&intel
->ctx
);
287 struct i915_hw_state
*state
= &i915
->state
;
288 int i
, count
, aper_count
;
290 drm_intel_bo
*aper_array
[3 + I915_TEX_UNITS
];
291 GET_CURRENT_CONTEXT(ctx
);
294 /* We don't hold the lock at this point, so want to make sure that
295 * there won't be a buffer wrap between the state emits and the primitive
298 * It might be better to talk about explicit places where
299 * scheduling is allowed, rather than assume that it is whenever a
300 * batchbuffer fills up.
302 intel_batchbuffer_require_space(intel
,
303 get_state_size(state
) +
304 INTEL_PRIM_EMIT_SIZE
);
307 if (intel
->batch
.bo
== NULL
) {
308 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i915 emit state");
312 dirty
= get_dirty(state
);
314 aper_array
[aper_count
++] = intel
->batch
.bo
;
315 if (dirty
& I915_UPLOAD_BUFFERS
) {
316 if (state
->draw_region
)
317 aper_array
[aper_count
++] = state
->draw_region
->bo
;
318 if (state
->depth_region
)
319 aper_array
[aper_count
++] = state
->depth_region
->bo
;
322 if (dirty
& I915_UPLOAD_TEX_ALL
) {
323 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
324 if (dirty
& I915_UPLOAD_TEX(i
)) {
325 if (state
->tex_buffer
[i
]) {
326 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
332 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
335 intel_batchbuffer_flush(intel
);
338 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i915 emit state");
343 /* work out list of buffers to emit */
345 /* Do this here as we may have flushed the batchbuffer above,
346 * causing more state to be dirty!
348 dirty
= get_dirty(state
);
349 state
->emitted
|= dirty
;
350 assert(get_dirty(state
) == 0);
352 if (INTEL_DEBUG
& DEBUG_STATE
)
353 fprintf(stderr
, "%s dirty: %x\n", __func__
, dirty
);
355 if (dirty
& I915_UPLOAD_INVARIENT
) {
356 if (INTEL_DEBUG
& DEBUG_STATE
)
357 fprintf(stderr
, "I915_UPLOAD_INVARIENT:\n");
358 i915_emit_invarient_state(intel
);
361 if (dirty
& I915_UPLOAD_RASTER_RULES
) {
362 if (INTEL_DEBUG
& DEBUG_STATE
)
363 fprintf(stderr
, "I915_UPLOAD_RASTER_RULES:\n");
364 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
367 if (dirty
& I915_UPLOAD_CTX
) {
368 if (INTEL_DEBUG
& DEBUG_STATE
)
369 fprintf(stderr
, "I915_UPLOAD_CTX:\n");
371 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
374 if (dirty
& I915_UPLOAD_BLEND
) {
375 if (INTEL_DEBUG
& DEBUG_STATE
)
376 fprintf(stderr
, "I915_UPLOAD_BLEND:\n");
378 emit(intel
, state
->Blend
, sizeof(state
->Blend
));
381 if (dirty
& I915_UPLOAD_BUFFERS
) {
384 if (INTEL_DEBUG
& DEBUG_STATE
)
385 fprintf(stderr
, "I915_UPLOAD_BUFFERS:\n");
388 if (state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
)
392 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR0
]);
393 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR1
]);
394 if (state
->draw_region
) {
395 OUT_RELOC(state
->draw_region
->bo
,
396 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
401 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR0
]);
402 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR1
]);
403 if (state
->depth_region
) {
404 OUT_RELOC(state
->depth_region
->bo
,
405 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
410 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV0
]);
411 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV1
]);
412 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR0
]);
413 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR1
]);
414 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR2
]);
415 OUT_BATCH(state
->Buffer
[I915_DESTREG_SENABLE
]);
417 if (state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
)
418 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT0
]);
419 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT1
]);
420 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT2
]);
421 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT3
]);
422 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT4
]);
423 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT5
]);
428 if (dirty
& I915_UPLOAD_STIPPLE
) {
429 if (INTEL_DEBUG
& DEBUG_STATE
)
430 fprintf(stderr
, "I915_UPLOAD_STIPPLE:\n");
431 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
434 /* Combine all the dirty texture state into a single command to
435 * avoid lockups on I915 hardware.
437 if (dirty
& I915_UPLOAD_TEX_ALL
) {
441 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
442 if (dirty
& I915_UPLOAD_TEX(i
))
445 BEGIN_BATCH(2 + nr
* 3);
446 OUT_BATCH(_3DSTATE_MAP_STATE
| (3 * nr
));
447 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
448 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
449 if (dirty
& I915_UPLOAD_TEX(i
)) {
450 OUT_RELOC(state
->tex_buffer
[i
],
451 I915_GEM_DOMAIN_SAMPLER
, 0,
452 state
->tex_offset
[i
]);
454 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS3
]);
455 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS4
]);
459 unwind
= intel
->batch
.used
;
460 BEGIN_BATCH(2 + nr
* 3);
461 OUT_BATCH(_3DSTATE_SAMPLER_STATE
| (3 * nr
));
462 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
463 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
464 if (dirty
& I915_UPLOAD_TEX(i
)) {
465 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS2
]);
466 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS3
]);
467 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS4
]);
470 if (i915
->last_sampler
&&
471 memcmp(intel
->batch
.map
+ i915
->last_sampler
,
472 intel
->batch
.map
+ unwind
,
473 (2 + nr
*3)*sizeof(int)) == 0)
474 intel
->batch
.used
= unwind
;
476 i915
->last_sampler
= unwind
;
479 if (dirty
& I915_UPLOAD_CONSTANTS
) {
480 if (INTEL_DEBUG
& DEBUG_STATE
)
481 fprintf(stderr
, "I915_UPLOAD_CONSTANTS:\n");
482 emit(intel
, state
->Constant
, state
->ConstantSize
* sizeof(GLuint
));
485 if (dirty
& I915_UPLOAD_PROGRAM
) {
486 if (state
->ProgramSize
) {
487 if (INTEL_DEBUG
& DEBUG_STATE
)
488 fprintf(stderr
, "I915_UPLOAD_PROGRAM:\n");
490 assert((state
->Program
[0] & 0x1ff) + 2 == state
->ProgramSize
);
492 emit(intel
, state
->Program
, state
->ProgramSize
* sizeof(GLuint
));
493 if (INTEL_DEBUG
& DEBUG_STATE
)
494 i915_disassemble_program(state
->Program
, state
->ProgramSize
);
498 assert(get_dirty(state
) == 0);
502 i915_destroy_context(struct intel_context
*intel
)
505 struct i915_context
*i915
= i915_context(&intel
->ctx
);
507 intel_region_release(&i915
->state
.draw_region
);
508 intel_region_release(&i915
->state
.depth_region
);
510 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
511 if (i915
->state
.tex_buffer
[i
] != NULL
) {
512 drm_intel_bo_unreference(i915
->state
.tex_buffer
[i
]);
513 i915
->state
.tex_buffer
[i
] = NULL
;
517 _tnl_free_vertices(&intel
->ctx
);
521 i915_set_buf_info_for_region(uint32_t *state
, struct intel_region
*region
,
524 state
[0] = _3DSTATE_BUF_INFO_CMD
;
525 state
[1] = buffer_id
;
527 if (region
!= NULL
) {
528 state
[1] |= BUF_3D_PITCH(region
->pitch
);
530 if (region
->tiling
!= I915_TILING_NONE
) {
531 state
[1] |= BUF_3D_TILED_SURFACE
;
532 if (region
->tiling
== I915_TILING_Y
)
533 state
[1] |= BUF_3D_TILE_WALK_Y
;
536 /* Fill in a default pitch, since 0 is invalid. We'll be
537 * setting the buffer offset to 0 and not referencing the
538 * buffer, so the pitch could really be any valid value.
540 state
[1] |= BUF_3D_PITCH(4096);
544 static uint32_t i915_render_target_format_for_mesa_format
[MESA_FORMAT_COUNT
] =
546 [MESA_FORMAT_B8G8R8A8_UNORM
] = DV_PF_8888
,
547 [MESA_FORMAT_B8G8R8X8_UNORM
] = DV_PF_8888
,
548 [MESA_FORMAT_B5G6R5_UNORM
] = DV_PF_565
| DITHER_FULL_ALWAYS
,
549 [MESA_FORMAT_B5G5R5A1_UNORM
] = DV_PF_1555
| DITHER_FULL_ALWAYS
,
550 [MESA_FORMAT_B4G4R4A4_UNORM
] = DV_PF_4444
| DITHER_FULL_ALWAYS
,
554 i915_render_target_supported(struct intel_context
*intel
,
555 struct gl_renderbuffer
*rb
)
557 mesa_format format
= rb
->Format
;
559 if (format
== MESA_FORMAT_Z24_UNORM_S8_UINT
||
560 format
== MESA_FORMAT_Z24_UNORM_X8_UINT
||
561 format
== MESA_FORMAT_Z_UNORM16
) {
565 return i915_render_target_format_for_mesa_format
[format
] != 0;
569 i915_set_draw_region(struct intel_context
*intel
,
570 struct intel_region
*color_regions
[],
571 struct intel_region
*depth_region
,
574 struct i915_context
*i915
= i915_context(&intel
->ctx
);
575 struct gl_context
*ctx
= &intel
->ctx
;
576 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
577 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
578 struct gl_renderbuffer
*drb
;
579 struct intel_renderbuffer
*idrb
= NULL
;
581 struct i915_hw_state
*state
= &i915
->state
;
582 uint32_t draw_x
, draw_y
, draw_offset
;
584 if (state
->draw_region
!= color_regions
[0]) {
585 intel_region_reference(&state
->draw_region
, color_regions
[0]);
587 if (state
->depth_region
!= depth_region
) {
588 intel_region_reference(&state
->depth_region
, depth_region
);
592 * Set stride/cpp values
594 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_CBUFADDR0
],
595 color_regions
[0], BUF_3D_ID_COLOR_BACK
);
597 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_DBUFADDR0
],
598 depth_region
, BUF_3D_ID_DEPTH
);
601 * Compute/set I915_DESTREG_DV1 value
603 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
604 DSTORG_VERT_BIAS(0x8) | /* .5 */
605 LOD_PRECLAMP_OGL
| TEX_DEFAULT_COLOR_OGL
);
607 value
|= i915_render_target_format_for_mesa_format
[intel_rb_format(irb
)];
612 if (depth_region
&& depth_region
->cpp
== 4) {
613 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
616 value
|= DEPTH_FRMT_16_FIXED
;
618 state
->Buffer
[I915_DESTREG_DV1
] = value
;
620 drb
= ctx
->DrawBuffer
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
622 drb
= ctx
->DrawBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
625 idrb
= intel_renderbuffer(drb
);
627 /* We set up the drawing rectangle to be offset into the color
628 * region's location in the miptree. If it doesn't match with
629 * depth's offsets, we can't render to it.
631 * (Well, not actually true -- the hw grew a bit to let depth's
632 * offset get forced to 0,0. We may want to use that if people are
633 * hitting that case. Also, some configurations may be supportable
634 * by tweaking the start offset of the buffers around, which we
635 * can't do in general due to tiling)
637 FALLBACK(intel
, I915_FALLBACK_DRAW_OFFSET
,
638 idrb
&& irb
&& (idrb
->draw_x
!= irb
->draw_x
||
639 idrb
->draw_y
!= irb
->draw_y
));
642 draw_x
= irb
->draw_x
;
643 draw_y
= irb
->draw_y
;
645 draw_x
= idrb
->draw_x
;
646 draw_y
= idrb
->draw_y
;
652 draw_offset
= (draw_y
<< 16) | draw_x
;
654 FALLBACK(intel
, I915_FALLBACK_DRAW_OFFSET
,
655 (ctx
->DrawBuffer
->Width
+ draw_x
> 2048) ||
656 (ctx
->DrawBuffer
->Height
+ draw_y
> 2048));
657 /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
658 if (draw_offset
!= i915
->last_draw_offset
) {
659 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_FLUSH
| INHIBIT_FLUSH_RENDER_CACHE
;
660 i915
->last_draw_offset
= draw_offset
;
662 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_NOOP
;
664 state
->Buffer
[I915_DESTREG_DRAWRECT1
] = _3DSTATE_DRAWRECT_INFO
;
665 state
->Buffer
[I915_DESTREG_DRAWRECT2
] = 0;
666 state
->Buffer
[I915_DESTREG_DRAWRECT3
] = draw_offset
;
667 state
->Buffer
[I915_DESTREG_DRAWRECT4
] =
668 ((ctx
->DrawBuffer
->Width
+ draw_x
- 1) & 0xffff) |
669 ((ctx
->DrawBuffer
->Height
+ draw_y
- 1) << 16);
670 state
->Buffer
[I915_DESTREG_DRAWRECT5
] = draw_offset
;
672 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
676 i915_update_color_write_enable(struct i915_context
*i915
, bool enable
)
678 uint32_t dw
= i915
->state
.Ctx
[I915_CTXREG_LIS6
];
680 dw
|= S6_COLOR_WRITE_ENABLE
;
682 dw
&= ~S6_COLOR_WRITE_ENABLE
;
683 if (dw
!= i915
->state
.Ctx
[I915_CTXREG_LIS6
]) {
684 I915_STATECHANGE(i915
, I915_UPLOAD_CTX
);
685 i915
->state
.Ctx
[I915_CTXREG_LIS6
] = dw
;
690 * Update the hardware state for drawing into a window or framebuffer object.
692 * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
693 * places within the driver.
695 * Basically, this needs to be called any time the current framebuffer
696 * changes, the renderbuffers change, or we need to draw into different
700 i915_update_draw_buffer(struct intel_context
*intel
)
702 struct i915_context
*i915
= (struct i915_context
*)intel
;
703 struct gl_context
*ctx
= &intel
->ctx
;
704 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
705 struct intel_region
*colorRegion
= NULL
, *depthRegion
= NULL
;
706 struct intel_renderbuffer
*irbDepth
= NULL
, *irbStencil
= NULL
;
709 /* this can happen during the initial context initialization */
713 irbDepth
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
714 irbStencil
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
716 /* Do this here, not core Mesa, since this function is called from
717 * many places within the driver.
719 if (ctx
->NewState
& _NEW_BUFFERS
) {
720 /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
721 _mesa_update_framebuffer(ctx
, ctx
->ReadBuffer
, ctx
->DrawBuffer
);
722 /* this updates the DrawBuffer's Width/Height if it's a FBO */
723 _mesa_update_draw_buffer_bounds(ctx
, ctx
->DrawBuffer
);
726 if (fb
->_Status
!= GL_FRAMEBUFFER_COMPLETE_EXT
) {
727 /* this may occur when we're called by glBindFrameBuffer() during
728 * the process of someone setting up renderbuffers, etc.
730 /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
734 /* How many color buffers are we drawing into?
736 * If there is more than one drawbuffer (GL_FRONT_AND_BACK), or the
737 * drawbuffers are too big, we have to fallback to software.
739 if ((fb
->Width
> ctx
->Const
.MaxRenderbufferSize
)
740 || (fb
->Height
> ctx
->Const
.MaxRenderbufferSize
)) {
741 FALLBACK(intel
, INTEL_FALLBACK_DRAW_BUFFER
, true);
742 } else if (fb
->_NumColorDrawBuffers
> 1) {
743 FALLBACK(intel
, INTEL_FALLBACK_DRAW_BUFFER
, true);
745 struct intel_renderbuffer
*irb
;
746 irb
= intel_renderbuffer(fb
->_ColorDrawBuffers
[0]);
747 colorRegion
= (irb
&& irb
->mt
) ? irb
->mt
->region
: NULL
;
748 FALLBACK(intel
, INTEL_FALLBACK_DRAW_BUFFER
, false);
751 /* Check for depth fallback. */
752 if (irbDepth
&& irbDepth
->mt
) {
753 FALLBACK(intel
, INTEL_FALLBACK_DEPTH_BUFFER
, false);
754 depthRegion
= irbDepth
->mt
->region
;
755 } else if (irbDepth
&& !irbDepth
->mt
) {
756 FALLBACK(intel
, INTEL_FALLBACK_DEPTH_BUFFER
, true);
758 } else { /* !irbDepth */
759 /* No fallback is needed because there is no depth buffer. */
760 FALLBACK(intel
, INTEL_FALLBACK_DEPTH_BUFFER
, false);
764 /* Check for stencil fallback. */
765 if (irbStencil
&& irbStencil
->mt
) {
766 assert(intel_rb_format(irbStencil
) == MESA_FORMAT_Z24_UNORM_S8_UINT
);
767 FALLBACK(intel
, INTEL_FALLBACK_STENCIL_BUFFER
, false);
768 } else if (irbStencil
&& !irbStencil
->mt
) {
769 FALLBACK(intel
, INTEL_FALLBACK_STENCIL_BUFFER
, true);
770 } else { /* !irbStencil */
771 /* No fallback is needed because there is no stencil buffer. */
772 FALLBACK(intel
, INTEL_FALLBACK_STENCIL_BUFFER
, false);
775 /* If we have a (packed) stencil buffer attached but no depth buffer,
776 * we still need to set up the shared depth/stencil state so we can use it.
778 if (depthRegion
== NULL
&& irbStencil
&& irbStencil
->mt
779 && intel_rb_format(irbStencil
) == MESA_FORMAT_Z24_UNORM_S8_UINT
) {
780 depthRegion
= irbStencil
->mt
->region
;
784 * Update depth and stencil test state
786 ctx
->Driver
.Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
787 ctx
->Driver
.Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
.Enabled
);
789 i915_update_color_write_enable(i915
, colorRegion
!= NULL
);
791 intel
->vtbl
.set_draw_region(intel
, &colorRegion
, depthRegion
,
792 fb
->_NumColorDrawBuffers
);
793 intel
->NewGLState
|= _NEW_BUFFERS
;
795 /* Set state we know depends on drawable parameters:
797 intelCalcViewport(ctx
);
798 ctx
->Driver
.Scissor(ctx
);
800 /* Update culling direction which changes depending on the
801 * orientation of the buffer:
803 ctx
->Driver
.FrontFace(ctx
, ctx
->Polygon
.FrontFace
);
807 i915_new_batch(struct intel_context
*intel
)
809 struct i915_context
*i915
= i915_context(&intel
->ctx
);
811 /* Mark all state as needing to be emitted when starting a new batchbuffer.
812 * Using hardware contexts would be an alternative, but they have some
813 * difficulties associated with them (physical address requirements).
815 i915
->state
.emitted
= 0;
816 i915
->last_draw_offset
= 0;
817 i915
->last_sampler
= 0;
819 i915
->current_vb_bo
= NULL
;
820 i915
->current_vertex_size
= 0;
824 i915_assert_not_dirty( struct intel_context
*intel
)
826 struct i915_context
*i915
= i915_context(&intel
->ctx
);
827 GLuint dirty
= get_dirty(&i915
->state
);
833 i915_invalidate_state(struct intel_context
*intel
, GLuint new_state
)
835 struct gl_context
*ctx
= &intel
->ctx
;
837 _swsetup_InvalidateState(ctx
, new_state
);
838 _tnl_InvalidateState(ctx
, new_state
);
839 _tnl_invalidate_vertex_state(ctx
, new_state
);
843 i915InitVtbl(struct i915_context
*i915
)
845 i915
->intel
.vtbl
.check_vertex_size
= i915_check_vertex_size
;
846 i915
->intel
.vtbl
.destroy
= i915_destroy_context
;
847 i915
->intel
.vtbl
.emit_state
= i915_emit_state
;
848 i915
->intel
.vtbl
.new_batch
= i915_new_batch
;
849 i915
->intel
.vtbl
.reduced_primitive_state
= i915_reduced_primitive_state
;
850 i915
->intel
.vtbl
.render_start
= i915_render_start
;
851 i915
->intel
.vtbl
.render_prevalidate
= i915_render_prevalidate
;
852 i915
->intel
.vtbl
.set_draw_region
= i915_set_draw_region
;
853 i915
->intel
.vtbl
.update_draw_buffer
= i915_update_draw_buffer
;
854 i915
->intel
.vtbl
.update_texture_state
= i915UpdateTextureState
;
855 i915
->intel
.vtbl
.assert_not_dirty
= i915_assert_not_dirty
;
856 i915
->intel
.vtbl
.finish_batch
= intel_finish_vb
;
857 i915
->intel
.vtbl
.invalidate_state
= i915_invalidate_state
;
858 i915
->intel
.vtbl
.render_target_supported
= i915_render_target_supported
;