src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "glheader.h"
  31 #include "mtypes.h"
  32 #include "imports.h"
  33 #include "macros.h"
  34 #include "colormac.h"
  35
  36 #include "tnl/t_context.h"
  37 #include "tnl/t_vertex.h"
  38
  39 #include "intel_batchbuffer.h"
  40 #include "intel_tex.h"
  41 #include "intel_regions.h"
  42
  43 #include "i915_reg.h"
  44 #include "i915_context.h"
  45
  46 static void
  47 i915_render_prevalidate(struct intel_context *intel)
  48 {
  49    struct i915_context *i915 = i915_context(&intel->ctx);
  50
  51    i915ValidateFragmentProgram(i915);
  52 }
  53
  54 static void
  55 i915_render_start(struct intel_context *intel)
  56 {
  57 }
  58
  59
  60 static void
  61 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  62 {
  63    struct i915_context *i915 = i915_context(&intel->ctx);
  64    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  65
  66    st1 &= ~ST1_ENABLE;
  67
  68    switch (rprim) {
  69    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  70    case GL_TRIANGLES:
  71       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  72          st1 |= ST1_ENABLE;
  73       break;
  74    case GL_LINES:
  75    case GL_POINTS:
  76    default:
  77       break;
  78    }
  79
  80    i915->intel.reduced_primitive = rprim;
  81
  82    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  83       INTEL_FIREVERTICES(intel);
  84
  85       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  86       i915->state.Stipple[I915_STPREG_ST1] = st1;
  87    }
  88 }
  89
  90
  91 /* Pull apart the vertex format registers and figure out how large a
  92  * vertex is supposed to be.
  93  */
  94 static GLboolean
  95 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
  96 {
  97    struct i915_context *i915 = i915_context(&intel->ctx);
  98    int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
  99    int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
 100    int i, sz = 0;
 101
 102    switch (lis4 & S4_VFMT_XYZW_MASK) {
 103    case S4_VFMT_XY:
 104       sz = 2;
 105       break;
 106    case S4_VFMT_XYZ:
 107       sz = 3;
 108       break;
 109    case S4_VFMT_XYW:
 110       sz = 3;
 111       break;
 112    case S4_VFMT_XYZW:
 113       sz = 4;
 114       break;
 115    default:
 116       fprintf(stderr, "no xyzw specified\n");
 117       return 0;
 118    }
 119
 120    if (lis4 & S4_VFMT_SPEC_FOG)
 121       sz++;
 122    if (lis4 & S4_VFMT_COLOR)
 123       sz++;
 124    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 125       sz++;
 126    if (lis4 & S4_VFMT_POINT_WIDTH)
 127       sz++;
 128    if (lis4 & S4_VFMT_FOG_PARAM)
 129       sz++;
 130
 131    for (i = 0; i < 8; i++) {
 132       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 133       case TEXCOORDFMT_2D:
 134          sz += 2;
 135          break;
 136       case TEXCOORDFMT_3D:
 137          sz += 3;
 138          break;
 139       case TEXCOORDFMT_4D:
 140          sz += 4;
 141          break;
 142       case TEXCOORDFMT_1D:
 143          sz += 1;
 144          break;
 145       case TEXCOORDFMT_2D_16:
 146          sz += 1;
 147          break;
 148       case TEXCOORDFMT_4D_16:
 149          sz += 2;
 150          break;
 151       case TEXCOORDFMT_NOT_PRESENT:
 152          break;
 153       default:
 154          fprintf(stderr, "bad texcoord fmt %d\n", i);
 155          return GL_FALSE;
 156       }
 157       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 158    }
 159
 160    if (sz != expected)
 161       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 162
 163    return sz == expected;
 164 }
 165
 166
 167 static void
 168 i915_emit_invarient_state(struct intel_context *intel)
 169 {
 170    BATCH_LOCALS;
 171
 172    BEGIN_BATCH(200, 0);
 173
 174    OUT_BATCH(_3DSTATE_AA_CMD |
 175              AA_LINE_ECAAR_WIDTH_ENABLE |
 176              AA_LINE_ECAAR_WIDTH_1_0 |
 177              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 178
 179    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 180    OUT_BATCH(0);
 181
 182    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 183    OUT_BATCH(0);
 184
 185    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 186    OUT_BATCH(0);
 187
 188    /* Don't support texture crossbar yet */
 189    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 190              CSB_TCB(0, 0) |
 191              CSB_TCB(1, 1) |
 192              CSB_TCB(2, 2) |
 193              CSB_TCB(3, 3) |
 194              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 195
 196    OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 197              ENABLE_POINT_RASTER_RULE |
 198              OGL_POINT_RASTER_RULE |
 199              ENABLE_LINE_STRIP_PROVOKE_VRTX |
 200              ENABLE_TRI_FAN_PROVOKE_VRTX |
 201              LINE_STRIP_PROVOKE_VRTX(1) |
 202              TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
 203
 204    /* Need to initialize this to zero.
 205     */
 206    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 207    OUT_BATCH(0);
 208
 209    /* XXX: Use this */
 210    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 211
 212    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 213    OUT_BATCH(0);
 214    OUT_BATCH(0);
 215
 216    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 217
 218    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 219    OUT_BATCH(0);
 220
 221
 222    /* Don't support twosided stencil yet */
 223    OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
 224    OUT_BATCH(0);
 225
 226    ADVANCE_BATCH();
 227 }
 228
 229
 230 #define emit(intel, state, size )                    \
 231    intel_batchbuffer_data(intel->batch, state, size, 0 )
 232
 233 static GLuint
 234 get_dirty(struct i915_hw_state *state)
 235 {
 236    GLuint dirty;
 237
 238    /* Workaround the multitex hang - if one texture unit state is
 239     * modified, emit all texture units.
 240     */
 241    dirty = state->active & ~state->emitted;
 242    if (dirty & I915_UPLOAD_TEX_ALL)
 243       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 244    dirty = state->active & ~state->emitted;
 245    return dirty;
 246 }
 247
 248
 249 static GLuint
 250 get_state_size(struct i915_hw_state *state)
 251 {
 252    GLuint dirty = get_dirty(state);
 253    GLuint i;
 254    GLuint sz = 0;
 255
 256    if (dirty & I915_UPLOAD_INVARIENT)
 257       sz += 30 * 4;
 258
 259    if (dirty & I915_UPLOAD_CTX)
 260       sz += sizeof(state->Ctx);
 261
 262    if (dirty & I915_UPLOAD_BUFFERS)
 263       sz += sizeof(state->Buffer);
 264
 265    if (dirty & I915_UPLOAD_STIPPLE)
 266       sz += sizeof(state->Stipple);
 267
 268    if (dirty & I915_UPLOAD_FOG)
 269       sz += sizeof(state->Fog);
 270
 271    if (dirty & I915_UPLOAD_TEX_ALL) {
 272       int nr = 0;
 273       for (i = 0; i < I915_TEX_UNITS; i++)
 274          if (dirty & I915_UPLOAD_TEX(i))
 275             nr++;
 276
 277       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 278    }
 279
 280    if (dirty & I915_UPLOAD_CONSTANTS)
 281       sz += state->ConstantSize * sizeof(GLuint);
 282
 283    if (dirty & I915_UPLOAD_PROGRAM)
 284       sz += state->ProgramSize * sizeof(GLuint);
 285
 286    return sz;
 287 }
 288
 289
 290 /* Push the state into the sarea and/or texture memory.
 291  */
 292 static void
 293 i915_do_emit_state(struct intel_context *intel)
 294 {
 295    struct i915_context *i915 = i915_context(&intel->ctx);
 296    struct i915_hw_state *state = i915->current;
 297    int i;
 298    GLuint dirty;
 299    BATCH_LOCALS;
 300
 301    /* We don't hold the lock at this point, so want to make sure that
 302     * there won't be a buffer wrap.
 303     *
 304     * It might be better to talk about explicit places where
 305     * scheduling is allowed, rather than assume that it is whenever a
 306     * batchbuffer fills up.
 307     */
 308    intel_batchbuffer_require_space(intel->batch, get_state_size(state), 0);
 309
 310    /* Workaround.  There are cases I haven't been able to track down
 311     * where we aren't emitting a full state at the start of a new
 312     * batchbuffer.  This code spots that we are on a new batchbuffer
 313     * and forces a full state emit no matter what.
 314     *
 315     * In the normal case state->emitted is already zero, this code is
 316     * another set of checks to make sure it really is.
 317     */
 318    if (intel->batch->id != intel->last_state_batch_id ||
 319        intel->batch->map == intel->batch->ptr)
 320    {
 321       state->emitted = 0;
 322       intel_batchbuffer_require_space(intel->batch, get_state_size(state), 0);
 323    }
 324
 325    /* Do this here as we may have flushed the batchbuffer above,
 326     * causing more state to be dirty!
 327     */
 328    dirty = get_dirty(state);
 329    state->emitted |= dirty;
 330    assert(get_dirty(state) == 0);
 331
 332    if (intel->batch->id != intel->last_state_batch_id) {
 333       assert(dirty & I915_UPLOAD_CTX);
 334       intel->last_state_batch_id = intel->batch->id;
 335    }
 336
 337    if (INTEL_DEBUG & DEBUG_STATE)
 338       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 339
 340    if (dirty & I915_UPLOAD_INVARIENT) {
 341       if (INTEL_DEBUG & DEBUG_STATE)
 342          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 343       i915_emit_invarient_state(intel);
 344    }
 345
 346    if (dirty & I915_UPLOAD_CTX) {
 347       if (INTEL_DEBUG & DEBUG_STATE)
 348          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 349
 350       emit(intel, state->Ctx, sizeof(state->Ctx));
 351    }
 352
 353    if (dirty & I915_UPLOAD_BUFFERS) {
 354       if (INTEL_DEBUG & DEBUG_STATE)
 355          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 356       BEGIN_BATCH(I915_DEST_SETUP_SIZE + 2, 0);
 357       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 358       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 359       OUT_RELOC(state->draw_region->buffer,
 360                 DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
 361                 state->draw_region->draw_offset);
 362
 363       if (state->depth_region) {
 364          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 365          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 366          OUT_RELOC(state->depth_region->buffer,
 367                    DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
 368                    state->depth_region->draw_offset);
 369       }
 370
 371       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 372       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 373       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 374       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 375       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 376       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 377       ADVANCE_BATCH();
 378    }
 379
 380    if (dirty & I915_UPLOAD_STIPPLE) {
 381       if (INTEL_DEBUG & DEBUG_STATE)
 382          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 383       emit(intel, state->Stipple, sizeof(state->Stipple));
 384    }
 385
 386    if (dirty & I915_UPLOAD_FOG) {
 387       if (INTEL_DEBUG & DEBUG_STATE)
 388          fprintf(stderr, "I915_UPLOAD_FOG:\n");
 389       emit(intel, state->Fog, sizeof(state->Fog));
 390    }
 391
 392    /* Combine all the dirty texture state into a single command to
 393     * avoid lockups on I915 hardware.
 394     */
 395    if (dirty & I915_UPLOAD_TEX_ALL) {
 396       int nr = 0;
 397
 398       for (i = 0; i < I915_TEX_UNITS; i++)
 399          if (dirty & I915_UPLOAD_TEX(i))
 400             nr++;
 401
 402       BEGIN_BATCH(2 + nr * 3, 0);
 403       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 404       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 405       for (i = 0; i < I915_TEX_UNITS; i++)
 406          if (dirty & I915_UPLOAD_TEX(i)) {
 407
 408             if (state->tex_buffer[i]) {
 409                OUT_RELOC(state->tex_buffer[i],
 410                          DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
 411                          state->tex_offset[i]);
 412             }
 413             else if (state == &i915->meta) {
 414                assert(i == 0);
 415                OUT_BATCH(0);
 416             }
 417             else {
 418                OUT_BATCH(state->tex_offset[i]);
 419             }
 420
 421             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 422             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 423          }
 424       ADVANCE_BATCH();
 425
 426       BEGIN_BATCH(2 + nr * 3, 0);
 427       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 428       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 429       for (i = 0; i < I915_TEX_UNITS; i++)
 430          if (dirty & I915_UPLOAD_TEX(i)) {
 431             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 432             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 433             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 434          }
 435       ADVANCE_BATCH();
 436    }
 437
 438    if (dirty & I915_UPLOAD_CONSTANTS) {
 439       if (INTEL_DEBUG & DEBUG_STATE)
 440          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 441       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 442    }
 443
 444    if (dirty & I915_UPLOAD_PROGRAM) {
 445       if (state->ProgramSize) {
 446          if (INTEL_DEBUG & DEBUG_STATE)
 447             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 448
 449          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 450
 451          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 452          if (INTEL_DEBUG & DEBUG_STATE)
 453             i915_disassemble_program(state->Program, state->ProgramSize);
 454       }
 455    }
 456
 457    intel->batch->dirty_state &= ~dirty;
 458    assert(get_dirty(state) == 0);
 459 }
 460
 461 static void
 462 i915_emit_state(struct intel_context *intel)
 463 {
 464    struct i915_context *i915 = i915_context(&intel->ctx);
 465
 466    i915_do_emit_state( intel );
 467
 468    /* Second chance - catch batchbuffer wrap in the middle of state
 469     * emit.  This shouldn't happen but it has been observed in
 470     * testing.
 471     */
 472    if (get_dirty( i915->current )) {
 473       /* Force a full re-emit if this happens.
 474        */
 475       i915->current->emitted = 0;
 476       i915_do_emit_state( intel );
 477    }
 478
 479    assert(get_dirty(i915->current) == 0);
 480    assert((intel->batch->dirty_state & (1<<1)) == 0);
 481 }
 482
 483 static void
 484 i915_destroy_context(struct intel_context *intel)
 485 {
 486    GLuint i;
 487    struct i915_context *i915 = i915_context(&intel->ctx);
 488
 489    for (i = 0; i < I915_TEX_UNITS; i++) {
 490       if (i915->state.tex_buffer[i] != NULL) {
 491          dri_bo_unreference(i915->state.tex_buffer[i]);
 492          i915->state.tex_buffer[i] = NULL;
 493       }
 494    }
 495
 496    _tnl_free_vertices(&intel->ctx);
 497 }
 498
 499
 500 /**
 501  * Set the drawing regions for the color and depth/stencil buffers.
 502  * This involves setting the pitch, cpp and buffer ID/location.
 503  * Also set pixel format for color and Z rendering
 504  * Used for setting both regular and meta state.
 505  */
 506 void
 507 i915_state_draw_region(struct intel_context *intel,
 508                        struct i915_hw_state *state,
 509                        struct intel_region *color_region,
 510                        struct intel_region *depth_region)
 511 {
 512    struct i915_context *i915 = i915_context(&intel->ctx);
 513    GLuint value;
 514
 515    ASSERT(state == &i915->state || state == &i915->meta);
 516
 517    if (state->draw_region != color_region) {
 518       intel_region_release(&state->draw_region);
 519       intel_region_reference(&state->draw_region, color_region);
 520    }
 521    if (state->depth_region != depth_region) {
 522       intel_region_release(&state->depth_region);
 523       intel_region_reference(&state->depth_region, depth_region);
 524    }
 525
 526    /*
 527     * Set stride/cpp values
 528     */
 529    if (color_region) {
 530       state->Buffer[I915_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 531       state->Buffer[I915_DESTREG_CBUFADDR1] =
 532          (BUF_3D_ID_COLOR_BACK |
 533           BUF_3D_PITCH(color_region->pitch * color_region->cpp) |
 534           BUF_3D_USE_FENCE);
 535    }
 536
 537    if (depth_region) {
 538       state->Buffer[I915_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 539       state->Buffer[I915_DESTREG_DBUFADDR1] =
 540          (BUF_3D_ID_DEPTH |
 541           BUF_3D_PITCH(depth_region->pitch * depth_region->cpp) |
 542           BUF_3D_USE_FENCE);
 543    }
 544
 545    /*
 546     * Compute/set I915_DESTREG_DV1 value
 547     */
 548    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 549             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 550             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 551    if (color_region && color_region->cpp == 4) {
 552       value |= DV_PF_8888;
 553    }
 554    else {
 555       value |= (DITHER_FULL_ALWAYS | DV_PF_565);
 556    }
 557    if (depth_region && depth_region->cpp == 4) {
 558       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 559    }
 560    else {
 561       value |= DEPTH_FRMT_16_FIXED;
 562    }
 563    state->Buffer[I915_DESTREG_DV1] = value;
 564
 565    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 566 }
 567
 568
 569 static void
 570 i915_set_draw_region(struct intel_context *intel,
 571                      struct intel_region *color_region,
 572                      struct intel_region *depth_region)
 573 {
 574    struct i915_context *i915 = i915_context(&intel->ctx);
 575    i915_state_draw_region(intel, &i915->state, color_region, depth_region);
 576 }
 577
 578
 579
 580 static void
 581 i915_lost_hardware(struct intel_context *intel)
 582 {
 583    struct i915_context *i915 = i915_context(&intel->ctx);
 584    i915->state.emitted = 0;
 585 }
 586
 587 static GLuint
 588 i915_flush_cmd(void)
 589 {
 590    return MI_FLUSH | FLUSH_MAP_CACHE;
 591 }
 592
 593 static void
 594 i915_assert_not_dirty( struct intel_context *intel )
 595 {
 596    struct i915_context *i915 = i915_context(&intel->ctx);
 597    struct i915_hw_state *state = i915->current;
 598    GLuint dirty = get_dirty(state);
 599    assert(!dirty);
 600 }
 601
 602
 603 void
 604 i915InitVtbl(struct i915_context *i915)
 605 {
 606    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 607    i915->intel.vtbl.destroy = i915_destroy_context;
 608    i915->intel.vtbl.emit_state = i915_emit_state;
 609    i915->intel.vtbl.lost_hardware = i915_lost_hardware;
 610    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 611    i915->intel.vtbl.render_start = i915_render_start;
 612    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 613    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 614    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 615    i915->intel.vtbl.flush_cmd = i915_flush_cmd;
 616    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 617 }