src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "main/glheader.h"
  31 #include "main/mtypes.h"
  32 #include "main/imports.h"
  33 #include "main/macros.h"
  34 #include "main/colormac.h"
  35
  36 #include "tnl/t_context.h"
  37 #include "tnl/t_vertex.h"
  38
  39 #include "intel_batchbuffer.h"
  40 #include "intel_regions.h"
  41 #include "intel_tris.h"
  42 #include "intel_fbo.h"
  43 #include "intel_chipset.h"
  44
  45 #include "i915_reg.h"
  46 #include "i915_context.h"
  47
  48 #include "glapi/glapi.h"
  49
  50 static void
  51 i915_render_prevalidate(struct intel_context *intel)
  52 {
  53    struct i915_context *i915 = i915_context(&intel->ctx);
  54
  55    i915ValidateFragmentProgram(i915);
  56 }
  57
  58 static void
  59 i915_render_start(struct intel_context *intel)
  60 {
  61 }
  62
  63
  64 static void
  65 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  66 {
  67    struct i915_context *i915 = i915_context(&intel->ctx);
  68    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  69
  70    st1 &= ~ST1_ENABLE;
  71
  72    switch (rprim) {
  73    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  74    case GL_TRIANGLES:
  75       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  76          st1 |= ST1_ENABLE;
  77       break;
  78    case GL_LINES:
  79    case GL_POINTS:
  80    default:
  81       break;
  82    }
  83
  84    i915->intel.reduced_primitive = rprim;
  85
  86    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  87       INTEL_FIREVERTICES(intel);
  88
  89       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  90       i915->state.Stipple[I915_STPREG_ST1] = st1;
  91    }
  92 }
  93
  94
  95 /* Pull apart the vertex format registers and figure out how large a
  96  * vertex is supposed to be.
  97  */
  98 static GLboolean
  99 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
 100 {
 101    struct i915_context *i915 = i915_context(&intel->ctx);
 102    int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
 103    int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
 104    int i, sz = 0;
 105
 106    switch (lis4 & S4_VFMT_XYZW_MASK) {
 107    case S4_VFMT_XY:
 108       sz = 2;
 109       break;
 110    case S4_VFMT_XYZ:
 111       sz = 3;
 112       break;
 113    case S4_VFMT_XYW:
 114       sz = 3;
 115       break;
 116    case S4_VFMT_XYZW:
 117       sz = 4;
 118       break;
 119    default:
 120       fprintf(stderr, "no xyzw specified\n");
 121       return 0;
 122    }
 123
 124    if (lis4 & S4_VFMT_SPEC_FOG)
 125       sz++;
 126    if (lis4 & S4_VFMT_COLOR)
 127       sz++;
 128    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 129       sz++;
 130    if (lis4 & S4_VFMT_POINT_WIDTH)
 131       sz++;
 132    if (lis4 & S4_VFMT_FOG_PARAM)
 133       sz++;
 134
 135    for (i = 0; i < 8; i++) {
 136       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 137       case TEXCOORDFMT_2D:
 138          sz += 2;
 139          break;
 140       case TEXCOORDFMT_3D:
 141          sz += 3;
 142          break;
 143       case TEXCOORDFMT_4D:
 144          sz += 4;
 145          break;
 146       case TEXCOORDFMT_1D:
 147          sz += 1;
 148          break;
 149       case TEXCOORDFMT_2D_16:
 150          sz += 1;
 151          break;
 152       case TEXCOORDFMT_4D_16:
 153          sz += 2;
 154          break;
 155       case TEXCOORDFMT_NOT_PRESENT:
 156          break;
 157       default:
 158          fprintf(stderr, "bad texcoord fmt %d\n", i);
 159          return GL_FALSE;
 160       }
 161       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 162    }
 163
 164    if (sz != expected)
 165       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 166
 167    return sz == expected;
 168 }
 169
 170
 171 static void
 172 i915_emit_invarient_state(struct intel_context *intel)
 173 {
 174    BATCH_LOCALS;
 175
 176    BEGIN_BATCH(17, IGNORE_CLIPRECTS);
 177
 178    OUT_BATCH(_3DSTATE_AA_CMD |
 179              AA_LINE_ECAAR_WIDTH_ENABLE |
 180              AA_LINE_ECAAR_WIDTH_1_0 |
 181              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 182
 183    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 184    OUT_BATCH(0);
 185
 186    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 187    OUT_BATCH(0);
 188
 189    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 190    OUT_BATCH(0);
 191
 192    /* Don't support texture crossbar yet */
 193    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 194              CSB_TCB(0, 0) |
 195              CSB_TCB(1, 1) |
 196              CSB_TCB(2, 2) |
 197              CSB_TCB(3, 3) |
 198              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 199
 200    /* Need to initialize this to zero.
 201     */
 202    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 203    OUT_BATCH(0);
 204
 205    /* XXX: Use this */
 206    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 207
 208    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 209    OUT_BATCH(0);
 210    OUT_BATCH(0);
 211
 212    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 213
 214    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 215    OUT_BATCH(0);
 216
 217    ADVANCE_BATCH();
 218 }
 219
 220
 221 #define emit(intel, state, size )                    \
 222    intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
 223
 224 static GLuint
 225 get_dirty(struct i915_hw_state *state)
 226 {
 227    GLuint dirty;
 228
 229    /* Workaround the multitex hang - if one texture unit state is
 230     * modified, emit all texture units.
 231     */
 232    dirty = state->active & ~state->emitted;
 233    if (dirty & I915_UPLOAD_TEX_ALL)
 234       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 235    dirty = state->active & ~state->emitted;
 236    return dirty;
 237 }
 238
 239
 240 static GLuint
 241 get_state_size(struct i915_hw_state *state)
 242 {
 243    GLuint dirty = get_dirty(state);
 244    GLuint i;
 245    GLuint sz = 0;
 246
 247    if (dirty & I915_UPLOAD_INVARIENT)
 248       sz += 30 * 4;
 249
 250    if (dirty & I915_UPLOAD_RASTER_RULES)
 251       sz += sizeof(state->RasterRules);
 252
 253    if (dirty & I915_UPLOAD_CTX)
 254       sz += sizeof(state->Ctx);
 255
 256    if (dirty & I915_UPLOAD_BUFFERS)
 257       sz += sizeof(state->Buffer);
 258
 259    if (dirty & I915_UPLOAD_STIPPLE)
 260       sz += sizeof(state->Stipple);
 261
 262    if (dirty & I915_UPLOAD_FOG)
 263       sz += sizeof(state->Fog);
 264
 265    if (dirty & I915_UPLOAD_TEX_ALL) {
 266       int nr = 0;
 267       for (i = 0; i < I915_TEX_UNITS; i++)
 268          if (dirty & I915_UPLOAD_TEX(i))
 269             nr++;
 270
 271       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 272    }
 273
 274    if (dirty & I915_UPLOAD_CONSTANTS)
 275       sz += state->ConstantSize * sizeof(GLuint);
 276
 277    if (dirty & I915_UPLOAD_PROGRAM)
 278       sz += state->ProgramSize * sizeof(GLuint);
 279
 280    return sz;
 281 }
 282
 283 /* Push the state into the sarea and/or texture memory.
 284  */
 285 static void
 286 i915_emit_state(struct intel_context *intel)
 287 {
 288    struct i915_context *i915 = i915_context(&intel->ctx);
 289    struct i915_hw_state *state = i915->current;
 290    int i, count, aper_count;
 291    GLuint dirty;
 292    dri_bo *aper_array[3 + I915_TEX_UNITS];
 293    GET_CURRENT_CONTEXT(ctx);
 294    BATCH_LOCALS;
 295
 296    /* We don't hold the lock at this point, so want to make sure that
 297     * there won't be a buffer wrap between the state emits and the primitive
 298     * emit header.
 299     *
 300     * It might be better to talk about explicit places where
 301     * scheduling is allowed, rather than assume that it is whenever a
 302     * batchbuffer fills up.
 303     *
 304     * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
 305     * will be emitted under.
 306     */
 307    intel_batchbuffer_require_space(intel->batch,
 308                                    get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
 309                                    LOOP_CLIPRECTS);
 310    count = 0;
 311  again:
 312    aper_count = 0;
 313    dirty = get_dirty(state);
 314
 315    aper_array[aper_count++] = intel->batch->buf;
 316    if (dirty & I915_UPLOAD_BUFFERS) {
 317       aper_array[aper_count++] = state->draw_region->buffer;
 318       if (state->depth_region)
 319          aper_array[aper_count++] = state->depth_region->buffer;
 320    }
 321
 322    if (dirty & I915_UPLOAD_TEX_ALL) {
 323       for (i = 0; i < I915_TEX_UNITS; i++) {
 324          if (dirty & I915_UPLOAD_TEX(i)) {
 325             if (state->tex_buffer[i]) {
 326                aper_array[aper_count++] = state->tex_buffer[i];
 327             }
 328          }
 329       }
 330    }
 331
 332    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
 333        if (count == 0) {
 334            count++;
 335            intel_batchbuffer_flush(intel->batch);
 336            goto again;
 337        } else {
 338            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 339            assert(0);
 340        }
 341    }
 342
 343    /* work out list of buffers to emit */
 344
 345    /* Do this here as we may have flushed the batchbuffer above,
 346     * causing more state to be dirty!
 347     */
 348    dirty = get_dirty(state);
 349    state->emitted |= dirty;
 350    assert(get_dirty(state) == 0);
 351
 352    if (INTEL_DEBUG & DEBUG_STATE)
 353       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 354
 355    if (dirty & I915_UPLOAD_INVARIENT) {
 356       if (INTEL_DEBUG & DEBUG_STATE)
 357          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 358       i915_emit_invarient_state(intel);
 359    }
 360
 361    if (dirty & I915_UPLOAD_RASTER_RULES) {
 362       if (INTEL_DEBUG & DEBUG_STATE)
 363          fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
 364       emit(intel, state->RasterRules, sizeof(state->RasterRules));
 365    }
 366
 367    if (dirty & I915_UPLOAD_CTX) {
 368       if (INTEL_DEBUG & DEBUG_STATE)
 369          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 370
 371       emit(intel, state->Ctx, sizeof(state->Ctx));
 372    }
 373
 374    if (dirty & I915_UPLOAD_BUFFERS) {
 375       GLuint count = 9;
 376
 377       if (INTEL_DEBUG & DEBUG_STATE)
 378          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 379
 380       if (state->depth_region)
 381           count += 3;
 382
 383       if (intel->constant_cliprect)
 384           count += 6;
 385
 386       BEGIN_BATCH(count, IGNORE_CLIPRECTS);
 387       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 388       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 389       OUT_RELOC(state->draw_region->buffer,
 390                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 391                 state->draw_region->draw_offset);
 392
 393       if (state->depth_region) {
 394          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 395          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 396          OUT_RELOC(state->depth_region->buffer,
 397                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 398                    state->depth_region->draw_offset);
 399       }
 400
 401       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 402       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 403       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 404       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 405       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 406       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 407
 408       if (intel->constant_cliprect) {
 409          assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
 410          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
 411          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
 412          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
 413          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
 414          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
 415          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
 416       }
 417
 418       ADVANCE_BATCH();
 419    }
 420
 421    if (dirty & I915_UPLOAD_STIPPLE) {
 422       if (INTEL_DEBUG & DEBUG_STATE)
 423          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 424       emit(intel, state->Stipple, sizeof(state->Stipple));
 425    }
 426
 427    if (dirty & I915_UPLOAD_FOG) {
 428       if (INTEL_DEBUG & DEBUG_STATE)
 429          fprintf(stderr, "I915_UPLOAD_FOG:\n");
 430       emit(intel, state->Fog, sizeof(state->Fog));
 431    }
 432
 433    /* Combine all the dirty texture state into a single command to
 434     * avoid lockups on I915 hardware.
 435     */
 436    if (dirty & I915_UPLOAD_TEX_ALL) {
 437       int nr = 0;
 438
 439       for (i = 0; i < I915_TEX_UNITS; i++)
 440          if (dirty & I915_UPLOAD_TEX(i))
 441             nr++;
 442
 443       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 444       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 445       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 446       for (i = 0; i < I915_TEX_UNITS; i++)
 447          if (dirty & I915_UPLOAD_TEX(i)) {
 448
 449             if (state->tex_buffer[i]) {
 450                OUT_RELOC(state->tex_buffer[i],
 451                          I915_GEM_DOMAIN_SAMPLER, 0,
 452                          state->tex_offset[i]);
 453             }
 454             else if (state == &i915->meta) {
 455                assert(i == 0);
 456                OUT_BATCH(0);
 457             }
 458             else {
 459                OUT_BATCH(state->tex_offset[i]);
 460             }
 461
 462             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 463             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 464          }
 465       ADVANCE_BATCH();
 466
 467       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 468       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 469       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 470       for (i = 0; i < I915_TEX_UNITS; i++)
 471          if (dirty & I915_UPLOAD_TEX(i)) {
 472             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 473             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 474             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 475          }
 476       ADVANCE_BATCH();
 477    }
 478
 479    if (dirty & I915_UPLOAD_CONSTANTS) {
 480       if (INTEL_DEBUG & DEBUG_STATE)
 481          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 482       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 483    }
 484
 485    if (dirty & I915_UPLOAD_PROGRAM) {
 486       if (state->ProgramSize) {
 487          if (INTEL_DEBUG & DEBUG_STATE)
 488             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 489
 490          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 491
 492          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 493          if (INTEL_DEBUG & DEBUG_STATE)
 494             i915_disassemble_program(state->Program, state->ProgramSize);
 495       }
 496    }
 497
 498    intel->batch->dirty_state &= ~dirty;
 499    assert(get_dirty(state) == 0);
 500    assert((intel->batch->dirty_state & (1<<1)) == 0);
 501 }
 502
 503 static void
 504 i915_destroy_context(struct intel_context *intel)
 505 {
 506    GLuint i;
 507    struct i915_context *i915 = i915_context(&intel->ctx);
 508
 509    intel_region_release(&i915->state.draw_region);
 510    intel_region_release(&i915->state.depth_region);
 511    intel_region_release(&i915->meta.draw_region);
 512    intel_region_release(&i915->meta.depth_region);
 513    intel_region_release(&i915->initial.draw_region);
 514    intel_region_release(&i915->initial.depth_region);
 515
 516    for (i = 0; i < I915_TEX_UNITS; i++) {
 517       if (i915->state.tex_buffer[i] != NULL) {
 518          dri_bo_unreference(i915->state.tex_buffer[i]);
 519          i915->state.tex_buffer[i] = NULL;
 520       }
 521    }
 522
 523    _tnl_free_vertices(&intel->ctx);
 524 }
 525
 526 void
 527 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 528                              uint32_t buffer_id)
 529 {
 530    state[0] = _3DSTATE_BUF_INFO_CMD;
 531    state[1] = buffer_id;
 532
 533    if (region != NULL) {
 534       state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
 535
 536       if (region->tiling != I915_TILING_NONE) {
 537          state[1] |= BUF_3D_TILED_SURFACE;
 538          if (region->tiling == I915_TILING_Y)
 539             state[1] |= BUF_3D_TILE_WALK_Y;
 540       }
 541    }
 542 }
 543
 544 /**
 545  * Set the drawing regions for the color and depth/stencil buffers.
 546  * This involves setting the pitch, cpp and buffer ID/location.
 547  * Also set pixel format for color and Z rendering
 548  * Used for setting both regular and meta state.
 549  */
 550 void
 551 i915_state_draw_region(struct intel_context *intel,
 552                        struct i915_hw_state *state,
 553                        struct intel_region *color_region,
 554                        struct intel_region *depth_region)
 555 {
 556    struct i915_context *i915 = i915_context(&intel->ctx);
 557    GLcontext *ctx = &intel->ctx;
 558    struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
 559    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 560    GLuint value;
 561
 562    ASSERT(state == &i915->state || state == &i915->meta);
 563
 564    if (state->draw_region != color_region) {
 565       intel_region_release(&state->draw_region);
 566       intel_region_reference(&state->draw_region, color_region);
 567    }
 568    if (state->depth_region != depth_region) {
 569       intel_region_release(&state->depth_region);
 570       intel_region_reference(&state->depth_region, depth_region);
 571    }
 572
 573    /*
 574     * Set stride/cpp values
 575     */
 576    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
 577                                 color_region, BUF_3D_ID_COLOR_BACK);
 578
 579    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
 580                                 depth_region, BUF_3D_ID_DEPTH);
 581
 582    /*
 583     * Compute/set I915_DESTREG_DV1 value
 584     */
 585    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 586             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 587             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 588    if (irb != NULL) {
 589       switch (irb->Base.Format) {
 590       case MESA_FORMAT_ARGB8888:
 591       case MESA_FORMAT_XRGB8888:
 592          value |= DV_PF_8888;
 593          break;
 594       case MESA_FORMAT_RGB565:
 595          value |= DV_PF_565 | DITHER_FULL_ALWAYS;
 596          break;
 597       case MESA_FORMAT_ARGB1555:
 598          value |= DV_PF_1555 | DITHER_FULL_ALWAYS;
 599          break;
 600       case MESA_FORMAT_ARGB4444:
 601          value |= DV_PF_4444 | DITHER_FULL_ALWAYS;
 602          break;
 603       default:
 604          _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
 605                        irb->Base.Format);
 606       }
 607    }
 608
 609    /* This isn't quite safe, thus being hidden behind an option.  When changing
 610     * the value of this bit, the pipeline needs to be MI_FLUSHed.  And it
 611     * can only be set when a depth buffer is already defined.
 612     */
 613    if (IS_945(intel->intelScreen->deviceID) && intel->use_early_z &&
 614        depth_region->tiling != I915_TILING_NONE)
 615       value |= CLASSIC_EARLY_DEPTH;
 616
 617    if (depth_region && depth_region->cpp == 4) {
 618       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 619    }
 620    else {
 621       value |= DEPTH_FRMT_16_FIXED;
 622    }
 623    state->Buffer[I915_DESTREG_DV1] = value;
 624
 625    if (intel->constant_cliprect) {
 626       state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
 627       state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
 628       state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
 629       state->Buffer[I915_DESTREG_DRAWRECT3] =
 630          (ctx->DrawBuffer->Width & 0xffff) |
 631          (ctx->DrawBuffer->Height << 16);
 632       state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
 633       state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
 634    } else {
 635       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
 636       state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP;
 637       state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP;
 638       state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP;
 639       state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP;
 640       state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP;
 641    }
 642
 643    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 644 }
 645
 646
 647 static void
 648 i915_set_draw_region(struct intel_context *intel,
 649                      struct intel_region *color_regions[],
 650                      struct intel_region *depth_region,
 651                      GLuint num_regions)
 652 {
 653    struct i915_context *i915 = i915_context(&intel->ctx);
 654    i915_state_draw_region(intel, &i915->state, color_regions[0], depth_region);
 655 }
 656
 657
 658
 659 static void
 660 i915_new_batch(struct intel_context *intel)
 661 {
 662    struct i915_context *i915 = i915_context(&intel->ctx);
 663
 664    /* Mark all state as needing to be emitted when starting a new batchbuffer.
 665     * Using hardware contexts would be an alternative, but they have some
 666     * difficulties associated with them (physical address requirements).
 667     */
 668    i915->state.emitted = 0;
 669
 670    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 671    assert(!intel->no_batch_wrap);
 672 }
 673
 674 static void
 675 i915_assert_not_dirty( struct intel_context *intel )
 676 {
 677    struct i915_context *i915 = i915_context(&intel->ctx);
 678    struct i915_hw_state *state = i915->current;
 679    GLuint dirty = get_dirty(state);
 680    assert(!dirty);
 681 }
 682
 683 void
 684 i915InitVtbl(struct i915_context *i915)
 685 {
 686    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 687    i915->intel.vtbl.destroy = i915_destroy_context;
 688    i915->intel.vtbl.emit_state = i915_emit_state;
 689    i915->intel.vtbl.new_batch = i915_new_batch;
 690    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 691    i915->intel.vtbl.render_start = i915_render_start;
 692    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 693    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 694    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 695    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 696    i915->intel.vtbl.finish_batch = intel_finish_vb;
 697 }