Merge branch 'gallium-edgeflags'
[mesa.git] / src / mesa / drivers / dri / i915 / i915_vtbl.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
35
36 #include "tnl/t_context.h"
37 #include "tnl/t_vertex.h"
38
39 #include "intel_batchbuffer.h"
40 #include "intel_tex.h"
41 #include "intel_regions.h"
42 #include "intel_tris.h"
43 #include "intel_fbo.h"
44 #include "intel_chipset.h"
45
46 #include "i915_reg.h"
47 #include "i915_context.h"
48
49 #include "glapi/glapi.h"
50
51 static void
52 i915_render_prevalidate(struct intel_context *intel)
53 {
54 struct i915_context *i915 = i915_context(&intel->ctx);
55
56 i915ValidateFragmentProgram(i915);
57 }
58
59 static void
60 i915_render_start(struct intel_context *intel)
61 {
62 }
63
64
65 static void
66 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
67 {
68 struct i915_context *i915 = i915_context(&intel->ctx);
69 GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
70
71 st1 &= ~ST1_ENABLE;
72
73 switch (rprim) {
74 case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
75 case GL_TRIANGLES:
76 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
77 st1 |= ST1_ENABLE;
78 break;
79 case GL_LINES:
80 case GL_POINTS:
81 default:
82 break;
83 }
84
85 i915->intel.reduced_primitive = rprim;
86
87 if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
88 INTEL_FIREVERTICES(intel);
89
90 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
91 i915->state.Stipple[I915_STPREG_ST1] = st1;
92 }
93 }
94
95
96 /* Pull apart the vertex format registers and figure out how large a
97 * vertex is supposed to be.
98 */
99 static GLboolean
100 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
101 {
102 struct i915_context *i915 = i915_context(&intel->ctx);
103 int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
104 int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
105 int i, sz = 0;
106
107 switch (lis4 & S4_VFMT_XYZW_MASK) {
108 case S4_VFMT_XY:
109 sz = 2;
110 break;
111 case S4_VFMT_XYZ:
112 sz = 3;
113 break;
114 case S4_VFMT_XYW:
115 sz = 3;
116 break;
117 case S4_VFMT_XYZW:
118 sz = 4;
119 break;
120 default:
121 fprintf(stderr, "no xyzw specified\n");
122 return 0;
123 }
124
125 if (lis4 & S4_VFMT_SPEC_FOG)
126 sz++;
127 if (lis4 & S4_VFMT_COLOR)
128 sz++;
129 if (lis4 & S4_VFMT_DEPTH_OFFSET)
130 sz++;
131 if (lis4 & S4_VFMT_POINT_WIDTH)
132 sz++;
133 if (lis4 & S4_VFMT_FOG_PARAM)
134 sz++;
135
136 for (i = 0; i < 8; i++) {
137 switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
138 case TEXCOORDFMT_2D:
139 sz += 2;
140 break;
141 case TEXCOORDFMT_3D:
142 sz += 3;
143 break;
144 case TEXCOORDFMT_4D:
145 sz += 4;
146 break;
147 case TEXCOORDFMT_1D:
148 sz += 1;
149 break;
150 case TEXCOORDFMT_2D_16:
151 sz += 1;
152 break;
153 case TEXCOORDFMT_4D_16:
154 sz += 2;
155 break;
156 case TEXCOORDFMT_NOT_PRESENT:
157 break;
158 default:
159 fprintf(stderr, "bad texcoord fmt %d\n", i);
160 return GL_FALSE;
161 }
162 lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
163 }
164
165 if (sz != expected)
166 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
167
168 return sz == expected;
169 }
170
171
172 static void
173 i915_emit_invarient_state(struct intel_context *intel)
174 {
175 BATCH_LOCALS;
176
177 BEGIN_BATCH(17, IGNORE_CLIPRECTS);
178
179 OUT_BATCH(_3DSTATE_AA_CMD |
180 AA_LINE_ECAAR_WIDTH_ENABLE |
181 AA_LINE_ECAAR_WIDTH_1_0 |
182 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
183
184 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
185 OUT_BATCH(0);
186
187 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
188 OUT_BATCH(0);
189
190 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
191 OUT_BATCH(0);
192
193 /* Don't support texture crossbar yet */
194 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
195 CSB_TCB(0, 0) |
196 CSB_TCB(1, 1) |
197 CSB_TCB(2, 2) |
198 CSB_TCB(3, 3) |
199 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
200
201 /* Need to initialize this to zero.
202 */
203 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
204 OUT_BATCH(0);
205
206 /* XXX: Use this */
207 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
208
209 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
210 OUT_BATCH(0);
211 OUT_BATCH(0);
212
213 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
214
215 OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
216 OUT_BATCH(0);
217
218 ADVANCE_BATCH();
219 }
220
221
222 #define emit(intel, state, size ) \
223 intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
224
225 static GLuint
226 get_dirty(struct i915_hw_state *state)
227 {
228 GLuint dirty;
229
230 /* Workaround the multitex hang - if one texture unit state is
231 * modified, emit all texture units.
232 */
233 dirty = state->active & ~state->emitted;
234 if (dirty & I915_UPLOAD_TEX_ALL)
235 state->emitted &= ~I915_UPLOAD_TEX_ALL;
236 dirty = state->active & ~state->emitted;
237 return dirty;
238 }
239
240
241 static GLuint
242 get_state_size(struct i915_hw_state *state)
243 {
244 GLuint dirty = get_dirty(state);
245 GLuint i;
246 GLuint sz = 0;
247
248 if (dirty & I915_UPLOAD_INVARIENT)
249 sz += 30 * 4;
250
251 if (dirty & I915_UPLOAD_RASTER_RULES)
252 sz += sizeof(state->RasterRules);
253
254 if (dirty & I915_UPLOAD_CTX)
255 sz += sizeof(state->Ctx);
256
257 if (dirty & I915_UPLOAD_BUFFERS)
258 sz += sizeof(state->Buffer);
259
260 if (dirty & I915_UPLOAD_STIPPLE)
261 sz += sizeof(state->Stipple);
262
263 if (dirty & I915_UPLOAD_FOG)
264 sz += sizeof(state->Fog);
265
266 if (dirty & I915_UPLOAD_TEX_ALL) {
267 int nr = 0;
268 for (i = 0; i < I915_TEX_UNITS; i++)
269 if (dirty & I915_UPLOAD_TEX(i))
270 nr++;
271
272 sz += (2 + nr * 3) * sizeof(GLuint) * 2;
273 }
274
275 if (dirty & I915_UPLOAD_CONSTANTS)
276 sz += state->ConstantSize * sizeof(GLuint);
277
278 if (dirty & I915_UPLOAD_PROGRAM)
279 sz += state->ProgramSize * sizeof(GLuint);
280
281 return sz;
282 }
283
284 /* Push the state into the sarea and/or texture memory.
285 */
286 static void
287 i915_emit_state(struct intel_context *intel)
288 {
289 struct i915_context *i915 = i915_context(&intel->ctx);
290 struct i915_hw_state *state = i915->current;
291 int i, count, aper_count;
292 GLuint dirty;
293 dri_bo *aper_array[3 + I915_TEX_UNITS];
294 GET_CURRENT_CONTEXT(ctx);
295 BATCH_LOCALS;
296
297 /* We don't hold the lock at this point, so want to make sure that
298 * there won't be a buffer wrap between the state emits and the primitive
299 * emit header.
300 *
301 * It might be better to talk about explicit places where
302 * scheduling is allowed, rather than assume that it is whenever a
303 * batchbuffer fills up.
304 *
305 * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
306 * will be emitted under.
307 */
308 intel_batchbuffer_require_space(intel->batch,
309 get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
310 LOOP_CLIPRECTS);
311 count = 0;
312 again:
313 aper_count = 0;
314 dirty = get_dirty(state);
315
316 aper_array[aper_count++] = intel->batch->buf;
317 if (dirty & I915_UPLOAD_BUFFERS) {
318 aper_array[aper_count++] = state->draw_region->buffer;
319 if (state->depth_region)
320 aper_array[aper_count++] = state->depth_region->buffer;
321 }
322
323 if (dirty & I915_UPLOAD_TEX_ALL) {
324 for (i = 0; i < I915_TEX_UNITS; i++) {
325 if (dirty & I915_UPLOAD_TEX(i)) {
326 if (state->tex_buffer[i]) {
327 aper_array[aper_count++] = state->tex_buffer[i];
328 }
329 }
330 }
331 }
332
333 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
334 if (count == 0) {
335 count++;
336 intel_batchbuffer_flush(intel->batch);
337 goto again;
338 } else {
339 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
340 assert(0);
341 }
342 }
343
344 /* work out list of buffers to emit */
345
346 /* Do this here as we may have flushed the batchbuffer above,
347 * causing more state to be dirty!
348 */
349 dirty = get_dirty(state);
350 state->emitted |= dirty;
351 assert(get_dirty(state) == 0);
352
353 if (INTEL_DEBUG & DEBUG_STATE)
354 fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
355
356 if (dirty & I915_UPLOAD_INVARIENT) {
357 if (INTEL_DEBUG & DEBUG_STATE)
358 fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
359 i915_emit_invarient_state(intel);
360 }
361
362 if (dirty & I915_UPLOAD_RASTER_RULES) {
363 if (INTEL_DEBUG & DEBUG_STATE)
364 fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
365 emit(intel, state->RasterRules, sizeof(state->RasterRules));
366 }
367
368 if (dirty & I915_UPLOAD_CTX) {
369 if (INTEL_DEBUG & DEBUG_STATE)
370 fprintf(stderr, "I915_UPLOAD_CTX:\n");
371
372 emit(intel, state->Ctx, sizeof(state->Ctx));
373 }
374
375 if (dirty & I915_UPLOAD_BUFFERS) {
376 GLuint count = 9;
377
378 if (INTEL_DEBUG & DEBUG_STATE)
379 fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
380
381 if (state->depth_region)
382 count += 3;
383
384 if (intel->constant_cliprect)
385 count += 6;
386
387 BEGIN_BATCH(count, IGNORE_CLIPRECTS);
388 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
389 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
390 OUT_RELOC(state->draw_region->buffer,
391 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
392 state->draw_region->draw_offset);
393
394 if (state->depth_region) {
395 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
396 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
397 OUT_RELOC(state->depth_region->buffer,
398 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
399 state->depth_region->draw_offset);
400 }
401
402 OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
403 OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
404 OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
405 OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
406 OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
407 OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
408
409 if (intel->constant_cliprect) {
410 assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
411 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
412 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
413 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
414 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
415 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
416 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
417 }
418
419 ADVANCE_BATCH();
420 }
421
422 if (dirty & I915_UPLOAD_STIPPLE) {
423 if (INTEL_DEBUG & DEBUG_STATE)
424 fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
425 emit(intel, state->Stipple, sizeof(state->Stipple));
426 }
427
428 if (dirty & I915_UPLOAD_FOG) {
429 if (INTEL_DEBUG & DEBUG_STATE)
430 fprintf(stderr, "I915_UPLOAD_FOG:\n");
431 emit(intel, state->Fog, sizeof(state->Fog));
432 }
433
434 /* Combine all the dirty texture state into a single command to
435 * avoid lockups on I915 hardware.
436 */
437 if (dirty & I915_UPLOAD_TEX_ALL) {
438 int nr = 0;
439
440 for (i = 0; i < I915_TEX_UNITS; i++)
441 if (dirty & I915_UPLOAD_TEX(i))
442 nr++;
443
444 BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
445 OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
446 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
447 for (i = 0; i < I915_TEX_UNITS; i++)
448 if (dirty & I915_UPLOAD_TEX(i)) {
449
450 if (state->tex_buffer[i]) {
451 OUT_RELOC(state->tex_buffer[i],
452 I915_GEM_DOMAIN_SAMPLER, 0,
453 state->tex_offset[i]);
454 }
455 else if (state == &i915->meta) {
456 assert(i == 0);
457 OUT_BATCH(0);
458 }
459 else {
460 OUT_BATCH(state->tex_offset[i]);
461 }
462
463 OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
464 OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
465 }
466 ADVANCE_BATCH();
467
468 BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
469 OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
470 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
471 for (i = 0; i < I915_TEX_UNITS; i++)
472 if (dirty & I915_UPLOAD_TEX(i)) {
473 OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
474 OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
475 OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
476 }
477 ADVANCE_BATCH();
478 }
479
480 if (dirty & I915_UPLOAD_CONSTANTS) {
481 if (INTEL_DEBUG & DEBUG_STATE)
482 fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
483 emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
484 }
485
486 if (dirty & I915_UPLOAD_PROGRAM) {
487 if (state->ProgramSize) {
488 if (INTEL_DEBUG & DEBUG_STATE)
489 fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
490
491 assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
492
493 emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
494 if (INTEL_DEBUG & DEBUG_STATE)
495 i915_disassemble_program(state->Program, state->ProgramSize);
496 }
497 }
498
499 intel->batch->dirty_state &= ~dirty;
500 assert(get_dirty(state) == 0);
501 assert((intel->batch->dirty_state & (1<<1)) == 0);
502 }
503
504 static void
505 i915_destroy_context(struct intel_context *intel)
506 {
507 GLuint i;
508 struct i915_context *i915 = i915_context(&intel->ctx);
509
510 intel_region_release(&i915->state.draw_region);
511 intel_region_release(&i915->state.depth_region);
512 intel_region_release(&i915->meta.draw_region);
513 intel_region_release(&i915->meta.depth_region);
514 intel_region_release(&i915->initial.draw_region);
515 intel_region_release(&i915->initial.depth_region);
516
517 for (i = 0; i < I915_TEX_UNITS; i++) {
518 if (i915->state.tex_buffer[i] != NULL) {
519 dri_bo_unreference(i915->state.tex_buffer[i]);
520 i915->state.tex_buffer[i] = NULL;
521 }
522 }
523
524 _tnl_free_vertices(&intel->ctx);
525 }
526
527 void
528 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
529 uint32_t buffer_id)
530 {
531 state[0] = _3DSTATE_BUF_INFO_CMD;
532 state[1] = buffer_id;
533
534 if (region != NULL) {
535 state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
536
537 if (region->tiling != I915_TILING_NONE) {
538 state[1] |= BUF_3D_TILED_SURFACE;
539 if (region->tiling == I915_TILING_Y)
540 state[1] |= BUF_3D_TILE_WALK_Y;
541 }
542 }
543 }
544
545 /**
546 * Set the drawing regions for the color and depth/stencil buffers.
547 * This involves setting the pitch, cpp and buffer ID/location.
548 * Also set pixel format for color and Z rendering
549 * Used for setting both regular and meta state.
550 */
551 void
552 i915_state_draw_region(struct intel_context *intel,
553 struct i915_hw_state *state,
554 struct intel_region *color_region,
555 struct intel_region *depth_region)
556 {
557 struct i915_context *i915 = i915_context(&intel->ctx);
558 GLcontext *ctx = &intel->ctx;
559 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
560 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
561 GLuint value;
562
563 ASSERT(state == &i915->state || state == &i915->meta);
564
565 if (state->draw_region != color_region) {
566 intel_region_release(&state->draw_region);
567 intel_region_reference(&state->draw_region, color_region);
568 }
569 if (state->depth_region != depth_region) {
570 intel_region_release(&state->depth_region);
571 intel_region_reference(&state->depth_region, depth_region);
572 }
573
574 /*
575 * Set stride/cpp values
576 */
577 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
578 color_region, BUF_3D_ID_COLOR_BACK);
579
580 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
581 depth_region, BUF_3D_ID_DEPTH);
582
583 /*
584 * Compute/set I915_DESTREG_DV1 value
585 */
586 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
587 DSTORG_VERT_BIAS(0x8) | /* .5 */
588 LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
589 if (irb != NULL) {
590 switch (irb->Base.Format) {
591 case MESA_FORMAT_ARGB8888:
592 case MESA_FORMAT_XRGB8888:
593 value |= DV_PF_8888;
594 break;
595 case MESA_FORMAT_RGB565:
596 value |= DV_PF_565 | DITHER_FULL_ALWAYS;
597 break;
598 case MESA_FORMAT_ARGB1555:
599 value |= DV_PF_1555 | DITHER_FULL_ALWAYS;
600 break;
601 case MESA_FORMAT_ARGB4444:
602 value |= DV_PF_4444 | DITHER_FULL_ALWAYS;
603 break;
604 default:
605 _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
606 irb->Base.Format);
607 }
608 }
609
610 /* This isn't quite safe, thus being hidden behind an option. When changing
611 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
612 * can only be set when a depth buffer is already defined.
613 */
614 if (IS_945(intel->intelScreen->deviceID) && intel->use_early_z &&
615 depth_region->tiling != I915_TILING_NONE)
616 value |= CLASSIC_EARLY_DEPTH;
617
618 if (depth_region && depth_region->cpp == 4) {
619 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
620 }
621 else {
622 value |= DEPTH_FRMT_16_FIXED;
623 }
624 state->Buffer[I915_DESTREG_DV1] = value;
625
626 if (intel->constant_cliprect) {
627 state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
628 state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
629 state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
630 state->Buffer[I915_DESTREG_DRAWRECT3] =
631 (ctx->DrawBuffer->Width & 0xffff) |
632 (ctx->DrawBuffer->Height << 16);
633 state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
634 state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
635 } else {
636 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
637 state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP;
638 state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP;
639 state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP;
640 state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP;
641 state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP;
642 }
643
644 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
645 }
646
647
648 static void
649 i915_set_draw_region(struct intel_context *intel,
650 struct intel_region *color_regions[],
651 struct intel_region *depth_region,
652 GLuint num_regions)
653 {
654 struct i915_context *i915 = i915_context(&intel->ctx);
655 i915_state_draw_region(intel, &i915->state, color_regions[0], depth_region);
656 }
657
658
659
660 static void
661 i915_new_batch(struct intel_context *intel)
662 {
663 struct i915_context *i915 = i915_context(&intel->ctx);
664
665 /* Mark all state as needing to be emitted when starting a new batchbuffer.
666 * Using hardware contexts would be an alternative, but they have some
667 * difficulties associated with them (physical address requirements).
668 */
669 i915->state.emitted = 0;
670 }
671
672 static void
673 i915_assert_not_dirty( struct intel_context *intel )
674 {
675 struct i915_context *i915 = i915_context(&intel->ctx);
676 struct i915_hw_state *state = i915->current;
677 GLuint dirty = get_dirty(state);
678 assert(!dirty);
679 }
680
681 void
682 i915InitVtbl(struct i915_context *i915)
683 {
684 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
685 i915->intel.vtbl.destroy = i915_destroy_context;
686 i915->intel.vtbl.emit_state = i915_emit_state;
687 i915->intel.vtbl.new_batch = i915_new_batch;
688 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
689 i915->intel.vtbl.render_start = i915_render_start;
690 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
691 i915->intel.vtbl.set_draw_region = i915_set_draw_region;
692 i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
693 i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
694 i915->intel.vtbl.finish_batch = intel_finish_vb;
695 }