1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
36 #include "tnl/t_context.h"
37 #include "tnl/t_vertex.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_regions.h"
41 #include "intel_tris.h"
42 #include "intel_fbo.h"
45 #include "i915_context.h"
48 i915_render_prevalidate(struct intel_context
*intel
)
50 struct i915_context
*i915
= i915_context(&intel
->ctx
);
52 i915ValidateFragmentProgram(i915
);
56 i915_render_start(struct intel_context
*intel
)
58 intel_prepare_render(intel
);
63 i915_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
65 struct i915_context
*i915
= i915_context(&intel
->ctx
);
66 GLuint st1
= i915
->state
.Stipple
[I915_STPREG_ST1
];
71 case GL_QUADS
: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
73 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
82 i915
->intel
.reduced_primitive
= rprim
;
84 if (st1
!= i915
->state
.Stipple
[I915_STPREG_ST1
]) {
85 INTEL_FIREVERTICES(intel
);
87 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
88 i915
->state
.Stipple
[I915_STPREG_ST1
] = st1
;
93 /* Pull apart the vertex format registers and figure out how large a
94 * vertex is supposed to be.
97 i915_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
99 struct i915_context
*i915
= i915_context(&intel
->ctx
);
100 int lis2
= i915
->state
.Ctx
[I915_CTXREG_LIS2
];
101 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
104 switch (lis4
& S4_VFMT_XYZW_MASK
) {
118 fprintf(stderr
, "no xyzw specified\n");
122 if (lis4
& S4_VFMT_SPEC_FOG
)
124 if (lis4
& S4_VFMT_COLOR
)
126 if (lis4
& S4_VFMT_DEPTH_OFFSET
)
128 if (lis4
& S4_VFMT_POINT_WIDTH
)
130 if (lis4
& S4_VFMT_FOG_PARAM
)
133 for (i
= 0; i
< 8; i
++) {
134 switch (lis2
& S2_TEXCOORD_FMT0_MASK
) {
147 case TEXCOORDFMT_2D_16
:
150 case TEXCOORDFMT_4D_16
:
153 case TEXCOORDFMT_NOT_PRESENT
:
156 fprintf(stderr
, "bad texcoord fmt %d\n", i
);
159 lis2
>>= S2_TEXCOORD_FMT1_SHIFT
;
163 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
165 return sz
== expected
;
170 i915_emit_invarient_state(struct intel_context
*intel
)
176 OUT_BATCH(_3DSTATE_AA_CMD
|
177 AA_LINE_ECAAR_WIDTH_ENABLE
|
178 AA_LINE_ECAAR_WIDTH_1_0
|
179 AA_LINE_REGION_WIDTH_ENABLE
| AA_LINE_REGION_WIDTH_1_0
);
181 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
184 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
187 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
190 /* Don't support texture crossbar yet */
191 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS
|
196 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
198 /* Need to initialize this to zero.
200 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1
| I1_LOAD_S(3) | (0));
204 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
206 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD
);
210 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE
);
212 OUT_BATCH(_3DSTATE_LOAD_INDIRECT
| 0); /* disable indirect state */
219 #define emit(intel, state, size ) \
220 intel_batchbuffer_data(intel, state, size, false)
223 get_dirty(struct i915_hw_state
*state
)
227 /* Workaround the multitex hang - if one texture unit state is
228 * modified, emit all texture units.
230 dirty
= state
->active
& ~state
->emitted
;
231 if (dirty
& I915_UPLOAD_TEX_ALL
)
232 state
->emitted
&= ~I915_UPLOAD_TEX_ALL
;
233 dirty
= state
->active
& ~state
->emitted
;
239 get_state_size(struct i915_hw_state
*state
)
241 GLuint dirty
= get_dirty(state
);
245 if (dirty
& I915_UPLOAD_INVARIENT
)
248 if (dirty
& I915_UPLOAD_RASTER_RULES
)
249 sz
+= sizeof(state
->RasterRules
);
251 if (dirty
& I915_UPLOAD_CTX
)
252 sz
+= sizeof(state
->Ctx
);
254 if (dirty
& I915_UPLOAD_BLEND
)
255 sz
+= sizeof(state
->Blend
);
257 if (dirty
& I915_UPLOAD_BUFFERS
)
258 sz
+= sizeof(state
->Buffer
);
260 if (dirty
& I915_UPLOAD_STIPPLE
)
261 sz
+= sizeof(state
->Stipple
);
263 if (dirty
& I915_UPLOAD_FOG
)
264 sz
+= sizeof(state
->Fog
);
266 if (dirty
& I915_UPLOAD_TEX_ALL
) {
268 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
269 if (dirty
& I915_UPLOAD_TEX(i
))
272 sz
+= (2 + nr
* 3) * sizeof(GLuint
) * 2;
275 if (dirty
& I915_UPLOAD_CONSTANTS
)
276 sz
+= state
->ConstantSize
* sizeof(GLuint
);
278 if (dirty
& I915_UPLOAD_PROGRAM
)
279 sz
+= state
->ProgramSize
* sizeof(GLuint
);
284 /* Push the state into the sarea and/or texture memory.
287 i915_emit_state(struct intel_context
*intel
)
289 struct i915_context
*i915
= i915_context(&intel
->ctx
);
290 struct i915_hw_state
*state
= &i915
->state
;
291 int i
, count
, aper_count
;
293 drm_intel_bo
*aper_array
[3 + I915_TEX_UNITS
];
294 GET_CURRENT_CONTEXT(ctx
);
297 /* We don't hold the lock at this point, so want to make sure that
298 * there won't be a buffer wrap between the state emits and the primitive
301 * It might be better to talk about explicit places where
302 * scheduling is allowed, rather than assume that it is whenever a
303 * batchbuffer fills up.
305 intel_batchbuffer_require_space(intel
,
306 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
311 dirty
= get_dirty(state
);
313 aper_array
[aper_count
++] = intel
->batch
.bo
;
314 if (dirty
& I915_UPLOAD_BUFFERS
) {
315 aper_array
[aper_count
++] = state
->draw_region
->buffer
;
316 if (state
->depth_region
)
317 aper_array
[aper_count
++] = state
->depth_region
->buffer
;
320 if (dirty
& I915_UPLOAD_TEX_ALL
) {
321 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
322 if (dirty
& I915_UPLOAD_TEX(i
)) {
323 if (state
->tex_buffer
[i
]) {
324 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
330 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
333 intel_batchbuffer_flush(intel
);
336 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i915 emit state");
341 /* work out list of buffers to emit */
343 /* Do this here as we may have flushed the batchbuffer above,
344 * causing more state to be dirty!
346 dirty
= get_dirty(state
);
347 state
->emitted
|= dirty
;
348 assert(get_dirty(state
) == 0);
350 if (INTEL_DEBUG
& DEBUG_STATE
)
351 fprintf(stderr
, "%s dirty: %x\n", __FUNCTION__
, dirty
);
353 if (dirty
& I915_UPLOAD_INVARIENT
) {
354 if (INTEL_DEBUG
& DEBUG_STATE
)
355 fprintf(stderr
, "I915_UPLOAD_INVARIENT:\n");
356 i915_emit_invarient_state(intel
);
359 if (dirty
& I915_UPLOAD_RASTER_RULES
) {
360 if (INTEL_DEBUG
& DEBUG_STATE
)
361 fprintf(stderr
, "I915_UPLOAD_RASTER_RULES:\n");
362 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
365 if (dirty
& I915_UPLOAD_CTX
) {
366 if (INTEL_DEBUG
& DEBUG_STATE
)
367 fprintf(stderr
, "I915_UPLOAD_CTX:\n");
369 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
372 if (dirty
& I915_UPLOAD_BLEND
) {
373 if (INTEL_DEBUG
& DEBUG_STATE
)
374 fprintf(stderr
, "I915_UPLOAD_BLEND:\n");
376 emit(intel
, state
->Blend
, sizeof(state
->Blend
));
379 if (dirty
& I915_UPLOAD_BUFFERS
) {
382 if (INTEL_DEBUG
& DEBUG_STATE
)
383 fprintf(stderr
, "I915_UPLOAD_BUFFERS:\n");
386 if (state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
)
388 if (state
->depth_region
)
392 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR0
]);
393 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR1
]);
394 OUT_RELOC(state
->draw_region
->buffer
,
395 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
397 if (state
->depth_region
) {
398 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR0
]);
399 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR1
]);
400 OUT_RELOC(state
->depth_region
->buffer
,
401 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
404 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV0
]);
405 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV1
]);
406 OUT_BATCH(state
->Buffer
[I915_DESTREG_SENABLE
]);
407 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR0
]);
408 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR1
]);
409 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR2
]);
411 if (state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
)
412 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT0
]);
413 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT1
]);
414 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT2
]);
415 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT3
]);
416 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT4
]);
417 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT5
]);
422 if (dirty
& I915_UPLOAD_STIPPLE
) {
423 if (INTEL_DEBUG
& DEBUG_STATE
)
424 fprintf(stderr
, "I915_UPLOAD_STIPPLE:\n");
425 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
428 if (dirty
& I915_UPLOAD_FOG
) {
429 if (INTEL_DEBUG
& DEBUG_STATE
)
430 fprintf(stderr
, "I915_UPLOAD_FOG:\n");
431 emit(intel
, state
->Fog
, sizeof(state
->Fog
));
434 /* Combine all the dirty texture state into a single command to
435 * avoid lockups on I915 hardware.
437 if (dirty
& I915_UPLOAD_TEX_ALL
) {
441 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
442 if (dirty
& I915_UPLOAD_TEX(i
))
445 BEGIN_BATCH(2 + nr
* 3);
446 OUT_BATCH(_3DSTATE_MAP_STATE
| (3 * nr
));
447 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
448 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
449 if (dirty
& I915_UPLOAD_TEX(i
)) {
450 OUT_RELOC(state
->tex_buffer
[i
],
451 I915_GEM_DOMAIN_SAMPLER
, 0,
452 state
->tex_offset
[i
]);
454 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS3
]);
455 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS4
]);
459 unwind
= intel
->batch
.used
;
460 BEGIN_BATCH(2 + nr
* 3);
461 OUT_BATCH(_3DSTATE_SAMPLER_STATE
| (3 * nr
));
462 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
463 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
464 if (dirty
& I915_UPLOAD_TEX(i
)) {
465 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS2
]);
466 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS3
]);
467 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS4
]);
470 if (i915
->last_sampler
&&
471 memcmp(intel
->batch
.map
+ i915
->last_sampler
,
472 intel
->batch
.map
+ unwind
,
473 (2 + nr
*3)*sizeof(int)) == 0)
474 intel
->batch
.used
= unwind
;
476 i915
->last_sampler
= unwind
;
479 if (dirty
& I915_UPLOAD_CONSTANTS
) {
480 if (INTEL_DEBUG
& DEBUG_STATE
)
481 fprintf(stderr
, "I915_UPLOAD_CONSTANTS:\n");
482 emit(intel
, state
->Constant
, state
->ConstantSize
* sizeof(GLuint
));
485 if (dirty
& I915_UPLOAD_PROGRAM
) {
486 if (state
->ProgramSize
) {
487 if (INTEL_DEBUG
& DEBUG_STATE
)
488 fprintf(stderr
, "I915_UPLOAD_PROGRAM:\n");
490 assert((state
->Program
[0] & 0x1ff) + 2 == state
->ProgramSize
);
492 emit(intel
, state
->Program
, state
->ProgramSize
* sizeof(GLuint
));
493 if (INTEL_DEBUG
& DEBUG_STATE
)
494 i915_disassemble_program(state
->Program
, state
->ProgramSize
);
498 assert(get_dirty(state
) == 0);
502 i915_destroy_context(struct intel_context
*intel
)
505 struct i915_context
*i915
= i915_context(&intel
->ctx
);
507 intel_region_release(&i915
->state
.draw_region
);
508 intel_region_release(&i915
->state
.depth_region
);
510 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
511 if (i915
->state
.tex_buffer
[i
] != NULL
) {
512 drm_intel_bo_unreference(i915
->state
.tex_buffer
[i
]);
513 i915
->state
.tex_buffer
[i
] = NULL
;
517 _tnl_free_vertices(&intel
->ctx
);
521 i915_set_buf_info_for_region(uint32_t *state
, struct intel_region
*region
,
524 state
[0] = _3DSTATE_BUF_INFO_CMD
;
525 state
[1] = buffer_id
;
527 if (region
!= NULL
) {
528 state
[1] |= BUF_3D_PITCH(region
->pitch
* region
->cpp
);
530 if (region
->tiling
!= I915_TILING_NONE
) {
531 state
[1] |= BUF_3D_TILED_SURFACE
;
532 if (region
->tiling
== I915_TILING_Y
)
533 state
[1] |= BUF_3D_TILE_WALK_Y
;
538 static uint32_t i915_render_target_format_for_mesa_format
[MESA_FORMAT_COUNT
] =
540 [MESA_FORMAT_ARGB8888
] = DV_PF_8888
,
541 [MESA_FORMAT_XRGB8888
] = DV_PF_8888
,
542 [MESA_FORMAT_RGB565
] = DV_PF_565
| DITHER_FULL_ALWAYS
,
543 [MESA_FORMAT_ARGB1555
] = DV_PF_1555
| DITHER_FULL_ALWAYS
,
544 [MESA_FORMAT_ARGB4444
] = DV_PF_4444
| DITHER_FULL_ALWAYS
,
548 i915_render_target_supported(gl_format format
)
550 if (format
== MESA_FORMAT_S8_Z24
||
551 format
== MESA_FORMAT_X8_Z24
||
552 format
== MESA_FORMAT_Z16
) {
556 return i915_render_target_format_for_mesa_format
[format
] != 0;
560 i915_set_draw_region(struct intel_context
*intel
,
561 struct intel_region
*color_regions
[],
562 struct intel_region
*depth_region
,
565 struct i915_context
*i915
= i915_context(&intel
->ctx
);
566 struct gl_context
*ctx
= &intel
->ctx
;
567 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
568 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
570 struct i915_hw_state
*state
= &i915
->state
;
571 uint32_t draw_x
, draw_y
, draw_offset
;
573 if (state
->draw_region
!= color_regions
[0]) {
574 intel_region_release(&state
->draw_region
);
575 intel_region_reference(&state
->draw_region
, color_regions
[0]);
577 if (state
->depth_region
!= depth_region
) {
578 intel_region_release(&state
->depth_region
);
579 intel_region_reference(&state
->depth_region
, depth_region
);
583 * Set stride/cpp values
585 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_CBUFADDR0
],
586 color_regions
[0], BUF_3D_ID_COLOR_BACK
);
588 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_DBUFADDR0
],
589 depth_region
, BUF_3D_ID_DEPTH
);
592 * Compute/set I915_DESTREG_DV1 value
594 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
595 DSTORG_VERT_BIAS(0x8) | /* .5 */
596 LOD_PRECLAMP_OGL
| TEX_DEFAULT_COLOR_OGL
);
598 value
|= i915_render_target_format_for_mesa_format
[irb
->Base
.Format
];
601 /* This isn't quite safe, thus being hidden behind an option. When changing
602 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
603 * can only be set when a depth buffer is already defined.
605 if (intel
->is_945
&& intel
->use_early_z
&&
606 depth_region
->tiling
!= I915_TILING_NONE
)
607 value
|= CLASSIC_EARLY_DEPTH
;
609 if (depth_region
&& depth_region
->cpp
== 4) {
610 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
613 value
|= DEPTH_FRMT_16_FIXED
;
615 state
->Buffer
[I915_DESTREG_DV1
] = value
;
617 /* We set up the drawing rectangle to be offset into the color
618 * region's location in the miptree. If it doesn't match with
619 * depth's offsets, we can't render to it.
621 * (Well, not actually true -- the hw grew a bit to let depth's
622 * offset get forced to 0,0. We may want to use that if people are
623 * hitting that case. Also, some configurations may be supportable
624 * by tweaking the start offset of the buffers around, which we
625 * can't do in general due to tiling)
627 FALLBACK(intel
, I915_FALLBACK_DRAW_OFFSET
,
628 (depth_region
&& color_regions
[0]) &&
629 (depth_region
->draw_x
!= color_regions
[0]->draw_x
||
630 depth_region
->draw_y
!= color_regions
[0]->draw_y
));
632 if (color_regions
[0]) {
633 draw_x
= color_regions
[0]->draw_x
;
634 draw_y
= color_regions
[0]->draw_y
;
635 } else if (depth_region
) {
636 draw_x
= depth_region
->draw_x
;
637 draw_y
= depth_region
->draw_y
;
643 draw_offset
= (draw_y
<< 16) | draw_x
;
645 /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
646 if (draw_offset
!= i915
->last_draw_offset
) {
647 FALLBACK(intel
, I915_FALLBACK_DRAW_OFFSET
,
648 (ctx
->DrawBuffer
->Width
+ draw_x
> 2048) ||
649 (ctx
->DrawBuffer
->Height
+ draw_y
> 2048));
651 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_FLUSH
| INHIBIT_FLUSH_RENDER_CACHE
;
652 i915
->last_draw_offset
= draw_offset
;
654 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_NOOP
;
656 state
->Buffer
[I915_DESTREG_DRAWRECT1
] = _3DSTATE_DRAWRECT_INFO
;
657 state
->Buffer
[I915_DESTREG_DRAWRECT2
] = 0;
658 state
->Buffer
[I915_DESTREG_DRAWRECT3
] = draw_offset
;
659 state
->Buffer
[I915_DESTREG_DRAWRECT4
] =
660 ((ctx
->DrawBuffer
->Width
+ draw_x
- 1) & 0xffff) |
661 ((ctx
->DrawBuffer
->Height
+ draw_y
- 1) << 16);
662 state
->Buffer
[I915_DESTREG_DRAWRECT5
] = draw_offset
;
664 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
670 i915_new_batch(struct intel_context
*intel
)
672 struct i915_context
*i915
= i915_context(&intel
->ctx
);
674 /* Mark all state as needing to be emitted when starting a new batchbuffer.
675 * Using hardware contexts would be an alternative, but they have some
676 * difficulties associated with them (physical address requirements).
678 i915
->state
.emitted
= 0;
679 i915
->last_draw_offset
= 0;
680 i915
->last_sampler
= 0;
682 i915
->current_vb_bo
= NULL
;
683 i915
->current_vertex_size
= 0;
687 i915_assert_not_dirty( struct intel_context
*intel
)
689 struct i915_context
*i915
= i915_context(&intel
->ctx
);
690 GLuint dirty
= get_dirty(&i915
->state
);
696 i915InitVtbl(struct i915_context
*i915
)
698 i915
->intel
.vtbl
.check_vertex_size
= i915_check_vertex_size
;
699 i915
->intel
.vtbl
.destroy
= i915_destroy_context
;
700 i915
->intel
.vtbl
.emit_state
= i915_emit_state
;
701 i915
->intel
.vtbl
.new_batch
= i915_new_batch
;
702 i915
->intel
.vtbl
.reduced_primitive_state
= i915_reduced_primitive_state
;
703 i915
->intel
.vtbl
.render_start
= i915_render_start
;
704 i915
->intel
.vtbl
.render_prevalidate
= i915_render_prevalidate
;
705 i915
->intel
.vtbl
.set_draw_region
= i915_set_draw_region
;
706 i915
->intel
.vtbl
.update_texture_state
= i915UpdateTextureState
;
707 i915
->intel
.vtbl
.assert_not_dirty
= i915_assert_not_dirty
;
708 i915
->intel
.vtbl
.finish_batch
= intel_finish_vb
;
709 i915
->intel
.vtbl
.render_target_supported
= i915_render_target_supported
;