1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
37 #include "tnl/t_context.h"
38 #include "tnl/t_vertex.h"
39 #include "swrast_setup/swrast_setup.h"
41 #include "intel_batchbuffer.h"
42 #include "intel_regions.h"
43 #include "intel_tris.h"
44 #include "intel_fbo.h"
47 #include "i915_context.h"
50 i915_render_prevalidate(struct intel_context
*intel
)
52 struct i915_context
*i915
= i915_context(&intel
->ctx
);
54 i915ValidateFragmentProgram(i915
);
58 i915_render_start(struct intel_context
*intel
)
60 intel_prepare_render(intel
);
65 i915_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
67 struct i915_context
*i915
= i915_context(&intel
->ctx
);
68 GLuint st1
= i915
->state
.Stipple
[I915_STPREG_ST1
];
73 case GL_QUADS
: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
75 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
84 i915
->intel
.reduced_primitive
= rprim
;
86 if (st1
!= i915
->state
.Stipple
[I915_STPREG_ST1
]) {
87 INTEL_FIREVERTICES(intel
);
89 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
90 i915
->state
.Stipple
[I915_STPREG_ST1
] = st1
;
95 /* Pull apart the vertex format registers and figure out how large a
96 * vertex is supposed to be.
99 i915_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
101 struct i915_context
*i915
= i915_context(&intel
->ctx
);
102 int lis2
= i915
->state
.Ctx
[I915_CTXREG_LIS2
];
103 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
106 switch (lis4
& S4_VFMT_XYZW_MASK
) {
120 fprintf(stderr
, "no xyzw specified\n");
124 if (lis4
& S4_VFMT_SPEC_FOG
)
126 if (lis4
& S4_VFMT_COLOR
)
128 if (lis4
& S4_VFMT_DEPTH_OFFSET
)
130 if (lis4
& S4_VFMT_POINT_WIDTH
)
132 if (lis4
& S4_VFMT_FOG_PARAM
)
135 for (i
= 0; i
< 8; i
++) {
136 switch (lis2
& S2_TEXCOORD_FMT0_MASK
) {
149 case TEXCOORDFMT_2D_16
:
152 case TEXCOORDFMT_4D_16
:
155 case TEXCOORDFMT_NOT_PRESENT
:
158 fprintf(stderr
, "bad texcoord fmt %d\n", i
);
161 lis2
>>= S2_TEXCOORD_FMT1_SHIFT
;
165 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
167 return sz
== expected
;
172 i915_emit_invarient_state(struct intel_context
*intel
)
178 OUT_BATCH(_3DSTATE_AA_CMD
|
179 AA_LINE_ECAAR_WIDTH_ENABLE
|
180 AA_LINE_ECAAR_WIDTH_1_0
|
181 AA_LINE_REGION_WIDTH_ENABLE
| AA_LINE_REGION_WIDTH_1_0
);
183 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
186 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
189 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
192 /* Don't support texture crossbar yet */
193 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS
|
198 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
200 /* Need to initialize this to zero.
202 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1
| I1_LOAD_S(3) | (0));
206 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
208 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD
);
212 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE
);
214 OUT_BATCH(_3DSTATE_LOAD_INDIRECT
| 0); /* disable indirect state */
221 #define emit(intel, state, size ) \
222 intel_batchbuffer_data(intel, state, size, false)
225 get_dirty(struct i915_hw_state
*state
)
229 /* Workaround the multitex hang - if one texture unit state is
230 * modified, emit all texture units.
232 dirty
= state
->active
& ~state
->emitted
;
233 if (dirty
& I915_UPLOAD_TEX_ALL
)
234 state
->emitted
&= ~I915_UPLOAD_TEX_ALL
;
235 dirty
= state
->active
& ~state
->emitted
;
241 get_state_size(struct i915_hw_state
*state
)
243 GLuint dirty
= get_dirty(state
);
247 if (dirty
& I915_UPLOAD_INVARIENT
)
250 if (dirty
& I915_UPLOAD_RASTER_RULES
)
251 sz
+= sizeof(state
->RasterRules
);
253 if (dirty
& I915_UPLOAD_CTX
)
254 sz
+= sizeof(state
->Ctx
);
256 if (dirty
& I915_UPLOAD_BLEND
)
257 sz
+= sizeof(state
->Blend
);
259 if (dirty
& I915_UPLOAD_BUFFERS
)
260 sz
+= sizeof(state
->Buffer
);
262 if (dirty
& I915_UPLOAD_STIPPLE
)
263 sz
+= sizeof(state
->Stipple
);
265 if (dirty
& I915_UPLOAD_TEX_ALL
) {
267 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
268 if (dirty
& I915_UPLOAD_TEX(i
))
271 sz
+= (2 + nr
* 3) * sizeof(GLuint
) * 2;
274 if (dirty
& I915_UPLOAD_CONSTANTS
)
275 sz
+= state
->ConstantSize
* sizeof(GLuint
);
277 if (dirty
& I915_UPLOAD_PROGRAM
)
278 sz
+= state
->ProgramSize
* sizeof(GLuint
);
283 /* Push the state into the sarea and/or texture memory.
286 i915_emit_state(struct intel_context
*intel
)
288 struct i915_context
*i915
= i915_context(&intel
->ctx
);
289 struct i915_hw_state
*state
= &i915
->state
;
290 int i
, count
, aper_count
;
292 drm_intel_bo
*aper_array
[3 + I915_TEX_UNITS
];
293 GET_CURRENT_CONTEXT(ctx
);
296 /* We don't hold the lock at this point, so want to make sure that
297 * there won't be a buffer wrap between the state emits and the primitive
300 * It might be better to talk about explicit places where
301 * scheduling is allowed, rather than assume that it is whenever a
302 * batchbuffer fills up.
304 intel_batchbuffer_require_space(intel
,
305 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
309 if (intel
->batch
.bo
== NULL
) {
310 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i915 emit state");
314 dirty
= get_dirty(state
);
316 aper_array
[aper_count
++] = intel
->batch
.bo
;
317 if (dirty
& I915_UPLOAD_BUFFERS
) {
318 aper_array
[aper_count
++] = state
->draw_region
->buffer
;
319 if (state
->depth_region
)
320 aper_array
[aper_count
++] = state
->depth_region
->buffer
;
323 if (dirty
& I915_UPLOAD_TEX_ALL
) {
324 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
325 if (dirty
& I915_UPLOAD_TEX(i
)) {
326 if (state
->tex_buffer
[i
]) {
327 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
333 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
336 intel_batchbuffer_flush(intel
);
339 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i915 emit state");
344 /* work out list of buffers to emit */
346 /* Do this here as we may have flushed the batchbuffer above,
347 * causing more state to be dirty!
349 dirty
= get_dirty(state
);
350 state
->emitted
|= dirty
;
351 assert(get_dirty(state
) == 0);
353 if (INTEL_DEBUG
& DEBUG_STATE
)
354 fprintf(stderr
, "%s dirty: %x\n", __FUNCTION__
, dirty
);
356 if (dirty
& I915_UPLOAD_INVARIENT
) {
357 if (INTEL_DEBUG
& DEBUG_STATE
)
358 fprintf(stderr
, "I915_UPLOAD_INVARIENT:\n");
359 i915_emit_invarient_state(intel
);
362 if (dirty
& I915_UPLOAD_RASTER_RULES
) {
363 if (INTEL_DEBUG
& DEBUG_STATE
)
364 fprintf(stderr
, "I915_UPLOAD_RASTER_RULES:\n");
365 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
368 if (dirty
& I915_UPLOAD_CTX
) {
369 if (INTEL_DEBUG
& DEBUG_STATE
)
370 fprintf(stderr
, "I915_UPLOAD_CTX:\n");
372 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
375 if (dirty
& I915_UPLOAD_BLEND
) {
376 if (INTEL_DEBUG
& DEBUG_STATE
)
377 fprintf(stderr
, "I915_UPLOAD_BLEND:\n");
379 emit(intel
, state
->Blend
, sizeof(state
->Blend
));
382 if (dirty
& I915_UPLOAD_BUFFERS
) {
385 if (INTEL_DEBUG
& DEBUG_STATE
)
386 fprintf(stderr
, "I915_UPLOAD_BUFFERS:\n");
389 if (state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
)
391 if (state
->depth_region
)
395 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR0
]);
396 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR1
]);
397 OUT_RELOC(state
->draw_region
->buffer
,
398 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
400 if (state
->depth_region
) {
401 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR0
]);
402 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR1
]);
403 OUT_RELOC(state
->depth_region
->buffer
,
404 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
407 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV0
]);
408 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV1
]);
409 OUT_BATCH(state
->Buffer
[I915_DESTREG_SENABLE
]);
410 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR0
]);
411 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR1
]);
412 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR2
]);
414 if (state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
)
415 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT0
]);
416 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT1
]);
417 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT2
]);
418 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT3
]);
419 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT4
]);
420 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT5
]);
425 if (dirty
& I915_UPLOAD_STIPPLE
) {
426 if (INTEL_DEBUG
& DEBUG_STATE
)
427 fprintf(stderr
, "I915_UPLOAD_STIPPLE:\n");
428 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
431 /* Combine all the dirty texture state into a single command to
432 * avoid lockups on I915 hardware.
434 if (dirty
& I915_UPLOAD_TEX_ALL
) {
438 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
439 if (dirty
& I915_UPLOAD_TEX(i
))
442 BEGIN_BATCH(2 + nr
* 3);
443 OUT_BATCH(_3DSTATE_MAP_STATE
| (3 * nr
));
444 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
445 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
446 if (dirty
& I915_UPLOAD_TEX(i
)) {
447 OUT_RELOC(state
->tex_buffer
[i
],
448 I915_GEM_DOMAIN_SAMPLER
, 0,
449 state
->tex_offset
[i
]);
451 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS3
]);
452 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS4
]);
456 unwind
= intel
->batch
.used
;
457 BEGIN_BATCH(2 + nr
* 3);
458 OUT_BATCH(_3DSTATE_SAMPLER_STATE
| (3 * nr
));
459 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
460 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
461 if (dirty
& I915_UPLOAD_TEX(i
)) {
462 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS2
]);
463 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS3
]);
464 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS4
]);
467 if (i915
->last_sampler
&&
468 memcmp(intel
->batch
.map
+ i915
->last_sampler
,
469 intel
->batch
.map
+ unwind
,
470 (2 + nr
*3)*sizeof(int)) == 0)
471 intel
->batch
.used
= unwind
;
473 i915
->last_sampler
= unwind
;
476 if (dirty
& I915_UPLOAD_CONSTANTS
) {
477 if (INTEL_DEBUG
& DEBUG_STATE
)
478 fprintf(stderr
, "I915_UPLOAD_CONSTANTS:\n");
479 emit(intel
, state
->Constant
, state
->ConstantSize
* sizeof(GLuint
));
482 if (dirty
& I915_UPLOAD_PROGRAM
) {
483 if (state
->ProgramSize
) {
484 if (INTEL_DEBUG
& DEBUG_STATE
)
485 fprintf(stderr
, "I915_UPLOAD_PROGRAM:\n");
487 assert((state
->Program
[0] & 0x1ff) + 2 == state
->ProgramSize
);
489 emit(intel
, state
->Program
, state
->ProgramSize
* sizeof(GLuint
));
490 if (INTEL_DEBUG
& DEBUG_STATE
)
491 i915_disassemble_program(state
->Program
, state
->ProgramSize
);
495 assert(get_dirty(state
) == 0);
499 i915_destroy_context(struct intel_context
*intel
)
502 struct i915_context
*i915
= i915_context(&intel
->ctx
);
504 intel_region_release(&i915
->state
.draw_region
);
505 intel_region_release(&i915
->state
.depth_region
);
507 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
508 if (i915
->state
.tex_buffer
[i
] != NULL
) {
509 drm_intel_bo_unreference(i915
->state
.tex_buffer
[i
]);
510 i915
->state
.tex_buffer
[i
] = NULL
;
514 _tnl_free_vertices(&intel
->ctx
);
518 i915_set_buf_info_for_region(uint32_t *state
, struct intel_region
*region
,
521 state
[0] = _3DSTATE_BUF_INFO_CMD
;
522 state
[1] = buffer_id
;
524 if (region
!= NULL
) {
525 state
[1] |= BUF_3D_PITCH(region
->pitch
* region
->cpp
);
527 if (region
->tiling
!= I915_TILING_NONE
) {
528 state
[1] |= BUF_3D_TILED_SURFACE
;
529 if (region
->tiling
== I915_TILING_Y
)
530 state
[1] |= BUF_3D_TILE_WALK_Y
;
535 static uint32_t i915_render_target_format_for_mesa_format
[MESA_FORMAT_COUNT
] =
537 [MESA_FORMAT_ARGB8888
] = DV_PF_8888
,
538 [MESA_FORMAT_XRGB8888
] = DV_PF_8888
,
539 [MESA_FORMAT_RGB565
] = DV_PF_565
| DITHER_FULL_ALWAYS
,
540 [MESA_FORMAT_ARGB1555
] = DV_PF_1555
| DITHER_FULL_ALWAYS
,
541 [MESA_FORMAT_ARGB4444
] = DV_PF_4444
| DITHER_FULL_ALWAYS
,
545 i915_render_target_supported(gl_format format
)
547 if (format
== MESA_FORMAT_S8_Z24
||
548 format
== MESA_FORMAT_X8_Z24
||
549 format
== MESA_FORMAT_Z16
) {
553 return i915_render_target_format_for_mesa_format
[format
] != 0;
557 i915_set_draw_region(struct intel_context
*intel
,
558 struct intel_region
*color_regions
[],
559 struct intel_region
*depth_region
,
562 struct i915_context
*i915
= i915_context(&intel
->ctx
);
563 struct gl_context
*ctx
= &intel
->ctx
;
564 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
565 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
566 struct gl_renderbuffer
*drb
;
567 struct intel_renderbuffer
*idrb
= NULL
;
569 struct i915_hw_state
*state
= &i915
->state
;
570 uint32_t draw_x
, draw_y
, draw_offset
;
572 if (state
->draw_region
!= color_regions
[0]) {
573 intel_region_release(&state
->draw_region
);
574 intel_region_reference(&state
->draw_region
, color_regions
[0]);
576 if (state
->depth_region
!= depth_region
) {
577 intel_region_release(&state
->depth_region
);
578 intel_region_reference(&state
->depth_region
, depth_region
);
582 * Set stride/cpp values
584 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_CBUFADDR0
],
585 color_regions
[0], BUF_3D_ID_COLOR_BACK
);
587 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_DBUFADDR0
],
588 depth_region
, BUF_3D_ID_DEPTH
);
591 * Compute/set I915_DESTREG_DV1 value
593 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
594 DSTORG_VERT_BIAS(0x8) | /* .5 */
595 LOD_PRECLAMP_OGL
| TEX_DEFAULT_COLOR_OGL
);
597 value
|= i915_render_target_format_for_mesa_format
[irb
->Base
.Format
];
600 /* This isn't quite safe, thus being hidden behind an option. When changing
601 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
602 * can only be set when a depth buffer is already defined.
604 if (intel
->is_945
&& intel
->use_early_z
&&
605 depth_region
->tiling
!= I915_TILING_NONE
)
606 value
|= CLASSIC_EARLY_DEPTH
;
608 if (depth_region
&& depth_region
->cpp
== 4) {
609 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
612 value
|= DEPTH_FRMT_16_FIXED
;
614 state
->Buffer
[I915_DESTREG_DV1
] = value
;
616 drb
= ctx
->DrawBuffer
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
618 drb
= ctx
->DrawBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
621 idrb
= intel_renderbuffer(drb
);
623 /* We set up the drawing rectangle to be offset into the color
624 * region's location in the miptree. If it doesn't match with
625 * depth's offsets, we can't render to it.
627 * (Well, not actually true -- the hw grew a bit to let depth's
628 * offset get forced to 0,0. We may want to use that if people are
629 * hitting that case. Also, some configurations may be supportable
630 * by tweaking the start offset of the buffers around, which we
631 * can't do in general due to tiling)
633 FALLBACK(intel
, I915_FALLBACK_DRAW_OFFSET
,
634 idrb
&& irb
&& (idrb
->draw_x
!= irb
->draw_x
||
635 idrb
->draw_y
!= irb
->draw_y
));
638 draw_x
= irb
->draw_x
;
639 draw_y
= irb
->draw_y
;
641 draw_x
= idrb
->draw_x
;
642 draw_y
= idrb
->draw_y
;
648 draw_offset
= (draw_y
<< 16) | draw_x
;
650 /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
651 if (draw_offset
!= i915
->last_draw_offset
) {
652 FALLBACK(intel
, I915_FALLBACK_DRAW_OFFSET
,
653 (ctx
->DrawBuffer
->Width
+ draw_x
> 2048) ||
654 (ctx
->DrawBuffer
->Height
+ draw_y
> 2048));
656 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_FLUSH
| INHIBIT_FLUSH_RENDER_CACHE
;
657 i915
->last_draw_offset
= draw_offset
;
659 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_NOOP
;
661 state
->Buffer
[I915_DESTREG_DRAWRECT1
] = _3DSTATE_DRAWRECT_INFO
;
662 state
->Buffer
[I915_DESTREG_DRAWRECT2
] = 0;
663 state
->Buffer
[I915_DESTREG_DRAWRECT3
] = draw_offset
;
664 state
->Buffer
[I915_DESTREG_DRAWRECT4
] =
665 ((ctx
->DrawBuffer
->Width
+ draw_x
- 1) & 0xffff) |
666 ((ctx
->DrawBuffer
->Height
+ draw_y
- 1) << 16);
667 state
->Buffer
[I915_DESTREG_DRAWRECT5
] = draw_offset
;
669 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
675 i915_new_batch(struct intel_context
*intel
)
677 struct i915_context
*i915
= i915_context(&intel
->ctx
);
679 /* Mark all state as needing to be emitted when starting a new batchbuffer.
680 * Using hardware contexts would be an alternative, but they have some
681 * difficulties associated with them (physical address requirements).
683 i915
->state
.emitted
= 0;
684 i915
->last_draw_offset
= 0;
685 i915
->last_sampler
= 0;
687 i915
->current_vb_bo
= NULL
;
688 i915
->current_vertex_size
= 0;
692 i915_assert_not_dirty( struct intel_context
*intel
)
694 struct i915_context
*i915
= i915_context(&intel
->ctx
);
695 GLuint dirty
= get_dirty(&i915
->state
);
700 /** Return false; i915 does not support HiZ. */
702 i915_is_hiz_depth_format(struct intel_context
*intel
,
709 i915_invalidate_state(struct intel_context
*intel
, GLuint new_state
)
711 struct gl_context
*ctx
= &intel
->ctx
;
713 _swsetup_InvalidateState(ctx
, new_state
);
714 _tnl_InvalidateState(ctx
, new_state
);
715 _tnl_invalidate_vertex_state(ctx
, new_state
);
719 i915InitVtbl(struct i915_context
*i915
)
721 i915
->intel
.vtbl
.check_vertex_size
= i915_check_vertex_size
;
722 i915
->intel
.vtbl
.destroy
= i915_destroy_context
;
723 i915
->intel
.vtbl
.emit_state
= i915_emit_state
;
724 i915
->intel
.vtbl
.new_batch
= i915_new_batch
;
725 i915
->intel
.vtbl
.reduced_primitive_state
= i915_reduced_primitive_state
;
726 i915
->intel
.vtbl
.render_start
= i915_render_start
;
727 i915
->intel
.vtbl
.render_prevalidate
= i915_render_prevalidate
;
728 i915
->intel
.vtbl
.set_draw_region
= i915_set_draw_region
;
729 i915
->intel
.vtbl
.update_texture_state
= i915UpdateTextureState
;
730 i915
->intel
.vtbl
.assert_not_dirty
= i915_assert_not_dirty
;
731 i915
->intel
.vtbl
.finish_batch
= intel_finish_vb
;
732 i915
->intel
.vtbl
.invalidate_state
= i915_invalidate_state
;
733 i915
->intel
.vtbl
.render_target_supported
= i915_render_target_supported
;
734 i915
->intel
.vtbl
.is_hiz_depth_format
= i915_is_hiz_depth_format
;