src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "main/glheader.h"
  31 #include "main/mtypes.h"
  32 #include "main/imports.h"
  33 #include "main/macros.h"
  34 #include "main/colormac.h"
  35
  36 #include "tnl/t_context.h"
  37 #include "tnl/t_vertex.h"
  38
  39 #include "intel_batchbuffer.h"
  40 #include "intel_tex.h"
  41 #include "intel_regions.h"
  42 #include "intel_tris.h"
  43 #include "intel_fbo.h"
  44 #include "intel_chipset.h"
  45
  46 #include "i915_reg.h"
  47 #include "i915_context.h"
  48
  49 static void
  50 i915_render_prevalidate(struct intel_context *intel)
  51 {
  52    struct i915_context *i915 = i915_context(&intel->ctx);
  53
  54    i915ValidateFragmentProgram(i915);
  55 }
  56
  57 static void
  58 i915_render_start(struct intel_context *intel)
  59 {
  60 }
  61
  62
  63 static void
  64 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  65 {
  66    struct i915_context *i915 = i915_context(&intel->ctx);
  67    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  68
  69    st1 &= ~ST1_ENABLE;
  70
  71    switch (rprim) {
  72    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  73    case GL_TRIANGLES:
  74       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  75          st1 |= ST1_ENABLE;
  76       break;
  77    case GL_LINES:
  78    case GL_POINTS:
  79    default:
  80       break;
  81    }
  82
  83    i915->intel.reduced_primitive = rprim;
  84
  85    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  86       INTEL_FIREVERTICES(intel);
  87
  88       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  89       i915->state.Stipple[I915_STPREG_ST1] = st1;
  90    }
  91 }
  92
  93
  94 /* Pull apart the vertex format registers and figure out how large a
  95  * vertex is supposed to be.
  96  */
  97 static GLboolean
  98 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
  99 {
 100    struct i915_context *i915 = i915_context(&intel->ctx);
 101    int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
 102    int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
 103    int i, sz = 0;
 104
 105    switch (lis4 & S4_VFMT_XYZW_MASK) {
 106    case S4_VFMT_XY:
 107       sz = 2;
 108       break;
 109    case S4_VFMT_XYZ:
 110       sz = 3;
 111       break;
 112    case S4_VFMT_XYW:
 113       sz = 3;
 114       break;
 115    case S4_VFMT_XYZW:
 116       sz = 4;
 117       break;
 118    default:
 119       fprintf(stderr, "no xyzw specified\n");
 120       return 0;
 121    }
 122
 123    if (lis4 & S4_VFMT_SPEC_FOG)
 124       sz++;
 125    if (lis4 & S4_VFMT_COLOR)
 126       sz++;
 127    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 128       sz++;
 129    if (lis4 & S4_VFMT_POINT_WIDTH)
 130       sz++;
 131    if (lis4 & S4_VFMT_FOG_PARAM)
 132       sz++;
 133
 134    for (i = 0; i < 8; i++) {
 135       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 136       case TEXCOORDFMT_2D:
 137          sz += 2;
 138          break;
 139       case TEXCOORDFMT_3D:
 140          sz += 3;
 141          break;
 142       case TEXCOORDFMT_4D:
 143          sz += 4;
 144          break;
 145       case TEXCOORDFMT_1D:
 146          sz += 1;
 147          break;
 148       case TEXCOORDFMT_2D_16:
 149          sz += 1;
 150          break;
 151       case TEXCOORDFMT_4D_16:
 152          sz += 2;
 153          break;
 154       case TEXCOORDFMT_NOT_PRESENT:
 155          break;
 156       default:
 157          fprintf(stderr, "bad texcoord fmt %d\n", i);
 158          return GL_FALSE;
 159       }
 160       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 161    }
 162
 163    if (sz != expected)
 164       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 165
 166    return sz == expected;
 167 }
 168
 169
 170 static void
 171 i915_emit_invarient_state(struct intel_context *intel)
 172 {
 173    BATCH_LOCALS;
 174
 175    BEGIN_BATCH(17);
 176
 177    OUT_BATCH(_3DSTATE_AA_CMD |
 178              AA_LINE_ECAAR_WIDTH_ENABLE |
 179              AA_LINE_ECAAR_WIDTH_1_0 |
 180              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 181
 182    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 183    OUT_BATCH(0);
 184
 185    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 186    OUT_BATCH(0);
 187
 188    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 189    OUT_BATCH(0);
 190
 191    /* Don't support texture crossbar yet */
 192    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 193              CSB_TCB(0, 0) |
 194              CSB_TCB(1, 1) |
 195              CSB_TCB(2, 2) |
 196              CSB_TCB(3, 3) |
 197              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 198
 199    /* Need to initialize this to zero.
 200     */
 201    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 202    OUT_BATCH(0);
 203
 204    /* XXX: Use this */
 205    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 206
 207    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 208    OUT_BATCH(0);
 209    OUT_BATCH(0);
 210
 211    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 212
 213    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 214    OUT_BATCH(0);
 215
 216    ADVANCE_BATCH();
 217 }
 218
 219
 220 #define emit(intel, state, size )                    \
 221    intel_batchbuffer_data(intel->batch, state, size)
 222
 223 static GLuint
 224 get_dirty(struct i915_hw_state *state)
 225 {
 226    GLuint dirty;
 227
 228    /* Workaround the multitex hang - if one texture unit state is
 229     * modified, emit all texture units.
 230     */
 231    dirty = state->active & ~state->emitted;
 232    if (dirty & I915_UPLOAD_TEX_ALL)
 233       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 234    dirty = state->active & ~state->emitted;
 235    return dirty;
 236 }
 237
 238
 239 static GLuint
 240 get_state_size(struct i915_hw_state *state)
 241 {
 242    GLuint dirty = get_dirty(state);
 243    GLuint i;
 244    GLuint sz = 0;
 245
 246    if (dirty & I915_UPLOAD_INVARIENT)
 247       sz += 30 * 4;
 248
 249    if (dirty & I915_UPLOAD_RASTER_RULES)
 250       sz += sizeof(state->RasterRules);
 251
 252    if (dirty & I915_UPLOAD_CTX)
 253       sz += sizeof(state->Ctx);
 254
 255    if (dirty & I915_UPLOAD_BUFFERS)
 256       sz += sizeof(state->Buffer);
 257
 258    if (dirty & I915_UPLOAD_STIPPLE)
 259       sz += sizeof(state->Stipple);
 260
 261    if (dirty & I915_UPLOAD_FOG)
 262       sz += sizeof(state->Fog);
 263
 264    if (dirty & I915_UPLOAD_TEX_ALL) {
 265       int nr = 0;
 266       for (i = 0; i < I915_TEX_UNITS; i++)
 267          if (dirty & I915_UPLOAD_TEX(i))
 268             nr++;
 269
 270       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 271    }
 272
 273    if (dirty & I915_UPLOAD_CONSTANTS)
 274       sz += state->ConstantSize * sizeof(GLuint);
 275
 276    if (dirty & I915_UPLOAD_PROGRAM)
 277       sz += state->ProgramSize * sizeof(GLuint);
 278
 279    return sz;
 280 }
 281
 282 /* Push the state into the sarea and/or texture memory.
 283  */
 284 static void
 285 i915_emit_state(struct intel_context *intel)
 286 {
 287    struct i915_context *i915 = i915_context(&intel->ctx);
 288    struct i915_hw_state *state = i915->current;
 289    int i, count, aper_count;
 290    GLuint dirty;
 291    dri_bo *aper_array[3 + I915_TEX_UNITS];
 292    GET_CURRENT_CONTEXT(ctx);
 293    BATCH_LOCALS;
 294
 295    /* We don't hold the lock at this point, so want to make sure that
 296     * there won't be a buffer wrap between the state emits and the primitive
 297     * emit header.
 298     *
 299     * It might be better to talk about explicit places where
 300     * scheduling is allowed, rather than assume that it is whenever a
 301     * batchbuffer fills up.
 302     */
 303    intel_batchbuffer_require_space(intel->batch,
 304                                    get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
 305    count = 0;
 306  again:
 307    aper_count = 0;
 308    dirty = get_dirty(state);
 309
 310    aper_array[aper_count++] = intel->batch->buf;
 311    if (dirty & I915_UPLOAD_BUFFERS) {
 312       aper_array[aper_count++] = state->draw_region->buffer;
 313       if (state->depth_region)
 314          aper_array[aper_count++] = state->depth_region->buffer;
 315    }
 316
 317    if (dirty & I915_UPLOAD_TEX_ALL) {
 318       for (i = 0; i < I915_TEX_UNITS; i++) {
 319          if (dirty & I915_UPLOAD_TEX(i)) {
 320             if (state->tex_buffer[i]) {
 321                aper_array[aper_count++] = state->tex_buffer[i];
 322             }
 323          }
 324       }
 325    }
 326
 327    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
 328        if (count == 0) {
 329            count++;
 330            intel_batchbuffer_flush(intel->batch);
 331            goto again;
 332        } else {
 333            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 334            assert(0);
 335        }
 336    }
 337
 338    /* work out list of buffers to emit */
 339
 340    /* Do this here as we may have flushed the batchbuffer above,
 341     * causing more state to be dirty!
 342     */
 343    dirty = get_dirty(state);
 344    state->emitted |= dirty;
 345    assert(get_dirty(state) == 0);
 346
 347    if (INTEL_DEBUG & DEBUG_STATE)
 348       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 349
 350    if (dirty & I915_UPLOAD_INVARIENT) {
 351       if (INTEL_DEBUG & DEBUG_STATE)
 352          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 353       i915_emit_invarient_state(intel);
 354    }
 355
 356    if (dirty & I915_UPLOAD_RASTER_RULES) {
 357       if (INTEL_DEBUG & DEBUG_STATE)
 358          fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
 359       emit(intel, state->RasterRules, sizeof(state->RasterRules));
 360    }
 361
 362    if (dirty & I915_UPLOAD_CTX) {
 363       if (INTEL_DEBUG & DEBUG_STATE)
 364          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 365
 366       emit(intel, state->Ctx, sizeof(state->Ctx));
 367    }
 368
 369    if (dirty & I915_UPLOAD_BUFFERS) {
 370       GLuint count = 15;
 371
 372       if (INTEL_DEBUG & DEBUG_STATE)
 373          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 374
 375       if (state->depth_region)
 376           count += 3;
 377
 378       BEGIN_BATCH(count);
 379       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 380       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 381       OUT_RELOC(state->draw_region->buffer,
 382                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 383                 state->draw_region->draw_offset);
 384
 385       if (state->depth_region) {
 386          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 387          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 388          OUT_RELOC(state->depth_region->buffer,
 389                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 390                    state->depth_region->draw_offset);
 391       }
 392
 393       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 394       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 395       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 396       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 397       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 398       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 399
 400       assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
 401       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
 402       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
 403       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
 404       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
 405       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
 406       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
 407
 408       ADVANCE_BATCH();
 409    }
 410
 411    if (dirty & I915_UPLOAD_STIPPLE) {
 412       if (INTEL_DEBUG & DEBUG_STATE)
 413          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 414       emit(intel, state->Stipple, sizeof(state->Stipple));
 415    }
 416
 417    if (dirty & I915_UPLOAD_FOG) {
 418       if (INTEL_DEBUG & DEBUG_STATE)
 419          fprintf(stderr, "I915_UPLOAD_FOG:\n");
 420       emit(intel, state->Fog, sizeof(state->Fog));
 421    }
 422
 423    /* Combine all the dirty texture state into a single command to
 424     * avoid lockups on I915 hardware.
 425     */
 426    if (dirty & I915_UPLOAD_TEX_ALL) {
 427       int nr = 0;
 428
 429       for (i = 0; i < I915_TEX_UNITS; i++)
 430          if (dirty & I915_UPLOAD_TEX(i))
 431             nr++;
 432
 433       BEGIN_BATCH(2 + nr * 3);
 434       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 435       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 436       for (i = 0; i < I915_TEX_UNITS; i++)
 437          if (dirty & I915_UPLOAD_TEX(i)) {
 438
 439             if (state->tex_buffer[i]) {
 440                OUT_RELOC(state->tex_buffer[i],
 441                          I915_GEM_DOMAIN_SAMPLER, 0,
 442                          state->tex_offset[i]);
 443             }
 444             else if (state == &i915->meta) {
 445                assert(i == 0);
 446                OUT_BATCH(0);
 447             }
 448             else {
 449                OUT_BATCH(state->tex_offset[i]);
 450             }
 451
 452             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 453             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 454          }
 455       ADVANCE_BATCH();
 456
 457       BEGIN_BATCH(2 + nr * 3);
 458       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 459       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 460       for (i = 0; i < I915_TEX_UNITS; i++)
 461          if (dirty & I915_UPLOAD_TEX(i)) {
 462             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 463             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 464             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 465          }
 466       ADVANCE_BATCH();
 467    }
 468
 469    if (dirty & I915_UPLOAD_CONSTANTS) {
 470       if (INTEL_DEBUG & DEBUG_STATE)
 471          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 472       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 473    }
 474
 475    if (dirty & I915_UPLOAD_PROGRAM) {
 476       if (state->ProgramSize) {
 477          if (INTEL_DEBUG & DEBUG_STATE)
 478             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 479
 480          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 481
 482          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 483          if (INTEL_DEBUG & DEBUG_STATE)
 484             i915_disassemble_program(state->Program, state->ProgramSize);
 485       }
 486    }
 487
 488    intel->batch->dirty_state &= ~dirty;
 489    assert(get_dirty(state) == 0);
 490    assert((intel->batch->dirty_state & (1<<1)) == 0);
 491 }
 492
 493 static void
 494 i915_destroy_context(struct intel_context *intel)
 495 {
 496    GLuint i;
 497    struct i915_context *i915 = i915_context(&intel->ctx);
 498
 499    intel_region_release(&i915->state.draw_region);
 500    intel_region_release(&i915->state.depth_region);
 501    intel_region_release(&i915->meta.draw_region);
 502    intel_region_release(&i915->meta.depth_region);
 503    intel_region_release(&i915->initial.draw_region);
 504    intel_region_release(&i915->initial.depth_region);
 505
 506    for (i = 0; i < I915_TEX_UNITS; i++) {
 507       if (i915->state.tex_buffer[i] != NULL) {
 508          dri_bo_unreference(i915->state.tex_buffer[i]);
 509          i915->state.tex_buffer[i] = NULL;
 510       }
 511    }
 512
 513    _tnl_free_vertices(&intel->ctx);
 514 }
 515
 516 void
 517 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 518                              uint32_t buffer_id)
 519 {
 520    state[0] = _3DSTATE_BUF_INFO_CMD;
 521    state[1] = buffer_id;
 522
 523    if (region != NULL) {
 524       state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
 525
 526       if (region->tiling != I915_TILING_NONE) {
 527          state[1] |= BUF_3D_TILED_SURFACE;
 528          if (region->tiling == I915_TILING_Y)
 529             state[1] |= BUF_3D_TILE_WALK_Y;
 530       }
 531    }
 532 }
 533
 534 /**
 535  * Set the drawing regions for the color and depth/stencil buffers.
 536  * This involves setting the pitch, cpp and buffer ID/location.
 537  * Also set pixel format for color and Z rendering
 538  * Used for setting both regular and meta state.
 539  */
 540 void
 541 i915_state_draw_region(struct intel_context *intel,
 542                        struct i915_hw_state *state,
 543                        struct intel_region *color_region,
 544                        struct intel_region *depth_region)
 545 {
 546    struct i915_context *i915 = i915_context(&intel->ctx);
 547    GLcontext *ctx = &intel->ctx;
 548    struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
 549    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 550    GLuint value;
 551
 552    ASSERT(state == &i915->state || state == &i915->meta);
 553
 554    if (state->draw_region != color_region) {
 555       intel_region_release(&state->draw_region);
 556       intel_region_reference(&state->draw_region, color_region);
 557    }
 558    if (state->depth_region != depth_region) {
 559       intel_region_release(&state->depth_region);
 560       intel_region_reference(&state->depth_region, depth_region);
 561    }
 562
 563    /*
 564     * Set stride/cpp values
 565     */
 566    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
 567                                 color_region, BUF_3D_ID_COLOR_BACK);
 568
 569    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
 570                                 depth_region, BUF_3D_ID_DEPTH);
 571
 572    /*
 573     * Compute/set I915_DESTREG_DV1 value
 574     */
 575    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 576             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 577             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 578    if (irb != NULL) {
 579       switch (irb->Base.Format) {
 580       case MESA_FORMAT_ARGB8888:
 581       case MESA_FORMAT_XRGB8888:
 582          value |= DV_PF_8888;
 583          break;
 584       case MESA_FORMAT_RGB565:
 585          value |= DV_PF_565 | DITHER_FULL_ALWAYS;
 586          break;
 587       case MESA_FORMAT_ARGB1555:
 588          value |= DV_PF_1555 | DITHER_FULL_ALWAYS;
 589          break;
 590       case MESA_FORMAT_ARGB4444:
 591          value |= DV_PF_4444 | DITHER_FULL_ALWAYS;
 592          break;
 593       default:
 594          _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
 595                        irb->Base.Format);
 596       }
 597    }
 598
 599    /* This isn't quite safe, thus being hidden behind an option.  When changing
 600     * the value of this bit, the pipeline needs to be MI_FLUSHed.  And it
 601     * can only be set when a depth buffer is already defined.
 602     */
 603    if (intel->is_945 && intel->use_early_z &&
 604        depth_region->tiling != I915_TILING_NONE)
 605       value |= CLASSIC_EARLY_DEPTH;
 606
 607    if (depth_region && depth_region->cpp == 4) {
 608       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 609    }
 610    else {
 611       value |= DEPTH_FRMT_16_FIXED;
 612    }
 613    state->Buffer[I915_DESTREG_DV1] = value;
 614
 615    state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
 616    state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
 617    state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
 618    state->Buffer[I915_DESTREG_DRAWRECT3] =
 619       (ctx->DrawBuffer->Width & 0xffff) |
 620       (ctx->DrawBuffer->Height << 16);
 621    state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
 622    state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
 623
 624    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 625 }
 626
 627
 628 static void
 629 i915_set_draw_region(struct intel_context *intel,
 630                      struct intel_region *color_regions[],
 631                      struct intel_region *depth_region,
 632                      GLuint num_regions)
 633 {
 634    struct i915_context *i915 = i915_context(&intel->ctx);
 635    i915_state_draw_region(intel, &i915->state, color_regions[0], depth_region);
 636 }
 637
 638
 639
 640 static void
 641 i915_new_batch(struct intel_context *intel)
 642 {
 643    struct i915_context *i915 = i915_context(&intel->ctx);
 644
 645    /* Mark all state as needing to be emitted when starting a new batchbuffer.
 646     * Using hardware contexts would be an alternative, but they have some
 647     * difficulties associated with them (physical address requirements).
 648     */
 649    i915->state.emitted = 0;
 650 }
 651
 652 static void
 653 i915_assert_not_dirty( struct intel_context *intel )
 654 {
 655    struct i915_context *i915 = i915_context(&intel->ctx);
 656    struct i915_hw_state *state = i915->current;
 657    GLuint dirty = get_dirty(state);
 658    assert(!dirty);
 659 }
 660
 661 void
 662 i915InitVtbl(struct i915_context *i915)
 663 {
 664    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 665    i915->intel.vtbl.destroy = i915_destroy_context;
 666    i915->intel.vtbl.emit_state = i915_emit_state;
 667    i915->intel.vtbl.new_batch = i915_new_batch;
 668    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 669    i915->intel.vtbl.render_start = i915_render_start;
 670    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 671    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 672    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 673    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 674    i915->intel.vtbl.finish_batch = intel_finish_vb;
 675 }