1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
36 #include "tnl/t_context.h"
37 #include "tnl/t_vertex.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_tex.h"
41 #include "intel_regions.h"
42 #include "intel_tris.h"
43 #include "intel_fbo.h"
44 #include "intel_chipset.h"
47 #include "i915_context.h"
49 #include "glapi/glapi.h"
52 i915_render_prevalidate(struct intel_context
*intel
)
54 struct i915_context
*i915
= i915_context(&intel
->ctx
);
56 i915ValidateFragmentProgram(i915
);
60 i915_render_start(struct intel_context
*intel
)
66 i915_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
68 struct i915_context
*i915
= i915_context(&intel
->ctx
);
69 GLuint st1
= i915
->state
.Stipple
[I915_STPREG_ST1
];
74 case GL_QUADS
: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
76 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
85 i915
->intel
.reduced_primitive
= rprim
;
87 if (st1
!= i915
->state
.Stipple
[I915_STPREG_ST1
]) {
88 INTEL_FIREVERTICES(intel
);
90 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
91 i915
->state
.Stipple
[I915_STPREG_ST1
] = st1
;
96 /* Pull apart the vertex format registers and figure out how large a
97 * vertex is supposed to be.
100 i915_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
102 struct i915_context
*i915
= i915_context(&intel
->ctx
);
103 int lis2
= i915
->current
->Ctx
[I915_CTXREG_LIS2
];
104 int lis4
= i915
->current
->Ctx
[I915_CTXREG_LIS4
];
107 switch (lis4
& S4_VFMT_XYZW_MASK
) {
121 fprintf(stderr
, "no xyzw specified\n");
125 if (lis4
& S4_VFMT_SPEC_FOG
)
127 if (lis4
& S4_VFMT_COLOR
)
129 if (lis4
& S4_VFMT_DEPTH_OFFSET
)
131 if (lis4
& S4_VFMT_POINT_WIDTH
)
133 if (lis4
& S4_VFMT_FOG_PARAM
)
136 for (i
= 0; i
< 8; i
++) {
137 switch (lis2
& S2_TEXCOORD_FMT0_MASK
) {
150 case TEXCOORDFMT_2D_16
:
153 case TEXCOORDFMT_4D_16
:
156 case TEXCOORDFMT_NOT_PRESENT
:
159 fprintf(stderr
, "bad texcoord fmt %d\n", i
);
162 lis2
>>= S2_TEXCOORD_FMT1_SHIFT
;
166 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
168 return sz
== expected
;
173 i915_emit_invarient_state(struct intel_context
*intel
)
177 BEGIN_BATCH(17, IGNORE_CLIPRECTS
);
179 OUT_BATCH(_3DSTATE_AA_CMD
|
180 AA_LINE_ECAAR_WIDTH_ENABLE
|
181 AA_LINE_ECAAR_WIDTH_1_0
|
182 AA_LINE_REGION_WIDTH_ENABLE
| AA_LINE_REGION_WIDTH_1_0
);
184 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
187 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
190 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
193 /* Don't support texture crossbar yet */
194 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS
|
199 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
201 /* Need to initialize this to zero.
203 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1
| I1_LOAD_S(3) | (0));
207 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
209 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD
);
213 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE
);
215 OUT_BATCH(_3DSTATE_LOAD_INDIRECT
| 0); /* disable indirect state */
222 #define emit(intel, state, size ) \
223 intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
226 get_dirty(struct i915_hw_state
*state
)
230 /* Workaround the multitex hang - if one texture unit state is
231 * modified, emit all texture units.
233 dirty
= state
->active
& ~state
->emitted
;
234 if (dirty
& I915_UPLOAD_TEX_ALL
)
235 state
->emitted
&= ~I915_UPLOAD_TEX_ALL
;
236 dirty
= state
->active
& ~state
->emitted
;
242 get_state_size(struct i915_hw_state
*state
)
244 GLuint dirty
= get_dirty(state
);
248 if (dirty
& I915_UPLOAD_INVARIENT
)
251 if (dirty
& I915_UPLOAD_RASTER_RULES
)
252 sz
+= sizeof(state
->RasterRules
);
254 if (dirty
& I915_UPLOAD_CTX
)
255 sz
+= sizeof(state
->Ctx
);
257 if (dirty
& I915_UPLOAD_BUFFERS
)
258 sz
+= sizeof(state
->Buffer
);
260 if (dirty
& I915_UPLOAD_STIPPLE
)
261 sz
+= sizeof(state
->Stipple
);
263 if (dirty
& I915_UPLOAD_FOG
)
264 sz
+= sizeof(state
->Fog
);
266 if (dirty
& I915_UPLOAD_TEX_ALL
) {
268 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
269 if (dirty
& I915_UPLOAD_TEX(i
))
272 sz
+= (2 + nr
* 3) * sizeof(GLuint
) * 2;
275 if (dirty
& I915_UPLOAD_CONSTANTS
)
276 sz
+= state
->ConstantSize
* sizeof(GLuint
);
278 if (dirty
& I915_UPLOAD_PROGRAM
)
279 sz
+= state
->ProgramSize
* sizeof(GLuint
);
284 /* Push the state into the sarea and/or texture memory.
287 i915_emit_state(struct intel_context
*intel
)
289 struct i915_context
*i915
= i915_context(&intel
->ctx
);
290 struct i915_hw_state
*state
= i915
->current
;
291 int i
, count
, aper_count
;
293 dri_bo
*aper_array
[3 + I915_TEX_UNITS
];
294 GET_CURRENT_CONTEXT(ctx
);
297 /* We don't hold the lock at this point, so want to make sure that
298 * there won't be a buffer wrap between the state emits and the primitive
301 * It might be better to talk about explicit places where
302 * scheduling is allowed, rather than assume that it is whenever a
303 * batchbuffer fills up.
305 * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
306 * will be emitted under.
308 intel_batchbuffer_require_space(intel
->batch
,
309 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
314 dirty
= get_dirty(state
);
316 aper_array
[aper_count
++] = intel
->batch
->buf
;
317 if (dirty
& I915_UPLOAD_BUFFERS
) {
318 aper_array
[aper_count
++] = state
->draw_region
->buffer
;
319 if (state
->depth_region
)
320 aper_array
[aper_count
++] = state
->depth_region
->buffer
;
323 if (dirty
& I915_UPLOAD_TEX_ALL
) {
324 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
325 if (dirty
& I915_UPLOAD_TEX(i
)) {
326 if (state
->tex_buffer
[i
]) {
327 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
333 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
336 intel_batchbuffer_flush(intel
->batch
);
339 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i915 emit state");
344 /* work out list of buffers to emit */
346 /* Do this here as we may have flushed the batchbuffer above,
347 * causing more state to be dirty!
349 dirty
= get_dirty(state
);
350 state
->emitted
|= dirty
;
351 assert(get_dirty(state
) == 0);
353 if (INTEL_DEBUG
& DEBUG_STATE
)
354 fprintf(stderr
, "%s dirty: %x\n", __FUNCTION__
, dirty
);
356 if (dirty
& I915_UPLOAD_INVARIENT
) {
357 if (INTEL_DEBUG
& DEBUG_STATE
)
358 fprintf(stderr
, "I915_UPLOAD_INVARIENT:\n");
359 i915_emit_invarient_state(intel
);
362 if (dirty
& I915_UPLOAD_RASTER_RULES
) {
363 if (INTEL_DEBUG
& DEBUG_STATE
)
364 fprintf(stderr
, "I915_UPLOAD_RASTER_RULES:\n");
365 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
368 if (dirty
& I915_UPLOAD_CTX
) {
369 if (INTEL_DEBUG
& DEBUG_STATE
)
370 fprintf(stderr
, "I915_UPLOAD_CTX:\n");
372 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
375 if (dirty
& I915_UPLOAD_BUFFERS
) {
378 if (INTEL_DEBUG
& DEBUG_STATE
)
379 fprintf(stderr
, "I915_UPLOAD_BUFFERS:\n");
381 if (state
->depth_region
)
384 if (intel
->constant_cliprect
)
387 BEGIN_BATCH(count
, IGNORE_CLIPRECTS
);
388 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR0
]);
389 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR1
]);
390 OUT_RELOC(state
->draw_region
->buffer
,
391 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
392 state
->draw_region
->draw_offset
);
394 if (state
->depth_region
) {
395 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR0
]);
396 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR1
]);
397 OUT_RELOC(state
->depth_region
->buffer
,
398 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
399 state
->depth_region
->draw_offset
);
402 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV0
]);
403 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV1
]);
404 OUT_BATCH(state
->Buffer
[I915_DESTREG_SENABLE
]);
405 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR0
]);
406 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR1
]);
407 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR2
]);
409 if (intel
->constant_cliprect
) {
410 assert(state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
);
411 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT0
]);
412 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT1
]);
413 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT2
]);
414 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT3
]);
415 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT4
]);
416 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT5
]);
422 if (dirty
& I915_UPLOAD_STIPPLE
) {
423 if (INTEL_DEBUG
& DEBUG_STATE
)
424 fprintf(stderr
, "I915_UPLOAD_STIPPLE:\n");
425 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
428 if (dirty
& I915_UPLOAD_FOG
) {
429 if (INTEL_DEBUG
& DEBUG_STATE
)
430 fprintf(stderr
, "I915_UPLOAD_FOG:\n");
431 emit(intel
, state
->Fog
, sizeof(state
->Fog
));
434 /* Combine all the dirty texture state into a single command to
435 * avoid lockups on I915 hardware.
437 if (dirty
& I915_UPLOAD_TEX_ALL
) {
440 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
441 if (dirty
& I915_UPLOAD_TEX(i
))
444 BEGIN_BATCH(2 + nr
* 3, IGNORE_CLIPRECTS
);
445 OUT_BATCH(_3DSTATE_MAP_STATE
| (3 * nr
));
446 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
447 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
448 if (dirty
& I915_UPLOAD_TEX(i
)) {
450 if (state
->tex_buffer
[i
]) {
451 OUT_RELOC(state
->tex_buffer
[i
],
452 I915_GEM_DOMAIN_SAMPLER
, 0,
453 state
->tex_offset
[i
]);
455 else if (state
== &i915
->meta
) {
460 OUT_BATCH(state
->tex_offset
[i
]);
463 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS3
]);
464 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS4
]);
468 BEGIN_BATCH(2 + nr
* 3, IGNORE_CLIPRECTS
);
469 OUT_BATCH(_3DSTATE_SAMPLER_STATE
| (3 * nr
));
470 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
471 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
472 if (dirty
& I915_UPLOAD_TEX(i
)) {
473 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS2
]);
474 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS3
]);
475 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS4
]);
480 if (dirty
& I915_UPLOAD_CONSTANTS
) {
481 if (INTEL_DEBUG
& DEBUG_STATE
)
482 fprintf(stderr
, "I915_UPLOAD_CONSTANTS:\n");
483 emit(intel
, state
->Constant
, state
->ConstantSize
* sizeof(GLuint
));
486 if (dirty
& I915_UPLOAD_PROGRAM
) {
487 if (state
->ProgramSize
) {
488 if (INTEL_DEBUG
& DEBUG_STATE
)
489 fprintf(stderr
, "I915_UPLOAD_PROGRAM:\n");
491 assert((state
->Program
[0] & 0x1ff) + 2 == state
->ProgramSize
);
493 emit(intel
, state
->Program
, state
->ProgramSize
* sizeof(GLuint
));
494 if (INTEL_DEBUG
& DEBUG_STATE
)
495 i915_disassemble_program(state
->Program
, state
->ProgramSize
);
499 intel
->batch
->dirty_state
&= ~dirty
;
500 assert(get_dirty(state
) == 0);
501 assert((intel
->batch
->dirty_state
& (1<<1)) == 0);
505 i915_destroy_context(struct intel_context
*intel
)
508 struct i915_context
*i915
= i915_context(&intel
->ctx
);
510 intel_region_release(&i915
->state
.draw_region
);
511 intel_region_release(&i915
->state
.depth_region
);
512 intel_region_release(&i915
->meta
.draw_region
);
513 intel_region_release(&i915
->meta
.depth_region
);
514 intel_region_release(&i915
->initial
.draw_region
);
515 intel_region_release(&i915
->initial
.depth_region
);
517 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
518 if (i915
->state
.tex_buffer
[i
] != NULL
) {
519 dri_bo_unreference(i915
->state
.tex_buffer
[i
]);
520 i915
->state
.tex_buffer
[i
] = NULL
;
524 _tnl_free_vertices(&intel
->ctx
);
528 i915_set_buf_info_for_region(uint32_t *state
, struct intel_region
*region
,
531 state
[0] = _3DSTATE_BUF_INFO_CMD
;
532 state
[1] = buffer_id
;
534 if (region
!= NULL
) {
535 state
[1] |= BUF_3D_PITCH(region
->pitch
* region
->cpp
);
537 if (region
->tiling
!= I915_TILING_NONE
) {
538 state
[1] |= BUF_3D_TILED_SURFACE
;
539 if (region
->tiling
== I915_TILING_Y
)
540 state
[1] |= BUF_3D_TILE_WALK_Y
;
546 * Set the drawing regions for the color and depth/stencil buffers.
547 * This involves setting the pitch, cpp and buffer ID/location.
548 * Also set pixel format for color and Z rendering
549 * Used for setting both regular and meta state.
552 i915_state_draw_region(struct intel_context
*intel
,
553 struct i915_hw_state
*state
,
554 struct intel_region
*color_region
,
555 struct intel_region
*depth_region
)
557 struct i915_context
*i915
= i915_context(&intel
->ctx
);
558 GLcontext
*ctx
= &intel
->ctx
;
559 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
560 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
563 ASSERT(state
== &i915
->state
|| state
== &i915
->meta
);
565 if (state
->draw_region
!= color_region
) {
566 intel_region_release(&state
->draw_region
);
567 intel_region_reference(&state
->draw_region
, color_region
);
569 if (state
->depth_region
!= depth_region
) {
570 intel_region_release(&state
->depth_region
);
571 intel_region_reference(&state
->depth_region
, depth_region
);
575 * Set stride/cpp values
577 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_CBUFADDR0
],
578 color_region
, BUF_3D_ID_COLOR_BACK
);
580 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_DBUFADDR0
],
581 depth_region
, BUF_3D_ID_DEPTH
);
584 * Compute/set I915_DESTREG_DV1 value
586 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
587 DSTORG_VERT_BIAS(0x8) | /* .5 */
588 LOD_PRECLAMP_OGL
| TEX_DEFAULT_COLOR_OGL
);
590 switch (irb
->texformat
) {
591 case MESA_FORMAT_ARGB8888
:
592 case MESA_FORMAT_XRGB8888
:
595 case MESA_FORMAT_RGB565
:
596 value
|= DV_PF_565
| DITHER_FULL_ALWAYS
;
598 case MESA_FORMAT_ARGB1555
:
599 value
|= DV_PF_1555
| DITHER_FULL_ALWAYS
;
601 case MESA_FORMAT_ARGB4444
:
602 value
|= DV_PF_4444
| DITHER_FULL_ALWAYS
;
605 _mesa_problem(ctx
, "Bad renderbuffer format: %d\n",
610 /* This isn't quite safe, thus being hidden behind an option. When changing
611 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
612 * can only be set when a depth buffer is already defined.
614 if (IS_945(intel
->intelScreen
->deviceID
) && intel
->use_early_z
&&
615 depth_region
->tiling
!= I915_TILING_NONE
)
616 value
|= CLASSIC_EARLY_DEPTH
;
618 if (depth_region
&& depth_region
->cpp
== 4) {
619 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
622 value
|= DEPTH_FRMT_16_FIXED
;
624 state
->Buffer
[I915_DESTREG_DV1
] = value
;
626 if (intel
->constant_cliprect
) {
627 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = _3DSTATE_DRAWRECT_INFO
;
628 state
->Buffer
[I915_DESTREG_DRAWRECT1
] = 0;
629 state
->Buffer
[I915_DESTREG_DRAWRECT2
] = 0; /* xmin, ymin */
630 state
->Buffer
[I915_DESTREG_DRAWRECT3
] =
631 (ctx
->DrawBuffer
->Width
& 0xffff) |
632 (ctx
->DrawBuffer
->Height
<< 16);
633 state
->Buffer
[I915_DESTREG_DRAWRECT4
] = 0; /* xoff, yoff */
634 state
->Buffer
[I915_DESTREG_DRAWRECT5
] = 0;
636 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_NOOP
;
637 state
->Buffer
[I915_DESTREG_DRAWRECT1
] = MI_NOOP
;
638 state
->Buffer
[I915_DESTREG_DRAWRECT2
] = MI_NOOP
;
639 state
->Buffer
[I915_DESTREG_DRAWRECT3
] = MI_NOOP
;
640 state
->Buffer
[I915_DESTREG_DRAWRECT4
] = MI_NOOP
;
641 state
->Buffer
[I915_DESTREG_DRAWRECT5
] = MI_NOOP
;
644 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
649 i915_set_draw_region(struct intel_context
*intel
,
650 struct intel_region
*color_regions
[],
651 struct intel_region
*depth_region
,
654 struct i915_context
*i915
= i915_context(&intel
->ctx
);
655 i915_state_draw_region(intel
, &i915
->state
, color_regions
[0], depth_region
);
661 i915_new_batch(struct intel_context
*intel
)
663 struct i915_context
*i915
= i915_context(&intel
->ctx
);
665 /* Mark all state as needing to be emitted when starting a new batchbuffer.
666 * Using hardware contexts would be an alternative, but they have some
667 * difficulties associated with them (physical address requirements).
669 i915
->state
.emitted
= 0;
673 i915_assert_not_dirty( struct intel_context
*intel
)
675 struct i915_context
*i915
= i915_context(&intel
->ctx
);
676 struct i915_hw_state
*state
= i915
->current
;
677 GLuint dirty
= get_dirty(state
);
682 i915InitVtbl(struct i915_context
*i915
)
684 i915
->intel
.vtbl
.check_vertex_size
= i915_check_vertex_size
;
685 i915
->intel
.vtbl
.destroy
= i915_destroy_context
;
686 i915
->intel
.vtbl
.emit_state
= i915_emit_state
;
687 i915
->intel
.vtbl
.new_batch
= i915_new_batch
;
688 i915
->intel
.vtbl
.reduced_primitive_state
= i915_reduced_primitive_state
;
689 i915
->intel
.vtbl
.render_start
= i915_render_start
;
690 i915
->intel
.vtbl
.render_prevalidate
= i915_render_prevalidate
;
691 i915
->intel
.vtbl
.set_draw_region
= i915_set_draw_region
;
692 i915
->intel
.vtbl
.update_texture_state
= i915UpdateTextureState
;
693 i915
->intel
.vtbl
.assert_not_dirty
= i915_assert_not_dirty
;
694 i915
->intel
.vtbl
.finish_batch
= intel_finish_vb
;