1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
36 #include "intel_batchbuffer.h"
37 #include "intel_blit.h"
38 #include "intel_buffers.h"
39 #include "intel_context.h"
40 #include "intel_fbo.h"
41 #include "intel_reg.h"
42 #include "intel_regions.h"
44 #define FILE_DEBUG_FLAG DEBUG_BLIT
47 * Copy the back color buffer to the front color buffer.
48 * Used for SwapBuffers().
51 intelCopyBuffer(const __DRIdrawablePrivate
* dPriv
,
52 const drm_clip_rect_t
* rect
)
55 struct intel_context
*intel
;
56 const intelScreenPrivate
*intelScreen
;
58 DBG("%s\n", __FUNCTION__
);
62 intel
= intelScreenContext(dPriv
->driScreenPriv
->private);
66 intelScreen
= intel
->intelScreen
;
68 if (intel
->last_swap_fence
) {
69 dri_fence_wait(intel
->last_swap_fence
);
70 dri_fence_unreference(intel
->last_swap_fence
);
71 intel
->last_swap_fence
= NULL
;
73 intel
->last_swap_fence
= intel
->first_swap_fence
;
74 intel
->first_swap_fence
= NULL
;
76 /* The LOCK_HARDWARE is required for the cliprects. Buffer offsets
77 * should work regardless.
81 if (dPriv
&& dPriv
->numClipRects
) {
82 struct intel_framebuffer
*intel_fb
= dPriv
->driverPrivate
;
83 const struct intel_region
*frontRegion
84 = intel_get_rb_region(&intel_fb
->Base
, BUFFER_FRONT_LEFT
);
85 const struct intel_region
*backRegion
86 = intel_get_rb_region(&intel_fb
->Base
, BUFFER_BACK_LEFT
);
87 const int nbox
= dPriv
->numClipRects
;
88 const drm_clip_rect_t
*pbox
= dPriv
->pClipRects
;
89 const int pitch
= frontRegion
->pitch
;
90 const int cpp
= frontRegion
->cpp
;
95 ASSERT(intel_fb
->Base
.Name
== 0); /* Not a user-created FBO */
98 ASSERT(frontRegion
->pitch
== backRegion
->pitch
);
99 ASSERT(frontRegion
->cpp
== backRegion
->cpp
);
102 BR13
= (pitch
* cpp
) | (0xCC << 16) | (1 << 24);
103 CMD
= XY_SRC_COPY_BLT_CMD
;
106 BR13
= (pitch
* cpp
) | (0xCC << 16) | (1 << 24) | (1 << 25);
107 CMD
= (XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
);
110 for (i
= 0; i
< nbox
; i
++, pbox
++) {
113 if (pbox
->x1
> pbox
->x2
||
114 pbox
->y1
> pbox
->y2
||
115 pbox
->x2
> intelScreen
->width
|| pbox
->y2
> intelScreen
->height
)
121 if (rect
->x1
> box
.x1
)
123 if (rect
->y1
> box
.y1
)
125 if (rect
->x2
< box
.x2
)
127 if (rect
->y2
< box
.y2
)
130 if (box
.x1
> box
.x2
|| box
.y1
> box
.y2
)
134 BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS
);
137 OUT_BATCH((pbox
->y1
<< 16) | pbox
->x1
);
138 OUT_BATCH((pbox
->y2
<< 16) | pbox
->x2
);
140 OUT_RELOC(frontRegion
->buffer
, DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_WRITE
,
142 OUT_BATCH((pbox
->y1
<< 16) | pbox
->x1
);
143 OUT_BATCH(BR13
& 0xffff);
144 OUT_RELOC(backRegion
->buffer
, DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_READ
,
150 if (intel
->first_swap_fence
)
151 dri_fence_unreference(intel
->first_swap_fence
);
152 intel_batchbuffer_flush(intel
->batch
);
153 intel
->first_swap_fence
= intel
->batch
->last_fence
;
154 dri_fence_reference(intel
->first_swap_fence
);
157 UNLOCK_HARDWARE(intel
);
164 intelEmitFillBlit(struct intel_context
*intel
,
169 GLshort x
, GLshort y
, GLshort w
, GLshort h
, GLuint color
)
180 BR13
= dst_pitch
| (0xF0 << 16) | (1 << 24);
181 CMD
= XY_COLOR_BLT_CMD
;
184 BR13
= dst_pitch
| (0xF0 << 16) | (1 << 24) | (1 << 25);
185 CMD
= (XY_COLOR_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
);
191 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
192 __FUNCTION__
, dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
);
195 BEGIN_BATCH(6, INTEL_BATCH_NO_CLIPRECTS
);
198 OUT_BATCH((y
<< 16) | x
);
199 OUT_BATCH(((y
+ h
) << 16) | (x
+ w
));
200 OUT_RELOC(dst_buffer
, DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_WRITE
, dst_offset
);
206 static GLuint
translate_raster_op(GLenum logicop
)
209 case GL_CLEAR
: return 0x00;
210 case GL_AND
: return 0x88;
211 case GL_AND_REVERSE
: return 0x44;
212 case GL_COPY
: return 0xCC;
213 case GL_AND_INVERTED
: return 0x22;
214 case GL_NOOP
: return 0xAA;
215 case GL_XOR
: return 0x66;
216 case GL_OR
: return 0xEE;
217 case GL_NOR
: return 0x11;
218 case GL_EQUIV
: return 0x99;
219 case GL_INVERT
: return 0x55;
220 case GL_OR_REVERSE
: return 0xDD;
221 case GL_COPY_INVERTED
: return 0x33;
222 case GL_OR_INVERTED
: return 0xBB;
223 case GL_NAND
: return 0x77;
224 case GL_SET
: return 0xFF;
233 intelEmitCopyBlit(struct intel_context
*intel
,
241 GLshort src_x
, GLshort src_y
,
242 GLshort dst_x
, GLshort dst_y
,
243 GLshort w
, GLshort h
,
247 int dst_y2
= dst_y
+ h
;
248 int dst_x2
= dst_x
+ w
;
252 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
254 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
255 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
264 BR13
= (((GLint
) dst_pitch
) & 0xffff) |
265 (translate_raster_op(logic_op
) << 16) | (1 << 24);
266 CMD
= XY_SRC_COPY_BLT_CMD
;
270 (((GLint
) dst_pitch
) & 0xffff) |
271 (translate_raster_op(logic_op
) << 16) | (1 << 24) | (1 << 25);
273 (XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
);
279 if (dst_y2
< dst_y
|| dst_x2
< dst_x
) {
283 /* Initial y values don't seem to work with negative pitches. If
284 * we adjust the offsets manually (below), it seems to work fine.
286 * On the other hand, if we always adjust, the hardware doesn't
287 * know which blit directions to use, so overlapping copypixels get
290 if (dst_pitch
> 0 && src_pitch
> 0) {
291 BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS
);
294 OUT_BATCH((dst_y
<< 16) | dst_x
);
295 OUT_BATCH((dst_y2
<< 16) | dst_x2
);
296 OUT_RELOC(dst_buffer
, DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_WRITE
, dst_offset
);
297 OUT_BATCH((src_y
<< 16) | src_x
);
298 OUT_BATCH(((GLint
) src_pitch
& 0xffff));
299 OUT_RELOC(src_buffer
, DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_READ
, src_offset
);
303 BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS
);
306 OUT_BATCH((0 << 16) | dst_x
);
307 OUT_BATCH((h
<< 16) | dst_x2
);
308 OUT_RELOC(dst_buffer
, DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_WRITE
,
309 dst_offset
+ dst_y
* dst_pitch
);
310 OUT_BATCH((0 << 16) | src_x
);
311 OUT_BATCH(((GLint
) src_pitch
& 0xffff));
312 OUT_RELOC(src_buffer
, DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_READ
,
313 src_offset
+ src_y
* src_pitch
);
320 * Use blitting to clear the renderbuffers named by 'flags'.
321 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferMask field
322 * since that might include software renderbuffers or renderbuffers
323 * which we're clearing with triangles.
324 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
327 intelClearWithBlit(GLcontext
* ctx
, GLbitfield mask
)
329 struct intel_context
*intel
= intel_context(ctx
);
330 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
332 GLbitfield skipBuffers
= 0;
335 DBG("%s %x\n", __FUNCTION__
, mask
);
338 * Compute values for clearing the buffers.
341 if (mask
& BUFFER_BIT_DEPTH
) {
342 clear_depth
= (GLuint
) (fb
->_DepthMax
* ctx
->Depth
.Clear
);
344 if (mask
& BUFFER_BIT_STENCIL
) {
345 clear_depth
|= (ctx
->Stencil
.Clear
& 0xff) << 24;
348 /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in
351 if ((mask
& BUFFER_BIT_DEPTH
) && (mask
& BUFFER_BIT_STENCIL
)) {
352 skipBuffers
= BUFFER_BIT_STENCIL
;
355 /* XXX Move this flush/lock into the following conditional? */
356 intelFlush(&intel
->ctx
);
357 LOCK_HARDWARE(intel
);
359 if (intel
->numClipRects
) {
360 GLint cx
, cy
, cw
, ch
;
361 drm_clip_rect_t clear
;
364 /* Get clear bounds after locking */
371 /* clearing a window */
373 /* flip top to bottom */
374 clear
.x1
= cx
+ intel
->drawX
;
375 clear
.y1
= intel
->driDrawable
->y
+ intel
->driDrawable
->h
- cy
- ch
;
376 clear
.x2
= clear
.x1
+ cw
;
377 clear
.y2
= clear
.y1
+ ch
;
381 assert(intel
->numClipRects
== 1);
382 assert(intel
->pClipRects
== &intel
->fboRect
);
385 clear
.x2
= clear
.x1
+ cw
;
386 clear
.y2
= clear
.y1
+ ch
;
387 /* no change to mask */
390 for (i
= 0; i
< intel
->numClipRects
; i
++) {
391 const drm_clip_rect_t
*box
= &intel
->pClipRects
[i
];
394 GLuint clearMask
= mask
; /* use copy, since we modify it below */
395 GLboolean all
= (cw
== fb
->Width
&& ch
== fb
->Height
);
398 intel_intersect_cliprects(&b
, &clear
, box
);
404 if (b
.x1
>= b
.x2
|| b
.y1
>= b
.y2
)
408 _mesa_printf("clear %d,%d..%d,%d, mask %x\n",
409 b
.x1
, b
.y1
, b
.x2
, b
.y2
, mask
);
411 /* Loop over all renderbuffers */
412 for (buf
= 0; buf
< BUFFER_COUNT
&& clearMask
; buf
++) {
413 const GLbitfield bufBit
= 1 << buf
;
414 if ((clearMask
& bufBit
) && !(bufBit
& skipBuffers
)) {
415 /* OK, clear this renderbuffer */
416 struct intel_region
*irb_region
=
417 intel_get_rb_region(fb
, buf
);
418 dri_bo
*write_buffer
=
419 intel_region_buffer(intel
->intelScreen
, irb_region
,
420 all
? INTEL_WRITE_FULL
:
429 pitch
= irb_region
->pitch
;
430 cpp
= irb_region
->cpp
;
432 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
434 irb_region
->buffer
, (pitch
* cpp
),
435 irb_region
->draw_offset
,
436 b
.x1
, b
.y1
, b
.x2
- b
.x1
, b
.y2
- b
.y1
);
439 /* Setup the blit command */
441 BR13
= (0xF0 << 16) | (pitch
* cpp
) | (1 << 24) | (1 << 25);
442 if (buf
== BUFFER_DEPTH
|| buf
== BUFFER_STENCIL
) {
443 CMD
= XY_COLOR_BLT_CMD
;
444 if (clearMask
& BUFFER_BIT_DEPTH
)
445 CMD
|= XY_BLT_WRITE_RGB
;
446 if (clearMask
& BUFFER_BIT_STENCIL
)
447 CMD
|= XY_BLT_WRITE_ALPHA
;
451 CMD
= XY_COLOR_BLT_CMD
|
452 XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
456 ASSERT(cpp
== 2 || cpp
== 0);
457 BR13
= (0xF0 << 16) | (pitch
* cpp
) | (1 << 24);
458 CMD
= XY_COLOR_BLT_CMD
;
461 if (buf
== BUFFER_DEPTH
|| buf
== BUFFER_STENCIL
) {
462 clearVal
= clear_depth
;
465 clearVal
= (cpp
== 4)
466 ? intel
->ClearColor8888
: intel
->ClearColor565
;
469 _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n",
470 buf, irb->Base.Name);
472 intel_wait_flips(intel
, INTEL_BATCH_NO_CLIPRECTS
);
474 BEGIN_BATCH(6, INTEL_BATCH_NO_CLIPRECTS
);
477 OUT_BATCH((b
.y1
<< 16) | b
.x1
);
478 OUT_BATCH((b
.y2
<< 16) | b
.x2
);
479 OUT_RELOC(write_buffer
, DRM_BO_FLAG_MEM_TT
| DRM_BO_FLAG_WRITE
,
480 irb_region
->draw_offset
);
483 clearMask
&= ~bufBit
; /* turn off bit, for faster loop exit */
487 intel_batchbuffer_flush(intel
->batch
);
490 UNLOCK_HARDWARE(intel
);