src/mesa/drivers/dri/i915/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33 #include "main/fbobject.h"
  34
  35 #include "intel_blit.h"
  36 #include "intel_buffers.h"
  37 #include "intel_context.h"
  38 #include "intel_fbo.h"
  39 #include "intel_reg.h"
  40 #include "intel_regions.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_mipmap_tree.h"
  43
  44 #define FILE_DEBUG_FLAG DEBUG_BLIT
  45
  46 static void
  47 intel_miptree_set_alpha_to_one(struct intel_context *intel,
  48                                struct intel_mipmap_tree *mt,
  49                                int x, int y, int width, int height);
  50
  51 static GLuint translate_raster_op(enum gl_logicop_mode logicop)
  52 {
  53    return logicop | (logicop << 4);
  54 }
  55
  56 static uint32_t
  57 br13_for_cpp(int cpp)
  58 {
  59    switch (cpp) {
  60    case 4:
  61       return BR13_8888;
  62       break;
  63    case 2:
  64       return BR13_565;
  65       break;
  66    case 1:
  67       return BR13_8;
  68       break;
  69    default:
  70       assert(0);
  71       return 0;
  72    }
  73 }
  74
  75 /**
  76  * Implements a rectangular block transfer (blit) of pixels between two
  77  * miptrees.
  78  *
  79  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
  80  * but limited, pitches and sizes allowed.
  81  *
  82  * The src/dst coordinates are relative to the given level/slice of the
  83  * miptree.
  84  *
  85  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
  86  * will be inverted (including scanline order) when copying.  This is common
  87  * in GL when copying between window system and user-created
  88  * renderbuffers/textures.
  89  */
  90 bool
  91 intel_miptree_blit(struct intel_context *intel,
  92                    struct intel_mipmap_tree *src_mt,
  93                    int src_level, int src_slice,
  94                    uint32_t src_x, uint32_t src_y, bool src_flip,
  95                    struct intel_mipmap_tree *dst_mt,
  96                    int dst_level, int dst_slice,
  97                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
  98                    uint32_t width, uint32_t height,
  99                    enum gl_logicop_mode logicop)
 100 {
 101    /* No sRGB decode or encode is done by the hardware blitter, which is
 102     * consistent with what we want in the callers (glCopyTexSubImage(),
 103     * glBlitFramebuffer(), texture validation, etc.).
 104     */
 105    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 106    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 107
 108    /* The blitter doesn't support doing any format conversions.  We do also
 109     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 110     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 111     * channel to 1.0 at the end.
 112     */
 113    if (src_format != dst_format &&
 114       ((src_format != MESA_FORMAT_B8G8R8A8_UNORM &&
 115         src_format != MESA_FORMAT_B8G8R8X8_UNORM) ||
 116        (dst_format != MESA_FORMAT_B8G8R8A8_UNORM &&
 117         dst_format != MESA_FORMAT_B8G8R8X8_UNORM))) {
 118       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 119                  "falling back.\n", __func__,
 120                  _mesa_get_format_name(src_format),
 121                  _mesa_get_format_name(dst_format));
 122       return false;
 123    }
 124
 125    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 126     * Data Size Limitations):
 127     *
 128     *    The BLT engine is capable of transferring very large quantities of
 129     *    graphics data. Any graphics data read from and written to the
 130     *    destination is permitted to represent a number of pixels that
 131     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 132     *    at the destination. The maximum number of pixels that may be
 133     *    represented per scan line’s worth of graphics data depends on the
 134     *    color depth.
 135     *
 136     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 137     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 138     * pitches < 32k.
 139     *
 140     * As a result of these two limitations, we can only use the blitter to do
 141     * this copy when the region's pitch is less than 32k.
 142     */
 143    if (src_mt->region->pitch > 32768 ||
 144        dst_mt->region->pitch > 32768) {
 145       perf_debug("Falling back due to >32k pitch\n");
 146       return false;
 147    }
 148
 149    if (src_flip)
 150       src_y = src_mt->level[src_level].height - src_y - height;
 151
 152    if (dst_flip)
 153       dst_y = dst_mt->level[dst_level].height - dst_y - height;
 154
 155    int src_pitch = src_mt->region->pitch;
 156    if (src_flip != dst_flip)
 157       src_pitch = -src_pitch;
 158
 159    uint32_t src_image_x, src_image_y;
 160    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 161                                   &src_image_x, &src_image_y);
 162    src_x += src_image_x;
 163    src_y += src_image_y;
 164
 165    uint32_t dst_image_x, dst_image_y;
 166    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 167                                   &dst_image_x, &dst_image_y);
 168    dst_x += dst_image_x;
 169    dst_y += dst_image_y;
 170
 171    if (!intelEmitCopyBlit(intel,
 172                           src_mt->cpp,
 173                           src_pitch,
 174                           src_mt->region->bo, src_mt->offset,
 175                           src_mt->region->tiling,
 176                           dst_mt->region->pitch,
 177                           dst_mt->region->bo, dst_mt->offset,
 178                           dst_mt->region->tiling,
 179                           src_x, src_y,
 180                           dst_x, dst_y,
 181                           width, height,
 182                           logicop)) {
 183       return false;
 184    }
 185
 186    if (src_mt->format == MESA_FORMAT_B8G8R8X8_UNORM &&
 187        dst_mt->format == MESA_FORMAT_B8G8R8A8_UNORM) {
 188       intel_miptree_set_alpha_to_one(intel, dst_mt,
 189                                      dst_x, dst_y,
 190                                      width, height);
 191    }
 192
 193    return true;
 194 }
 195
 196 /* Copy BitBlt
 197  */
 198 bool
 199 intelEmitCopyBlit(struct intel_context *intel,
 200                   GLuint cpp,
 201                   GLshort src_pitch,
 202                   drm_intel_bo *src_buffer,
 203                   GLuint src_offset,
 204                   uint32_t src_tiling,
 205                   GLshort dst_pitch,
 206                   drm_intel_bo *dst_buffer,
 207                   GLuint dst_offset,
 208                   uint32_t dst_tiling,
 209                   GLshort src_x, GLshort src_y,
 210                   GLshort dst_x, GLshort dst_y,
 211                   GLshort w, GLshort h,
 212                   enum gl_logicop_mode logic_op)
 213 {
 214    GLuint CMD, BR13, pass = 0;
 215    int dst_y2 = dst_y + h;
 216    int dst_x2 = dst_x + w;
 217    drm_intel_bo *aper_array[3];
 218    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 219    bool src_y_tiled = src_tiling == I915_TILING_Y;
 220    BATCH_LOCALS;
 221
 222    if (dst_tiling != I915_TILING_NONE) {
 223       if (dst_offset & 4095)
 224          return false;
 225    }
 226    if (src_tiling != I915_TILING_NONE) {
 227       if (src_offset & 4095)
 228          return false;
 229    }
 230    if (dst_y_tiled || src_y_tiled)
 231       return false;
 232
 233    /* do space check before going any further */
 234    do {
 235        aper_array[0] = intel->batch.bo;
 236        aper_array[1] = dst_buffer;
 237        aper_array[2] = src_buffer;
 238
 239        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 240            intel_batchbuffer_flush(intel);
 241            pass++;
 242        } else
 243            break;
 244    } while (pass < 2);
 245
 246    if (pass >= 2)
 247       return false;
 248
 249    intel_batchbuffer_require_space(intel, 8 * 4);
 250    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 251        __func__,
 252        src_buffer, src_pitch, src_offset, src_x, src_y,
 253        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 254
 255    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 256     * the low bits.  Offsets must be naturally aligned.
 257     */
 258    if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
 259        dst_pitch % 4 != 0 || dst_offset % cpp != 0)
 260       return false;
 261
 262    /* For big formats (such as floating point), do the copy using 16 or 32bpp
 263     * and multiply the coordinates.
 264     */
 265    if (cpp > 4) {
 266       if (cpp % 4 == 2) {
 267          dst_x *= cpp / 2;
 268          dst_x2 *= cpp / 2;
 269          src_x *= cpp / 2;
 270          cpp = 2;
 271       } else {
 272          assert(cpp % 4 == 0);
 273          dst_x *= cpp / 4;
 274          dst_x2 *= cpp / 4;
 275          src_x *= cpp / 4;
 276          cpp = 4;
 277       }
 278    }
 279
 280    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 281
 282    switch (cpp) {
 283    case 1:
 284    case 2:
 285       CMD = XY_SRC_COPY_BLT_CMD;
 286       break;
 287    case 4:
 288       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 289       break;
 290    default:
 291       return false;
 292    }
 293
 294    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 295       return true;
 296    }
 297
 298    assert(dst_x < dst_x2);
 299    assert(dst_y < dst_y2);
 300
 301    BEGIN_BATCH(8);
 302
 303    OUT_BATCH(CMD | (8 - 2));
 304    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 305    OUT_BATCH((dst_y << 16) | dst_x);
 306    OUT_BATCH((dst_y2 << 16) | dst_x2);
 307    OUT_RELOC_FENCED(dst_buffer,
 308                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 309                     dst_offset);
 310    OUT_BATCH((src_y << 16) | src_x);
 311    OUT_BATCH((uint16_t)src_pitch);
 312    OUT_RELOC_FENCED(src_buffer,
 313                     I915_GEM_DOMAIN_RENDER, 0,
 314                     src_offset);
 315
 316    ADVANCE_BATCH();
 317
 318    intel_batchbuffer_emit_mi_flush(intel);
 319
 320    return true;
 321 }
 322
 323
 324 /**
 325  * Use blitting to clear the renderbuffers named by 'flags'.
 326  * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
 327  * since that might include software renderbuffers or renderbuffers
 328  * which we're clearing with triangles.
 329  * \param mask  bitmask of BUFFER_BIT_* values indicating buffers to clear
 330  */
 331 GLbitfield
 332 intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
 333 {
 334    struct intel_context *intel = intel_context(ctx);
 335    struct gl_framebuffer *fb = ctx->DrawBuffer;
 336    GLuint clear_depth_value, clear_depth_mask;
 337    GLint cx, cy, cw, ch;
 338    GLbitfield fail_mask = 0;
 339    BATCH_LOCALS;
 340
 341    /* Note: we don't use this function on Gen7+ hardware, so we can safely
 342     * ignore fast color clear issues.
 343     */
 344    assert(intel->gen < 7);
 345
 346    /*
 347     * Compute values for clearing the buffers.
 348     */
 349    clear_depth_value = 0;
 350    clear_depth_mask = 0;
 351    if (mask & BUFFER_BIT_DEPTH) {
 352       clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
 353       clear_depth_mask = XY_BLT_WRITE_RGB;
 354    }
 355    if (mask & BUFFER_BIT_STENCIL) {
 356       clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24;
 357       clear_depth_mask |= XY_BLT_WRITE_ALPHA;
 358    }
 359
 360    cx = fb->_Xmin;
 361    if (_mesa_is_winsys_fbo(fb))
 362       cy = ctx->DrawBuffer->Height - fb->_Ymax;
 363    else
 364       cy = fb->_Ymin;
 365    cw = fb->_Xmax - fb->_Xmin;
 366    ch = fb->_Ymax - fb->_Ymin;
 367
 368    if (cw == 0 || ch == 0)
 369       return 0;
 370
 371    /* Loop over all renderbuffers */
 372    mask &= (1 << BUFFER_COUNT) - 1;
 373    while (mask) {
 374       GLuint buf = ffs(mask) - 1;
 375       bool is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL;
 376       struct intel_renderbuffer *irb;
 377       int x1, y1, x2, y2;
 378       uint32_t clear_val;
 379       uint32_t BR13, CMD;
 380       struct intel_region *region;
 381       int pitch, cpp;
 382       drm_intel_bo *aper_array[2];
 383
 384       mask &= ~(1 << buf);
 385
 386       irb = intel_get_renderbuffer(fb, buf);
 387       if (irb && irb->mt) {
 388          region = irb->mt->region;
 389          assert(region);
 390          assert(region->bo);
 391       } else {
 392          fail_mask |= 1 << buf;
 393          continue;
 394       }
 395
 396       /* OK, clear this renderbuffer */
 397       x1 = cx + irb->draw_x;
 398       y1 = cy + irb->draw_y;
 399       x2 = cx + cw + irb->draw_x;
 400       y2 = cy + ch + irb->draw_y;
 401
 402       pitch = region->pitch;
 403       cpp = region->cpp;
 404
 405       DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 406           __func__,
 407           region->bo, pitch,
 408           x1, y1, x2 - x1, y2 - y1);
 409
 410       BR13 = 0xf0 << 16;
 411       CMD = XY_COLOR_BLT_CMD;
 412
 413       /* Setup the blit command */
 414       if (cpp == 4) {
 415          if (is_depth_stencil) {
 416             CMD |= clear_depth_mask;
 417          } else {
 418             /* clearing RGBA */
 419             CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 420          }
 421       }
 422
 423       assert(region->tiling != I915_TILING_Y);
 424
 425       BR13 |= pitch;
 426
 427       if (is_depth_stencil) {
 428          clear_val = clear_depth_value;
 429       } else {
 430          uint8_t clear[4];
 431          GLfloat *color = ctx->Color.ClearColor.f;
 432
 433          _mesa_unclamped_float_rgba_to_ubyte(clear, color);
 434
 435          switch (intel_rb_format(irb)) {
 436          case MESA_FORMAT_B8G8R8A8_UNORM:
 437          case MESA_FORMAT_B8G8R8X8_UNORM:
 438             clear_val = PACK_COLOR_8888(clear[3], clear[0],
 439                                         clear[1], clear[2]);
 440             break;
 441          case MESA_FORMAT_B5G6R5_UNORM:
 442             clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
 443             break;
 444          case MESA_FORMAT_B4G4R4A4_UNORM:
 445             clear_val = PACK_COLOR_4444(clear[3], clear[0],
 446                                         clear[1], clear[2]);
 447             break;
 448          case MESA_FORMAT_B5G5R5A1_UNORM:
 449             clear_val = PACK_COLOR_1555(clear[3], clear[0],
 450                                         clear[1], clear[2]);
 451             break;
 452          case MESA_FORMAT_A_UNORM8:
 453             clear_val = PACK_COLOR_8888(clear[3], clear[3],
 454                                         clear[3], clear[3]);
 455             break;
 456          default:
 457             fail_mask |= 1 << buf;
 458             continue;
 459          }
 460       }
 461
 462       BR13 |= br13_for_cpp(cpp);
 463
 464       assert(x1 < x2);
 465       assert(y1 < y2);
 466
 467       /* do space check before going any further */
 468       aper_array[0] = intel->batch.bo;
 469       aper_array[1] = region->bo;
 470
 471       if (drm_intel_bufmgr_check_aperture_space(aper_array,
 472                                                 ARRAY_SIZE(aper_array)) != 0) {
 473          intel_batchbuffer_flush(intel);
 474       }
 475
 476       BEGIN_BATCH(6);
 477       OUT_BATCH(CMD | (6 - 2));
 478       OUT_BATCH(BR13);
 479       OUT_BATCH((y1 << 16) | x1);
 480       OUT_BATCH((y2 << 16) | x2);
 481       OUT_RELOC_FENCED(region->bo,
 482                        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 483                        0);
 484       OUT_BATCH(clear_val);
 485       ADVANCE_BATCH();
 486
 487       if (intel->always_flush_cache)
 488          intel_batchbuffer_emit_mi_flush(intel);
 489
 490       if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
 491          mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
 492    }
 493
 494    return fail_mask;
 495 }
 496
 497 bool
 498 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 499                                   GLuint cpp,
 500                                   GLubyte *src_bits, GLuint src_size,
 501                                   GLuint fg_color,
 502                                   GLshort dst_pitch,
 503                                   drm_intel_bo *dst_buffer,
 504                                   GLuint dst_offset,
 505                                   uint32_t dst_tiling,
 506                                   GLshort x, GLshort y,
 507                                   GLshort w, GLshort h,
 508                                   enum gl_logicop_mode logic_op)
 509 {
 510    int dwords = ALIGN(src_size, 8) / 4;
 511    uint32_t opcode, br13, blit_cmd;
 512
 513    if (dst_tiling != I915_TILING_NONE) {
 514       if (dst_offset & 4095)
 515          return false;
 516       if (dst_tiling == I915_TILING_Y)
 517          return false;
 518    }
 519
 520    assert((unsigned)logic_op <= 0x0f);
 521    assert(dst_pitch > 0);
 522
 523    if (w < 0 || h < 0)
 524       return true;
 525
 526    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 527        __func__,
 528        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 529
 530    intel_batchbuffer_require_space(intel,
 531                                    (8 * 4) +
 532                                    (3 * 4) +
 533                                    dwords * 4);
 534
 535    opcode = XY_SETUP_BLT_CMD;
 536    if (cpp == 4)
 537       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 538
 539    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 540    br13 |= br13_for_cpp(cpp);
 541
 542    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 543    if (dst_tiling != I915_TILING_NONE)
 544       blit_cmd |= XY_DST_TILED;
 545
 546    BEGIN_BATCH(8 + 3);
 547    OUT_BATCH(opcode | (8 - 2));
 548    OUT_BATCH(br13);
 549    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 550    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 551    OUT_RELOC_FENCED(dst_buffer,
 552                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 553                     dst_offset);
 554    OUT_BATCH(0); /* bg */
 555    OUT_BATCH(fg_color); /* fg */
 556    OUT_BATCH(0); /* pattern base addr */
 557
 558    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 559    OUT_BATCH((y << 16) | x);
 560    OUT_BATCH(((y + h) << 16) | (x + w));
 561    ADVANCE_BATCH();
 562
 563    intel_batchbuffer_data(intel, src_bits, dwords * 4);
 564
 565    intel_batchbuffer_emit_mi_flush(intel);
 566
 567    return true;
 568 }
 569
 570 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 571  * rectangular blit covering a large space, then emit 1-scanline blit at the
 572  * end to cover the last if we need.
 573  */
 574 void
 575 intel_emit_linear_blit(struct intel_context *intel,
 576                        drm_intel_bo *dst_bo,
 577                        unsigned int dst_offset,
 578                        drm_intel_bo *src_bo,
 579                        unsigned int src_offset,
 580                        unsigned int size)
 581 {
 582    struct gl_context *ctx = &intel->ctx;
 583    GLuint pitch, height;
 584    bool ok;
 585
 586    /* The pitch given to the GPU must be DWORD aligned, and
 587     * we want width to match pitch. Max width is (1 << 15 - 1),
 588     * rounding that down to the nearest DWORD is 1 << 15 - 4
 589     */
 590    pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
 591    height = (pitch == 0) ? 1 : size / pitch;
 592    ok = intelEmitCopyBlit(intel, 1,
 593                           pitch, src_bo, src_offset, I915_TILING_NONE,
 594                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 595                           0, 0, /* src x/y */
 596                           0, 0, /* dst x/y */
 597                           pitch, height, /* w, h */
 598                           COLOR_LOGICOP_COPY);
 599    if (!ok)
 600       _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
 601
 602    src_offset += pitch * height;
 603    dst_offset += pitch * height;
 604    size -= pitch * height;
 605    assert (size < (1 << 15));
 606    pitch = ALIGN(size, 4);
 607    if (size != 0) {
 608       ok = intelEmitCopyBlit(intel, 1,
 609                              pitch, src_bo, src_offset, I915_TILING_NONE,
 610                              pitch, dst_bo, dst_offset, I915_TILING_NONE,
 611                              0, 0, /* src x/y */
 612                              0, 0, /* dst x/y */
 613                              size, 1, /* w, h */
 614                              COLOR_LOGICOP_COPY);
 615       if (!ok)
 616          _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
 617    }
 618 }
 619
 620 /**
 621  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 622  * into it from an XRGB8888 source.
 623  *
 624  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 625  * relative to the start of the miptree, not relative to a slice within the
 626  * miptree.
 627  */
 628 static void
 629 intel_miptree_set_alpha_to_one(struct intel_context *intel,
 630                               struct intel_mipmap_tree *mt,
 631                               int x, int y, int width, int height)
 632 {
 633    struct intel_region *region = mt->region;
 634    uint32_t BR13, CMD;
 635    int pitch, cpp;
 636    drm_intel_bo *aper_array[2];
 637    BATCH_LOCALS;
 638
 639    pitch = region->pitch;
 640    cpp = region->cpp;
 641
 642    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 643        __func__, region->bo, pitch, x, y, width, height);
 644
 645    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 646    CMD = XY_COLOR_BLT_CMD;
 647    CMD |= XY_BLT_WRITE_ALPHA;
 648
 649    BR13 |= pitch;
 650
 651    /* do space check before going any further */
 652    aper_array[0] = intel->batch.bo;
 653    aper_array[1] = region->bo;
 654
 655    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 656                                              ARRAY_SIZE(aper_array)) != 0) {
 657       intel_batchbuffer_flush(intel);
 658    }
 659
 660    BEGIN_BATCH(6);
 661    OUT_BATCH(CMD | (6 - 2));
 662    OUT_BATCH(BR13);
 663    OUT_BATCH((y << 16) | x);
 664    OUT_BATCH(((y + height) << 16) | (x + width));
 665    OUT_RELOC_FENCED(region->bo,
 666                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 667                     0);
 668    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 669    ADVANCE_BATCH();
 670
 671    intel_batchbuffer_emit_mi_flush(intel);
 672 }