src/mesa/drivers/dri/i915/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33 #include "main/fbobject.h"
  34
  35 #include "intel_blit.h"
  36 #include "intel_buffers.h"
  37 #include "intel_context.h"
  38 #include "intel_fbo.h"
  39 #include "intel_reg.h"
  40 #include "intel_regions.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_mipmap_tree.h"
  43
  44 #define FILE_DEBUG_FLAG DEBUG_BLIT
  45
  46 static void
  47 intel_miptree_set_alpha_to_one(struct intel_context *intel,
  48                                struct intel_mipmap_tree *mt,
  49                                int x, int y, int width, int height);
  50
  51 static GLuint translate_raster_op(GLenum logicop)
  52 {
  53    switch(logicop) {
  54    case GL_CLEAR: return 0x00;
  55    case GL_AND: return 0x88;
  56    case GL_AND_REVERSE: return 0x44;
  57    case GL_COPY: return 0xCC;
  58    case GL_AND_INVERTED: return 0x22;
  59    case GL_NOOP: return 0xAA;
  60    case GL_XOR: return 0x66;
  61    case GL_OR: return 0xEE;
  62    case GL_NOR: return 0x11;
  63    case GL_EQUIV: return 0x99;
  64    case GL_INVERT: return 0x55;
  65    case GL_OR_REVERSE: return 0xDD;
  66    case GL_COPY_INVERTED: return 0x33;
  67    case GL_OR_INVERTED: return 0xBB;
  68    case GL_NAND: return 0x77;
  69    case GL_SET: return 0xFF;
  70    default: return 0;
  71    }
  72 }
  73
  74 static uint32_t
  75 br13_for_cpp(int cpp)
  76 {
  77    switch (cpp) {
  78    case 4:
  79       return BR13_8888;
  80       break;
  81    case 2:
  82       return BR13_565;
  83       break;
  84    case 1:
  85       return BR13_8;
  86       break;
  87    default:
  88       assert(0);
  89       return 0;
  90    }
  91 }
  92
  93 /**
  94  * Emits the packet for switching the blitter from X to Y tiled or back.
  95  *
  96  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
  97  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
  98  * part of the power context, not a render context, and if the batchbuffer was
  99  * to get flushed between setting and blitting, or blitting and restoring, our
 100  * tiling state would leak into other unsuspecting applications (like the X
 101  * server).
 102  */
 103 static void
 104 set_blitter_tiling(struct intel_context *intel,
 105                    bool dst_y_tiled, bool src_y_tiled)
 106 {
 107    assert(intel->gen >= 6);
 108
 109    /* Idle the blitter before we update how tiling is interpreted. */
 110    OUT_BATCH(MI_FLUSH_DW);
 111    OUT_BATCH(0);
 112    OUT_BATCH(0);
 113    OUT_BATCH(0);
 114
 115    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 116    OUT_BATCH(BCS_SWCTRL);
 117    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 118              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 119              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 120 }
 121
 122 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do {         \
 123       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 124       if (dst_y_tiled || src_y_tiled)                                   \
 125          set_blitter_tiling(intel, dst_y_tiled, src_y_tiled);           \
 126    } while (0)
 127
 128 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do {              \
 129       if (dst_y_tiled || src_y_tiled)                                   \
 130          set_blitter_tiling(intel, false, false);                       \
 131       ADVANCE_BATCH();                                                  \
 132    } while (0)
 133
 134 /**
 135  * Implements a rectangular block transfer (blit) of pixels between two
 136  * miptrees.
 137  *
 138  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 139  * but limited, pitches and sizes allowed.
 140  *
 141  * The src/dst coordinates are relative to the given level/slice of the
 142  * miptree.
 143  *
 144  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 145  * will be inverted (including scanline order) when copying.  This is common
 146  * in GL when copying between window system and user-created
 147  * renderbuffers/textures.
 148  */
 149 bool
 150 intel_miptree_blit(struct intel_context *intel,
 151                    struct intel_mipmap_tree *src_mt,
 152                    int src_level, int src_slice,
 153                    uint32_t src_x, uint32_t src_y, bool src_flip,
 154                    struct intel_mipmap_tree *dst_mt,
 155                    int dst_level, int dst_slice,
 156                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 157                    uint32_t width, uint32_t height,
 158                    GLenum logicop)
 159 {
 160    /* No sRGB decode or encode is done by the hardware blitter, which is
 161     * consistent with what we want in the callers (glCopyTexSubImage(),
 162     * glBlitFramebuffer(), texture validation, etc.).
 163     */
 164    gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 165    gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 166
 167    /* The blitter doesn't support doing any format conversions.  We do also
 168     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 169     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 170     * channel to 1.0 at the end.
 171     */
 172    if (src_format != dst_format &&
 173       ((src_format != MESA_FORMAT_ARGB8888 &&
 174         src_format != MESA_FORMAT_XRGB8888) ||
 175        (dst_format != MESA_FORMAT_ARGB8888 &&
 176         dst_format != MESA_FORMAT_XRGB8888))) {
 177       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 178                  "falling back.\n", __FUNCTION__,
 179                  _mesa_get_format_name(src_format),
 180                  _mesa_get_format_name(dst_format));
 181       return false;
 182    }
 183
 184    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 185     * Data Size Limitations):
 186     *
 187     *    The BLT engine is capable of transferring very large quantities of
 188     *    graphics data. Any graphics data read from and written to the
 189     *    destination is permitted to represent a number of pixels that
 190     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 191     *    at the destination. The maximum number of pixels that may be
 192     *    represented per scan line’s worth of graphics data depends on the
 193     *    color depth.
 194     *
 195     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 196     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 197     * pitches < 32k.
 198     *
 199     * As a result of these two limitations, we can only use the blitter to do
 200     * this copy when the region's pitch is less than 32k.
 201     */
 202    if (src_mt->region->pitch > 32768 ||
 203        dst_mt->region->pitch > 32768) {
 204       perf_debug("Falling back due to >32k pitch\n");
 205       return false;
 206    }
 207
 208    if (src_flip)
 209       src_y = src_mt->level[src_level].height - src_y - height;
 210
 211    if (dst_flip)
 212       dst_y = dst_mt->level[dst_level].height - dst_y - height;
 213
 214    int src_pitch = src_mt->region->pitch;
 215    if (src_flip != dst_flip)
 216       src_pitch = -src_pitch;
 217
 218    uint32_t src_image_x, src_image_y;
 219    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 220                                   &src_image_x, &src_image_y);
 221    src_x += src_image_x;
 222    src_y += src_image_y;
 223
 224    uint32_t dst_image_x, dst_image_y;
 225    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 226                                   &dst_image_x, &dst_image_y);
 227    dst_x += dst_image_x;
 228    dst_y += dst_image_y;
 229
 230    if (!intelEmitCopyBlit(intel,
 231                           src_mt->cpp,
 232                           src_pitch,
 233                           src_mt->region->bo, src_mt->offset,
 234                           src_mt->region->tiling,
 235                           dst_mt->region->pitch,
 236                           dst_mt->region->bo, dst_mt->offset,
 237                           dst_mt->region->tiling,
 238                           src_x, src_y,
 239                           dst_x, dst_y,
 240                           width, height,
 241                           logicop)) {
 242       return false;
 243    }
 244
 245    if (src_mt->format == MESA_FORMAT_XRGB8888 &&
 246        dst_mt->format == MESA_FORMAT_ARGB8888) {
 247       intel_miptree_set_alpha_to_one(intel, dst_mt,
 248                                      dst_x, dst_y,
 249                                      width, height);
 250    }
 251
 252    return true;
 253 }
 254
 255 /* Copy BitBlt
 256  */
 257 bool
 258 intelEmitCopyBlit(struct intel_context *intel,
 259                   GLuint cpp,
 260                   GLshort src_pitch,
 261                   drm_intel_bo *src_buffer,
 262                   GLuint src_offset,
 263                   uint32_t src_tiling,
 264                   GLshort dst_pitch,
 265                   drm_intel_bo *dst_buffer,
 266                   GLuint dst_offset,
 267                   uint32_t dst_tiling,
 268                   GLshort src_x, GLshort src_y,
 269                   GLshort dst_x, GLshort dst_y,
 270                   GLshort w, GLshort h,
 271                   GLenum logic_op)
 272 {
 273    GLuint CMD, BR13, pass = 0;
 274    int dst_y2 = dst_y + h;
 275    int dst_x2 = dst_x + w;
 276    drm_intel_bo *aper_array[3];
 277    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 278    bool src_y_tiled = src_tiling == I915_TILING_Y;
 279    BATCH_LOCALS;
 280
 281    if (dst_tiling != I915_TILING_NONE) {
 282       if (dst_offset & 4095)
 283          return false;
 284    }
 285    if (src_tiling != I915_TILING_NONE) {
 286       if (src_offset & 4095)
 287          return false;
 288    }
 289    if ((dst_y_tiled || src_y_tiled) && intel->gen < 6)
 290       return false;
 291
 292    /* do space check before going any further */
 293    do {
 294        aper_array[0] = intel->batch.bo;
 295        aper_array[1] = dst_buffer;
 296        aper_array[2] = src_buffer;
 297
 298        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 299            intel_batchbuffer_flush(intel);
 300            pass++;
 301        } else
 302            break;
 303    } while (pass < 2);
 304
 305    if (pass >= 2)
 306       return false;
 307
 308    intel_batchbuffer_require_space(intel, 8 * 4, true);
 309    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 310        __FUNCTION__,
 311        src_buffer, src_pitch, src_offset, src_x, src_y,
 312        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 313
 314    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 315     * the low bits.
 316     */
 317    if (src_pitch % 4 != 0 || dst_pitch % 4 != 0)
 318       return false;
 319
 320    /* For big formats (such as floating point), do the copy using 16 or 32bpp
 321     * and multiply the coordinates.
 322     */
 323    if (cpp > 4) {
 324       if (cpp % 4 == 2) {
 325          dst_x *= cpp / 2;
 326          dst_x2 *= cpp / 2;
 327          src_x *= cpp / 2;
 328          cpp = 2;
 329       } else {
 330          assert(cpp % 4 == 0);
 331          dst_x *= cpp / 4;
 332          dst_x2 *= cpp / 4;
 333          src_x *= cpp / 4;
 334          cpp = 4;
 335       }
 336    }
 337
 338    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 339
 340    switch (cpp) {
 341    case 1:
 342    case 2:
 343       CMD = XY_SRC_COPY_BLT_CMD;
 344       break;
 345    case 4:
 346       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 347       break;
 348    default:
 349       return false;
 350    }
 351
 352    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 353       return true;
 354    }
 355
 356    assert(dst_x < dst_x2);
 357    assert(dst_y < dst_y2);
 358
 359    BEGIN_BATCH_BLT_TILED(8, dst_y_tiled, src_y_tiled);
 360
 361    OUT_BATCH(CMD | (8 - 2));
 362    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 363    OUT_BATCH((dst_y << 16) | dst_x);
 364    OUT_BATCH((dst_y2 << 16) | dst_x2);
 365    OUT_RELOC_FENCED(dst_buffer,
 366                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 367                     dst_offset);
 368    OUT_BATCH((src_y << 16) | src_x);
 369    OUT_BATCH((uint16_t)src_pitch);
 370    OUT_RELOC_FENCED(src_buffer,
 371                     I915_GEM_DOMAIN_RENDER, 0,
 372                     src_offset);
 373
 374    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 375
 376    intel_batchbuffer_emit_mi_flush(intel);
 377
 378    return true;
 379 }
 380
 381
 382 /**
 383  * Use blitting to clear the renderbuffers named by 'flags'.
 384  * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
 385  * since that might include software renderbuffers or renderbuffers
 386  * which we're clearing with triangles.
 387  * \param mask  bitmask of BUFFER_BIT_* values indicating buffers to clear
 388  */
 389 GLbitfield
 390 intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
 391 {
 392    struct intel_context *intel = intel_context(ctx);
 393    struct gl_framebuffer *fb = ctx->DrawBuffer;
 394    GLuint clear_depth_value, clear_depth_mask;
 395    GLint cx, cy, cw, ch;
 396    GLbitfield fail_mask = 0;
 397    BATCH_LOCALS;
 398
 399    /* Note: we don't use this function on Gen7+ hardware, so we can safely
 400     * ignore fast color clear issues.
 401     */
 402    assert(intel->gen < 7);
 403
 404    /*
 405     * Compute values for clearing the buffers.
 406     */
 407    clear_depth_value = 0;
 408    clear_depth_mask = 0;
 409    if (mask & BUFFER_BIT_DEPTH) {
 410       clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
 411       clear_depth_mask = XY_BLT_WRITE_RGB;
 412    }
 413    if (mask & BUFFER_BIT_STENCIL) {
 414       clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24;
 415       clear_depth_mask |= XY_BLT_WRITE_ALPHA;
 416    }
 417
 418    cx = fb->_Xmin;
 419    if (_mesa_is_winsys_fbo(fb))
 420       cy = ctx->DrawBuffer->Height - fb->_Ymax;
 421    else
 422       cy = fb->_Ymin;
 423    cw = fb->_Xmax - fb->_Xmin;
 424    ch = fb->_Ymax - fb->_Ymin;
 425
 426    if (cw == 0 || ch == 0)
 427       return 0;
 428
 429    /* Loop over all renderbuffers */
 430    mask &= (1 << BUFFER_COUNT) - 1;
 431    while (mask) {
 432       GLuint buf = ffs(mask) - 1;
 433       bool is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL;
 434       struct intel_renderbuffer *irb;
 435       int x1, y1, x2, y2;
 436       uint32_t clear_val;
 437       uint32_t BR13, CMD;
 438       struct intel_region *region;
 439       int pitch, cpp;
 440       drm_intel_bo *aper_array[2];
 441
 442       mask &= ~(1 << buf);
 443
 444       irb = intel_get_renderbuffer(fb, buf);
 445       if (irb && irb->mt) {
 446          region = irb->mt->region;
 447          assert(region);
 448          assert(region->bo);
 449       } else {
 450          fail_mask |= 1 << buf;
 451          continue;
 452       }
 453
 454       /* OK, clear this renderbuffer */
 455       x1 = cx + irb->draw_x;
 456       y1 = cy + irb->draw_y;
 457       x2 = cx + cw + irb->draw_x;
 458       y2 = cy + ch + irb->draw_y;
 459
 460       pitch = region->pitch;
 461       cpp = region->cpp;
 462
 463       DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 464           __FUNCTION__,
 465           region->bo, pitch,
 466           x1, y1, x2 - x1, y2 - y1);
 467
 468       BR13 = 0xf0 << 16;
 469       CMD = XY_COLOR_BLT_CMD;
 470
 471       /* Setup the blit command */
 472       if (cpp == 4) {
 473          if (is_depth_stencil) {
 474             CMD |= clear_depth_mask;
 475          } else {
 476             /* clearing RGBA */
 477             CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 478          }
 479       }
 480
 481       assert(region->tiling != I915_TILING_Y);
 482
 483       BR13 |= pitch;
 484
 485       if (is_depth_stencil) {
 486          clear_val = clear_depth_value;
 487       } else {
 488          uint8_t clear[4];
 489          GLfloat *color = ctx->Color.ClearColor.f;
 490
 491          _mesa_unclamped_float_rgba_to_ubyte(clear, color);
 492
 493          switch (intel_rb_format(irb)) {
 494          case MESA_FORMAT_ARGB8888:
 495          case MESA_FORMAT_XRGB8888:
 496             clear_val = PACK_COLOR_8888(clear[3], clear[0],
 497                                         clear[1], clear[2]);
 498             break;
 499          case MESA_FORMAT_RGB565:
 500             clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
 501             break;
 502          case MESA_FORMAT_ARGB4444:
 503             clear_val = PACK_COLOR_4444(clear[3], clear[0],
 504                                         clear[1], clear[2]);
 505             break;
 506          case MESA_FORMAT_ARGB1555:
 507             clear_val = PACK_COLOR_1555(clear[3], clear[0],
 508                                         clear[1], clear[2]);
 509             break;
 510          case MESA_FORMAT_A8:
 511             clear_val = PACK_COLOR_8888(clear[3], clear[3],
 512                                         clear[3], clear[3]);
 513             break;
 514          default:
 515             fail_mask |= 1 << buf;
 516             continue;
 517          }
 518       }
 519
 520       BR13 |= br13_for_cpp(cpp);
 521
 522       assert(x1 < x2);
 523       assert(y1 < y2);
 524
 525       /* do space check before going any further */
 526       aper_array[0] = intel->batch.bo;
 527       aper_array[1] = region->bo;
 528
 529       if (drm_intel_bufmgr_check_aperture_space(aper_array,
 530                                                 ARRAY_SIZE(aper_array)) != 0) {
 531          intel_batchbuffer_flush(intel);
 532       }
 533
 534       BEGIN_BATCH_BLT(6);
 535       OUT_BATCH(CMD | (6 - 2));
 536       OUT_BATCH(BR13);
 537       OUT_BATCH((y1 << 16) | x1);
 538       OUT_BATCH((y2 << 16) | x2);
 539       OUT_RELOC_FENCED(region->bo,
 540                        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 541                        0);
 542       OUT_BATCH(clear_val);
 543       ADVANCE_BATCH();
 544
 545       if (intel->always_flush_cache)
 546          intel_batchbuffer_emit_mi_flush(intel);
 547
 548       if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
 549          mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
 550    }
 551
 552    return fail_mask;
 553 }
 554
 555 bool
 556 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 557                                   GLuint cpp,
 558                                   GLubyte *src_bits, GLuint src_size,
 559                                   GLuint fg_color,
 560                                   GLshort dst_pitch,
 561                                   drm_intel_bo *dst_buffer,
 562                                   GLuint dst_offset,
 563                                   uint32_t dst_tiling,
 564                                   GLshort x, GLshort y,
 565                                   GLshort w, GLshort h,
 566                                   GLenum logic_op)
 567 {
 568    int dwords = ALIGN(src_size, 8) / 4;
 569    uint32_t opcode, br13, blit_cmd;
 570
 571    if (dst_tiling != I915_TILING_NONE) {
 572       if (dst_offset & 4095)
 573          return false;
 574       if (dst_tiling == I915_TILING_Y)
 575          return false;
 576    }
 577
 578    assert( logic_op - GL_CLEAR >= 0 );
 579    assert( logic_op - GL_CLEAR < 0x10 );
 580    assert(dst_pitch > 0);
 581
 582    if (w < 0 || h < 0)
 583       return true;
 584
 585    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 586        __FUNCTION__,
 587        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 588
 589    intel_batchbuffer_require_space(intel,
 590                                    (8 * 4) +
 591                                    (3 * 4) +
 592                                    dwords * 4, true);
 593
 594    opcode = XY_SETUP_BLT_CMD;
 595    if (cpp == 4)
 596       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 597
 598    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 599    br13 |= br13_for_cpp(cpp);
 600
 601    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 602    if (dst_tiling != I915_TILING_NONE)
 603       blit_cmd |= XY_DST_TILED;
 604
 605    BEGIN_BATCH_BLT(8 + 3);
 606    OUT_BATCH(opcode | (8 - 2));
 607    OUT_BATCH(br13);
 608    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 609    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 610    OUT_RELOC_FENCED(dst_buffer,
 611                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 612                     dst_offset);
 613    OUT_BATCH(0); /* bg */
 614    OUT_BATCH(fg_color); /* fg */
 615    OUT_BATCH(0); /* pattern base addr */
 616
 617    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 618    OUT_BATCH((y << 16) | x);
 619    OUT_BATCH(((y + h) << 16) | (x + w));
 620    ADVANCE_BATCH();
 621
 622    intel_batchbuffer_data(intel, src_bits, dwords * 4, true);
 623
 624    intel_batchbuffer_emit_mi_flush(intel);
 625
 626    return true;
 627 }
 628
 629 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 630  * rectangular blit covering a large space, then emit 1-scanline blit at the
 631  * end to cover the last if we need.
 632  */
 633 void
 634 intel_emit_linear_blit(struct intel_context *intel,
 635                        drm_intel_bo *dst_bo,
 636                        unsigned int dst_offset,
 637                        drm_intel_bo *src_bo,
 638                        unsigned int src_offset,
 639                        unsigned int size)
 640 {
 641    struct gl_context *ctx = &intel->ctx;
 642    GLuint pitch, height;
 643    bool ok;
 644
 645    /* The pitch given to the GPU must be DWORD aligned, and
 646     * we want width to match pitch. Max width is (1 << 15 - 1),
 647     * rounding that down to the nearest DWORD is 1 << 15 - 4
 648     */
 649    pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
 650    height = (pitch == 0) ? 1 : size / pitch;
 651    ok = intelEmitCopyBlit(intel, 1,
 652                           pitch, src_bo, src_offset, I915_TILING_NONE,
 653                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 654                           0, 0, /* src x/y */
 655                           0, 0, /* dst x/y */
 656                           pitch, height, /* w, h */
 657                           GL_COPY);
 658    if (!ok)
 659       _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
 660
 661    src_offset += pitch * height;
 662    dst_offset += pitch * height;
 663    size -= pitch * height;
 664    assert (size < (1 << 15));
 665    pitch = ALIGN(size, 4);
 666    if (size != 0) {
 667       ok = intelEmitCopyBlit(intel, 1,
 668                              pitch, src_bo, src_offset, I915_TILING_NONE,
 669                              pitch, dst_bo, dst_offset, I915_TILING_NONE,
 670                              0, 0, /* src x/y */
 671                              0, 0, /* dst x/y */
 672                              size, 1, /* w, h */
 673                              GL_COPY);
 674       if (!ok)
 675          _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
 676    }
 677 }
 678
 679 /**
 680  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 681  * into it from an XRGB8888 source.
 682  *
 683  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 684  * relative to the start of the miptree, not relative to a slice within the
 685  * miptree.
 686  */
 687 static void
 688 intel_miptree_set_alpha_to_one(struct intel_context *intel,
 689                               struct intel_mipmap_tree *mt,
 690                               int x, int y, int width, int height)
 691 {
 692    struct intel_region *region = mt->region;
 693    uint32_t BR13, CMD;
 694    int pitch, cpp;
 695    drm_intel_bo *aper_array[2];
 696    BATCH_LOCALS;
 697
 698    pitch = region->pitch;
 699    cpp = region->cpp;
 700
 701    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 702        __FUNCTION__, region->bo, pitch, x, y, width, height);
 703
 704    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 705    CMD = XY_COLOR_BLT_CMD;
 706    CMD |= XY_BLT_WRITE_ALPHA;
 707
 708    BR13 |= pitch;
 709
 710    /* do space check before going any further */
 711    aper_array[0] = intel->batch.bo;
 712    aper_array[1] = region->bo;
 713
 714    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 715                                              ARRAY_SIZE(aper_array)) != 0) {
 716       intel_batchbuffer_flush(intel);
 717    }
 718
 719    bool dst_y_tiled = region->tiling == I915_TILING_Y;
 720
 721    BEGIN_BATCH_BLT_TILED(6, dst_y_tiled, false);
 722    OUT_BATCH(CMD | (6 - 2));
 723    OUT_BATCH(BR13);
 724    OUT_BATCH((y << 16) | x);
 725    OUT_BATCH(((y + height) << 16) | (x + width));
 726    OUT_RELOC_FENCED(region->bo,
 727                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 728                     0);
 729    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 730    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 731
 732    intel_batchbuffer_emit_mi_flush(intel);
 733 }