src/mesa/drivers/dri/i915/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33 #include "main/fbobject.h"
  34
  35 #include "intel_blit.h"
  36 #include "intel_buffers.h"
  37 #include "intel_context.h"
  38 #include "intel_fbo.h"
  39 #include "intel_reg.h"
  40 #include "intel_regions.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_mipmap_tree.h"
  43
  44 #define FILE_DEBUG_FLAG DEBUG_BLIT
  45
  46 static void
  47 intel_miptree_set_alpha_to_one(struct intel_context *intel,
  48                                struct intel_mipmap_tree *mt,
  49                                int x, int y, int width, int height);
  50
  51 static GLuint translate_raster_op(enum gl_logicop_mode logicop)
  52 {
  53    return logicop | (logicop << 4);
  54 }
  55
  56 static uint32_t
  57 br13_for_cpp(int cpp)
  58 {
  59    switch (cpp) {
  60    case 4:
  61       return BR13_8888;
  62       break;
  63    case 2:
  64       return BR13_565;
  65       break;
  66    case 1:
  67       return BR13_8;
  68       break;
  69    default:
  70       assert(0);
  71       return 0;
  72    }
  73 }
  74
  75 /* Copy BitBlt
  76  */
  77 static bool
  78 emit_copy_blit(struct intel_context *intel,
  79                GLuint cpp,
  80                GLshort src_pitch,
  81                drm_intel_bo *src_buffer,
  82                GLuint src_offset,
  83                uint32_t src_tiling,
  84                GLshort dst_pitch,
  85                drm_intel_bo *dst_buffer,
  86                GLuint dst_offset,
  87                uint32_t dst_tiling,
  88                GLshort src_x, GLshort src_y,
  89                GLshort dst_x, GLshort dst_y,
  90                GLshort w, GLshort h,
  91                enum gl_logicop_mode logic_op)
  92 {
  93    GLuint CMD, BR13, pass = 0;
  94    int dst_y2 = dst_y + h;
  95    int dst_x2 = dst_x + w;
  96    drm_intel_bo *aper_array[3];
  97    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
  98    bool src_y_tiled = src_tiling == I915_TILING_Y;
  99    BATCH_LOCALS;
 100
 101    if (dst_tiling != I915_TILING_NONE) {
 102       if (dst_offset & 4095)
 103          return false;
 104    }
 105    if (src_tiling != I915_TILING_NONE) {
 106       if (src_offset & 4095)
 107          return false;
 108    }
 109    if (dst_y_tiled || src_y_tiled)
 110       return false;
 111
 112    /* do space check before going any further */
 113    do {
 114        aper_array[0] = intel->batch.bo;
 115        aper_array[1] = dst_buffer;
 116        aper_array[2] = src_buffer;
 117
 118        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 119            intel_batchbuffer_flush(intel);
 120            pass++;
 121        } else
 122            break;
 123    } while (pass < 2);
 124
 125    if (pass >= 2)
 126       return false;
 127
 128    intel_batchbuffer_require_space(intel, 8 * 4);
 129    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 130        __func__,
 131        src_buffer, src_pitch, src_offset, src_x, src_y,
 132        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 133
 134    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 135     * the low bits.  Offsets must be naturally aligned.
 136     */
 137    if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
 138        dst_pitch % 4 != 0 || dst_offset % cpp != 0)
 139       return false;
 140
 141    /* For big formats (such as floating point), do the copy using 16 or 32bpp
 142     * and multiply the coordinates.
 143     */
 144    if (cpp > 4) {
 145       if (cpp % 4 == 2) {
 146          dst_x *= cpp / 2;
 147          dst_x2 *= cpp / 2;
 148          src_x *= cpp / 2;
 149          cpp = 2;
 150       } else {
 151          assert(cpp % 4 == 0);
 152          dst_x *= cpp / 4;
 153          dst_x2 *= cpp / 4;
 154          src_x *= cpp / 4;
 155          cpp = 4;
 156       }
 157    }
 158
 159    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 160
 161    switch (cpp) {
 162    case 1:
 163    case 2:
 164       CMD = XY_SRC_COPY_BLT_CMD;
 165       break;
 166    case 4:
 167       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 168       break;
 169    default:
 170       return false;
 171    }
 172
 173    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 174       return true;
 175    }
 176
 177    assert(dst_x < dst_x2);
 178    assert(dst_y < dst_y2);
 179
 180    BEGIN_BATCH(8);
 181
 182    OUT_BATCH(CMD | (8 - 2));
 183    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 184    OUT_BATCH((dst_y << 16) | dst_x);
 185    OUT_BATCH((dst_y2 << 16) | dst_x2);
 186    OUT_RELOC_FENCED(dst_buffer,
 187                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 188                     dst_offset);
 189    OUT_BATCH((src_y << 16) | src_x);
 190    OUT_BATCH((uint16_t)src_pitch);
 191    OUT_RELOC_FENCED(src_buffer,
 192                     I915_GEM_DOMAIN_RENDER, 0,
 193                     src_offset);
 194
 195    ADVANCE_BATCH();
 196
 197    intel_batchbuffer_emit_mi_flush(intel);
 198
 199    return true;
 200 }
 201
 202 /**
 203  * Implements a rectangular block transfer (blit) of pixels between two
 204  * miptrees.
 205  *
 206  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 207  * but limited, pitches and sizes allowed.
 208  *
 209  * The src/dst coordinates are relative to the given level/slice of the
 210  * miptree.
 211  *
 212  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 213  * will be inverted (including scanline order) when copying.  This is common
 214  * in GL when copying between window system and user-created
 215  * renderbuffers/textures.
 216  */
 217 bool
 218 intel_miptree_blit(struct intel_context *intel,
 219                    struct intel_mipmap_tree *src_mt,
 220                    int src_level, int src_slice,
 221                    uint32_t src_x, uint32_t src_y, bool src_flip,
 222                    struct intel_mipmap_tree *dst_mt,
 223                    int dst_level, int dst_slice,
 224                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 225                    uint32_t width, uint32_t height,
 226                    enum gl_logicop_mode logicop)
 227 {
 228    /* No sRGB decode or encode is done by the hardware blitter, which is
 229     * consistent with what we want in the callers (glCopyTexSubImage(),
 230     * glBlitFramebuffer(), texture validation, etc.).
 231     */
 232    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 233    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 234
 235    /* The blitter doesn't support doing any format conversions.  We do also
 236     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 237     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 238     * channel to 1.0 at the end.
 239     */
 240    if (src_format != dst_format &&
 241       ((src_format != MESA_FORMAT_B8G8R8A8_UNORM &&
 242         src_format != MESA_FORMAT_B8G8R8X8_UNORM) ||
 243        (dst_format != MESA_FORMAT_B8G8R8A8_UNORM &&
 244         dst_format != MESA_FORMAT_B8G8R8X8_UNORM))) {
 245       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 246                  "falling back.\n", __func__,
 247                  _mesa_get_format_name(src_format),
 248                  _mesa_get_format_name(dst_format));
 249       return false;
 250    }
 251
 252    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 253     * Data Size Limitations):
 254     *
 255     *    The BLT engine is capable of transferring very large quantities of
 256     *    graphics data. Any graphics data read from and written to the
 257     *    destination is permitted to represent a number of pixels that
 258     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 259     *    at the destination. The maximum number of pixels that may be
 260     *    represented per scan line’s worth of graphics data depends on the
 261     *    color depth.
 262     *
 263     * Furthermore, emit_copy_blit (which is called below) uses a signed
 264     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 265     * pitches < 32k.
 266     *
 267     * As a result of these two limitations, we can only use the blitter to do
 268     * this copy when the region's pitch is less than 32k.
 269     */
 270    if (src_mt->region->pitch > 32768 ||
 271        dst_mt->region->pitch > 32768) {
 272       perf_debug("Falling back due to >32k pitch\n");
 273       return false;
 274    }
 275
 276    if (src_flip)
 277       src_y = src_mt->level[src_level].height - src_y - height;
 278
 279    if (dst_flip)
 280       dst_y = dst_mt->level[dst_level].height - dst_y - height;
 281
 282    int src_pitch = src_mt->region->pitch;
 283    if (src_flip != dst_flip)
 284       src_pitch = -src_pitch;
 285
 286    uint32_t src_image_x, src_image_y;
 287    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 288                                   &src_image_x, &src_image_y);
 289    src_x += src_image_x;
 290    src_y += src_image_y;
 291
 292    uint32_t dst_image_x, dst_image_y;
 293    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 294                                   &dst_image_x, &dst_image_y);
 295    dst_x += dst_image_x;
 296    dst_y += dst_image_y;
 297
 298    if (!emit_copy_blit(intel,
 299                        src_mt->cpp,
 300                        src_pitch,
 301                        src_mt->region->bo, src_mt->offset,
 302                        src_mt->region->tiling,
 303                        dst_mt->region->pitch,
 304                        dst_mt->region->bo, dst_mt->offset,
 305                        dst_mt->region->tiling,
 306                        src_x, src_y,
 307                        dst_x, dst_y,
 308                        width, height,
 309                        logicop)) {
 310       return false;
 311    }
 312
 313    if (src_mt->format == MESA_FORMAT_B8G8R8X8_UNORM &&
 314        dst_mt->format == MESA_FORMAT_B8G8R8A8_UNORM) {
 315       intel_miptree_set_alpha_to_one(intel, dst_mt,
 316                                      dst_x, dst_y,
 317                                      width, height);
 318    }
 319
 320    return true;
 321 }
 322
 323 /**
 324  * Use blitting to clear the renderbuffers named by 'flags'.
 325  * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
 326  * since that might include software renderbuffers or renderbuffers
 327  * which we're clearing with triangles.
 328  * \param mask  bitmask of BUFFER_BIT_* values indicating buffers to clear
 329  */
 330 GLbitfield
 331 intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
 332 {
 333    struct intel_context *intel = intel_context(ctx);
 334    struct gl_framebuffer *fb = ctx->DrawBuffer;
 335    GLuint clear_depth_value, clear_depth_mask;
 336    GLint cx, cy, cw, ch;
 337    GLbitfield fail_mask = 0;
 338    BATCH_LOCALS;
 339
 340    /* Note: we don't use this function on Gen7+ hardware, so we can safely
 341     * ignore fast color clear issues.
 342     */
 343    assert(intel->gen < 7);
 344
 345    /*
 346     * Compute values for clearing the buffers.
 347     */
 348    clear_depth_value = 0;
 349    clear_depth_mask = 0;
 350    if (mask & BUFFER_BIT_DEPTH) {
 351       clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
 352       clear_depth_mask = XY_BLT_WRITE_RGB;
 353    }
 354    if (mask & BUFFER_BIT_STENCIL) {
 355       clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24;
 356       clear_depth_mask |= XY_BLT_WRITE_ALPHA;
 357    }
 358
 359    cx = fb->_Xmin;
 360    if (_mesa_is_winsys_fbo(fb))
 361       cy = ctx->DrawBuffer->Height - fb->_Ymax;
 362    else
 363       cy = fb->_Ymin;
 364    cw = fb->_Xmax - fb->_Xmin;
 365    ch = fb->_Ymax - fb->_Ymin;
 366
 367    if (cw == 0 || ch == 0)
 368       return 0;
 369
 370    /* Loop over all renderbuffers */
 371    mask &= (1 << BUFFER_COUNT) - 1;
 372    while (mask) {
 373       GLuint buf = ffs(mask) - 1;
 374       bool is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL;
 375       struct intel_renderbuffer *irb;
 376       int x1, y1, x2, y2;
 377       uint32_t clear_val;
 378       uint32_t BR13, CMD;
 379       struct intel_region *region;
 380       int pitch, cpp;
 381       drm_intel_bo *aper_array[2];
 382
 383       mask &= ~(1 << buf);
 384
 385       irb = intel_get_renderbuffer(fb, buf);
 386       if (irb && irb->mt) {
 387          region = irb->mt->region;
 388          assert(region);
 389          assert(region->bo);
 390       } else {
 391          fail_mask |= 1 << buf;
 392          continue;
 393       }
 394
 395       /* OK, clear this renderbuffer */
 396       x1 = cx + irb->draw_x;
 397       y1 = cy + irb->draw_y;
 398       x2 = cx + cw + irb->draw_x;
 399       y2 = cy + ch + irb->draw_y;
 400
 401       pitch = region->pitch;
 402       cpp = region->cpp;
 403
 404       DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 405           __func__,
 406           region->bo, pitch,
 407           x1, y1, x2 - x1, y2 - y1);
 408
 409       BR13 = 0xf0 << 16;
 410       CMD = XY_COLOR_BLT_CMD;
 411
 412       /* Setup the blit command */
 413       if (cpp == 4) {
 414          if (is_depth_stencil) {
 415             CMD |= clear_depth_mask;
 416          } else {
 417             /* clearing RGBA */
 418             CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 419          }
 420       }
 421
 422       assert(region->tiling != I915_TILING_Y);
 423
 424       BR13 |= pitch;
 425
 426       if (is_depth_stencil) {
 427          clear_val = clear_depth_value;
 428       } else {
 429          uint8_t clear[4];
 430          GLfloat *color = ctx->Color.ClearColor.f;
 431
 432          _mesa_unclamped_float_rgba_to_ubyte(clear, color);
 433
 434          switch (intel_rb_format(irb)) {
 435          case MESA_FORMAT_B8G8R8A8_UNORM:
 436          case MESA_FORMAT_B8G8R8X8_UNORM:
 437             clear_val = PACK_COLOR_8888(clear[3], clear[0],
 438                                         clear[1], clear[2]);
 439             break;
 440          case MESA_FORMAT_B5G6R5_UNORM:
 441             clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
 442             break;
 443          case MESA_FORMAT_B4G4R4A4_UNORM:
 444             clear_val = PACK_COLOR_4444(clear[3], clear[0],
 445                                         clear[1], clear[2]);
 446             break;
 447          case MESA_FORMAT_B5G5R5A1_UNORM:
 448             clear_val = PACK_COLOR_1555(clear[3], clear[0],
 449                                         clear[1], clear[2]);
 450             break;
 451          case MESA_FORMAT_A_UNORM8:
 452             clear_val = PACK_COLOR_8888(clear[3], clear[3],
 453                                         clear[3], clear[3]);
 454             break;
 455          default:
 456             fail_mask |= 1 << buf;
 457             continue;
 458          }
 459       }
 460
 461       BR13 |= br13_for_cpp(cpp);
 462
 463       assert(x1 < x2);
 464       assert(y1 < y2);
 465
 466       /* do space check before going any further */
 467       aper_array[0] = intel->batch.bo;
 468       aper_array[1] = region->bo;
 469
 470       if (drm_intel_bufmgr_check_aperture_space(aper_array,
 471                                                 ARRAY_SIZE(aper_array)) != 0) {
 472          intel_batchbuffer_flush(intel);
 473       }
 474
 475       BEGIN_BATCH(6);
 476       OUT_BATCH(CMD | (6 - 2));
 477       OUT_BATCH(BR13);
 478       OUT_BATCH((y1 << 16) | x1);
 479       OUT_BATCH((y2 << 16) | x2);
 480       OUT_RELOC_FENCED(region->bo,
 481                        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 482                        0);
 483       OUT_BATCH(clear_val);
 484       ADVANCE_BATCH();
 485
 486       if (intel->always_flush_cache)
 487          intel_batchbuffer_emit_mi_flush(intel);
 488
 489       if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
 490          mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
 491    }
 492
 493    return fail_mask;
 494 }
 495
 496 bool
 497 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 498                                   GLuint cpp,
 499                                   GLubyte *src_bits, GLuint src_size,
 500                                   GLuint fg_color,
 501                                   GLshort dst_pitch,
 502                                   drm_intel_bo *dst_buffer,
 503                                   GLuint dst_offset,
 504                                   uint32_t dst_tiling,
 505                                   GLshort x, GLshort y,
 506                                   GLshort w, GLshort h,
 507                                   enum gl_logicop_mode logic_op)
 508 {
 509    int dwords = ALIGN(src_size, 8) / 4;
 510    uint32_t opcode, br13, blit_cmd;
 511
 512    if (dst_tiling != I915_TILING_NONE) {
 513       if (dst_offset & 4095)
 514          return false;
 515       if (dst_tiling == I915_TILING_Y)
 516          return false;
 517    }
 518
 519    assert((unsigned)logic_op <= 0x0f);
 520    assert(dst_pitch > 0);
 521
 522    if (w < 0 || h < 0)
 523       return true;
 524
 525    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 526        __func__,
 527        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 528
 529    intel_batchbuffer_require_space(intel,
 530                                    (8 * 4) +
 531                                    (3 * 4) +
 532                                    dwords * 4);
 533
 534    opcode = XY_SETUP_BLT_CMD;
 535    if (cpp == 4)
 536       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 537
 538    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 539    br13 |= br13_for_cpp(cpp);
 540
 541    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 542    if (dst_tiling != I915_TILING_NONE)
 543       blit_cmd |= XY_DST_TILED;
 544
 545    BEGIN_BATCH(8 + 3);
 546    OUT_BATCH(opcode | (8 - 2));
 547    OUT_BATCH(br13);
 548    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 549    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 550    OUT_RELOC_FENCED(dst_buffer,
 551                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 552                     dst_offset);
 553    OUT_BATCH(0); /* bg */
 554    OUT_BATCH(fg_color); /* fg */
 555    OUT_BATCH(0); /* pattern base addr */
 556
 557    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 558    OUT_BATCH((y << 16) | x);
 559    OUT_BATCH(((y + h) << 16) | (x + w));
 560    ADVANCE_BATCH();
 561
 562    intel_batchbuffer_data(intel, src_bits, dwords * 4);
 563
 564    intel_batchbuffer_emit_mi_flush(intel);
 565
 566    return true;
 567 }
 568
 569 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 570  * rectangular blit covering a large space, then emit 1-scanline blit at the
 571  * end to cover the last if we need.
 572  */
 573 void
 574 intel_emit_linear_blit(struct intel_context *intel,
 575                        drm_intel_bo *dst_bo,
 576                        unsigned int dst_offset,
 577                        drm_intel_bo *src_bo,
 578                        unsigned int src_offset,
 579                        unsigned int size)
 580 {
 581    struct gl_context *ctx = &intel->ctx;
 582    GLuint pitch, height;
 583    bool ok;
 584
 585    /* The pitch given to the GPU must be DWORD aligned, and
 586     * we want width to match pitch. Max width is (1 << 15 - 1),
 587     * rounding that down to the nearest DWORD is 1 << 15 - 4
 588     */
 589    pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
 590    height = (pitch == 0) ? 1 : size / pitch;
 591    ok = emit_copy_blit(intel, 1,
 592                        pitch, src_bo, src_offset, I915_TILING_NONE,
 593                        pitch, dst_bo, dst_offset, I915_TILING_NONE,
 594                        0, 0, /* src x/y */
 595                        0, 0, /* dst x/y */
 596                        pitch, height, /* w, h */
 597                        COLOR_LOGICOP_COPY);
 598    if (!ok)
 599       _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
 600
 601    src_offset += pitch * height;
 602    dst_offset += pitch * height;
 603    size -= pitch * height;
 604    assert (size < (1 << 15));
 605    pitch = ALIGN(size, 4);
 606    if (size != 0) {
 607       ok = emit_copy_blit(intel, 1,
 608                           pitch, src_bo, src_offset, I915_TILING_NONE,
 609                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 610                           0, 0, /* src x/y */
 611                           0, 0, /* dst x/y */
 612                           size, 1, /* w, h */
 613                           COLOR_LOGICOP_COPY);
 614       if (!ok)
 615          _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
 616    }
 617 }
 618
 619 /**
 620  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 621  * into it from an XRGB8888 source.
 622  *
 623  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 624  * relative to the start of the miptree, not relative to a slice within the
 625  * miptree.
 626  */
 627 static void
 628 intel_miptree_set_alpha_to_one(struct intel_context *intel,
 629                               struct intel_mipmap_tree *mt,
 630                               int x, int y, int width, int height)
 631 {
 632    struct intel_region *region = mt->region;
 633    uint32_t BR13, CMD;
 634    int pitch, cpp;
 635    drm_intel_bo *aper_array[2];
 636    BATCH_LOCALS;
 637
 638    pitch = region->pitch;
 639    cpp = region->cpp;
 640
 641    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 642        __func__, region->bo, pitch, x, y, width, height);
 643
 644    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 645    CMD = XY_COLOR_BLT_CMD;
 646    CMD |= XY_BLT_WRITE_ALPHA;
 647
 648    BR13 |= pitch;
 649
 650    /* do space check before going any further */
 651    aper_array[0] = intel->batch.bo;
 652    aper_array[1] = region->bo;
 653
 654    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 655                                              ARRAY_SIZE(aper_array)) != 0) {
 656       intel_batchbuffer_flush(intel);
 657    }
 658
 659    BEGIN_BATCH(6);
 660    OUT_BATCH(CMD | (6 - 2));
 661    OUT_BATCH(BR13);
 662    OUT_BATCH((y << 16) | x);
 663    OUT_BATCH(((y + height) << 16) | (x + width));
 664    OUT_RELOC_FENCED(region->bo,
 665                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 666                     0);
 667    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 668    ADVANCE_BATCH();
 669
 670    intel_batchbuffer_emit_mi_flush(intel);
 671 }