1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/mtypes.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/colormac.h"
33 #include "main/fbobject.h"
35 #include "intel_blit.h"
36 #include "intel_buffers.h"
37 #include "intel_context.h"
38 #include "intel_fbo.h"
39 #include "intel_reg.h"
40 #include "intel_regions.h"
41 #include "intel_batchbuffer.h"
42 #include "intel_mipmap_tree.h"
44 #define FILE_DEBUG_FLAG DEBUG_BLIT
47 intel_miptree_set_alpha_to_one(struct intel_context
*intel
,
48 struct intel_mipmap_tree
*mt
,
49 int x
, int y
, int width
, int height
);
51 static GLuint
translate_raster_op(GLenum logicop
)
54 case GL_CLEAR
: return 0x00;
55 case GL_AND
: return 0x88;
56 case GL_AND_REVERSE
: return 0x44;
57 case GL_COPY
: return 0xCC;
58 case GL_AND_INVERTED
: return 0x22;
59 case GL_NOOP
: return 0xAA;
60 case GL_XOR
: return 0x66;
61 case GL_OR
: return 0xEE;
62 case GL_NOR
: return 0x11;
63 case GL_EQUIV
: return 0x99;
64 case GL_INVERT
: return 0x55;
65 case GL_OR_REVERSE
: return 0xDD;
66 case GL_COPY_INVERTED
: return 0x33;
67 case GL_OR_INVERTED
: return 0xBB;
68 case GL_NAND
: return 0x77;
69 case GL_SET
: return 0xFF;
94 * Implements a rectangular block transfer (blit) of pixels between two
97 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
98 * but limited, pitches and sizes allowed.
100 * The src/dst coordinates are relative to the given level/slice of the
103 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
104 * will be inverted (including scanline order) when copying. This is common
105 * in GL when copying between window system and user-created
106 * renderbuffers/textures.
109 intel_miptree_blit(struct intel_context
*intel
,
110 struct intel_mipmap_tree
*src_mt
,
111 int src_level
, int src_slice
,
112 uint32_t src_x
, uint32_t src_y
, bool src_flip
,
113 struct intel_mipmap_tree
*dst_mt
,
114 int dst_level
, int dst_slice
,
115 uint32_t dst_x
, uint32_t dst_y
, bool dst_flip
,
116 uint32_t width
, uint32_t height
,
119 /* No sRGB decode or encode is done by the hardware blitter, which is
120 * consistent with what we want in the callers (glCopyTexSubImage(),
121 * glBlitFramebuffer(), texture validation, etc.).
123 mesa_format src_format
= _mesa_get_srgb_format_linear(src_mt
->format
);
124 mesa_format dst_format
= _mesa_get_srgb_format_linear(dst_mt
->format
);
126 /* The blitter doesn't support doing any format conversions. We do also
127 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
128 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
129 * channel to 1.0 at the end.
131 if (src_format
!= dst_format
&&
132 ((src_format
!= MESA_FORMAT_B8G8R8A8_UNORM
&&
133 src_format
!= MESA_FORMAT_B8G8R8X8_UNORM
) ||
134 (dst_format
!= MESA_FORMAT_B8G8R8A8_UNORM
&&
135 dst_format
!= MESA_FORMAT_B8G8R8X8_UNORM
))) {
136 perf_debug("%s: Can't use hardware blitter from %s to %s, "
137 "falling back.\n", __FUNCTION__
,
138 _mesa_get_format_name(src_format
),
139 _mesa_get_format_name(dst_format
));
143 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
144 * Data Size Limitations):
146 * The BLT engine is capable of transferring very large quantities of
147 * graphics data. Any graphics data read from and written to the
148 * destination is permitted to represent a number of pixels that
149 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
150 * at the destination. The maximum number of pixels that may be
151 * represented per scan line’s worth of graphics data depends on the
154 * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
155 * 16-bit integer to represent buffer pitch, so it can only handle buffer
158 * As a result of these two limitations, we can only use the blitter to do
159 * this copy when the region's pitch is less than 32k.
161 if (src_mt
->region
->pitch
> 32768 ||
162 dst_mt
->region
->pitch
> 32768) {
163 perf_debug("Falling back due to >32k pitch\n");
168 src_y
= src_mt
->level
[src_level
].height
- src_y
- height
;
171 dst_y
= dst_mt
->level
[dst_level
].height
- dst_y
- height
;
173 int src_pitch
= src_mt
->region
->pitch
;
174 if (src_flip
!= dst_flip
)
175 src_pitch
= -src_pitch
;
177 uint32_t src_image_x
, src_image_y
;
178 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
179 &src_image_x
, &src_image_y
);
180 src_x
+= src_image_x
;
181 src_y
+= src_image_y
;
183 uint32_t dst_image_x
, dst_image_y
;
184 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
185 &dst_image_x
, &dst_image_y
);
186 dst_x
+= dst_image_x
;
187 dst_y
+= dst_image_y
;
189 if (!intelEmitCopyBlit(intel
,
192 src_mt
->region
->bo
, src_mt
->offset
,
193 src_mt
->region
->tiling
,
194 dst_mt
->region
->pitch
,
195 dst_mt
->region
->bo
, dst_mt
->offset
,
196 dst_mt
->region
->tiling
,
204 if (src_mt
->format
== MESA_FORMAT_B8G8R8X8_UNORM
&&
205 dst_mt
->format
== MESA_FORMAT_B8G8R8A8_UNORM
) {
206 intel_miptree_set_alpha_to_one(intel
, dst_mt
,
217 intelEmitCopyBlit(struct intel_context
*intel
,
220 drm_intel_bo
*src_buffer
,
224 drm_intel_bo
*dst_buffer
,
227 GLshort src_x
, GLshort src_y
,
228 GLshort dst_x
, GLshort dst_y
,
229 GLshort w
, GLshort h
,
232 GLuint CMD
, BR13
, pass
= 0;
233 int dst_y2
= dst_y
+ h
;
234 int dst_x2
= dst_x
+ w
;
235 drm_intel_bo
*aper_array
[3];
236 bool dst_y_tiled
= dst_tiling
== I915_TILING_Y
;
237 bool src_y_tiled
= src_tiling
== I915_TILING_Y
;
240 if (dst_tiling
!= I915_TILING_NONE
) {
241 if (dst_offset
& 4095)
244 if (src_tiling
!= I915_TILING_NONE
) {
245 if (src_offset
& 4095)
248 if (dst_y_tiled
|| src_y_tiled
)
251 /* do space check before going any further */
253 aper_array
[0] = intel
->batch
.bo
;
254 aper_array
[1] = dst_buffer
;
255 aper_array
[2] = src_buffer
;
257 if (dri_bufmgr_check_aperture_space(aper_array
, 3) != 0) {
258 intel_batchbuffer_flush(intel
);
267 intel_batchbuffer_require_space(intel
, 8 * 4);
268 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
270 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
271 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
273 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
276 if (src_pitch
% 4 != 0 || dst_pitch
% 4 != 0)
279 /* For big formats (such as floating point), do the copy using 16 or 32bpp
280 * and multiply the coordinates.
289 assert(cpp
% 4 == 0);
297 BR13
= br13_for_cpp(cpp
) | translate_raster_op(logic_op
) << 16;
302 CMD
= XY_SRC_COPY_BLT_CMD
;
305 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
311 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
) {
315 assert(dst_x
< dst_x2
);
316 assert(dst_y
< dst_y2
);
320 OUT_BATCH(CMD
| (8 - 2));
321 OUT_BATCH(BR13
| (uint16_t)dst_pitch
);
322 OUT_BATCH((dst_y
<< 16) | dst_x
);
323 OUT_BATCH((dst_y2
<< 16) | dst_x2
);
324 OUT_RELOC_FENCED(dst_buffer
,
325 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
327 OUT_BATCH((src_y
<< 16) | src_x
);
328 OUT_BATCH((uint16_t)src_pitch
);
329 OUT_RELOC_FENCED(src_buffer
,
330 I915_GEM_DOMAIN_RENDER
, 0,
335 intel_batchbuffer_emit_mi_flush(intel
);
342 * Use blitting to clear the renderbuffers named by 'flags'.
343 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
344 * since that might include software renderbuffers or renderbuffers
345 * which we're clearing with triangles.
346 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
349 intelClearWithBlit(struct gl_context
*ctx
, GLbitfield mask
)
351 struct intel_context
*intel
= intel_context(ctx
);
352 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
353 GLuint clear_depth_value
, clear_depth_mask
;
354 GLint cx
, cy
, cw
, ch
;
355 GLbitfield fail_mask
= 0;
358 /* Note: we don't use this function on Gen7+ hardware, so we can safely
359 * ignore fast color clear issues.
361 assert(intel
->gen
< 7);
364 * Compute values for clearing the buffers.
366 clear_depth_value
= 0;
367 clear_depth_mask
= 0;
368 if (mask
& BUFFER_BIT_DEPTH
) {
369 clear_depth_value
= (GLuint
) (fb
->_DepthMax
* ctx
->Depth
.Clear
);
370 clear_depth_mask
= XY_BLT_WRITE_RGB
;
372 if (mask
& BUFFER_BIT_STENCIL
) {
373 clear_depth_value
|= (ctx
->Stencil
.Clear
& 0xff) << 24;
374 clear_depth_mask
|= XY_BLT_WRITE_ALPHA
;
378 if (_mesa_is_winsys_fbo(fb
))
379 cy
= ctx
->DrawBuffer
->Height
- fb
->_Ymax
;
382 cw
= fb
->_Xmax
- fb
->_Xmin
;
383 ch
= fb
->_Ymax
- fb
->_Ymin
;
385 if (cw
== 0 || ch
== 0)
388 /* Loop over all renderbuffers */
389 mask
&= (1 << BUFFER_COUNT
) - 1;
391 GLuint buf
= ffs(mask
) - 1;
392 bool is_depth_stencil
= buf
== BUFFER_DEPTH
|| buf
== BUFFER_STENCIL
;
393 struct intel_renderbuffer
*irb
;
397 struct intel_region
*region
;
399 drm_intel_bo
*aper_array
[2];
403 irb
= intel_get_renderbuffer(fb
, buf
);
404 if (irb
&& irb
->mt
) {
405 region
= irb
->mt
->region
;
409 fail_mask
|= 1 << buf
;
413 /* OK, clear this renderbuffer */
414 x1
= cx
+ irb
->draw_x
;
415 y1
= cy
+ irb
->draw_y
;
416 x2
= cx
+ cw
+ irb
->draw_x
;
417 y2
= cy
+ ch
+ irb
->draw_y
;
419 pitch
= region
->pitch
;
422 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
425 x1
, y1
, x2
- x1
, y2
- y1
);
428 CMD
= XY_COLOR_BLT_CMD
;
430 /* Setup the blit command */
432 if (is_depth_stencil
) {
433 CMD
|= clear_depth_mask
;
436 CMD
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
440 assert(region
->tiling
!= I915_TILING_Y
);
444 if (is_depth_stencil
) {
445 clear_val
= clear_depth_value
;
448 GLfloat
*color
= ctx
->Color
.ClearColor
.f
;
450 _mesa_unclamped_float_rgba_to_ubyte(clear
, color
);
452 switch (intel_rb_format(irb
)) {
453 case MESA_FORMAT_B8G8R8A8_UNORM
:
454 case MESA_FORMAT_B8G8R8X8_UNORM
:
455 clear_val
= PACK_COLOR_8888(clear
[3], clear
[0],
458 case MESA_FORMAT_B5G6R5_UNORM
:
459 clear_val
= PACK_COLOR_565(clear
[0], clear
[1], clear
[2]);
461 case MESA_FORMAT_B4G4R4A4_UNORM
:
462 clear_val
= PACK_COLOR_4444(clear
[3], clear
[0],
465 case MESA_FORMAT_B5G5R5A1_UNORM
:
466 clear_val
= PACK_COLOR_1555(clear
[3], clear
[0],
469 case MESA_FORMAT_A_UNORM8
:
470 clear_val
= PACK_COLOR_8888(clear
[3], clear
[3],
474 fail_mask
|= 1 << buf
;
479 BR13
|= br13_for_cpp(cpp
);
484 /* do space check before going any further */
485 aper_array
[0] = intel
->batch
.bo
;
486 aper_array
[1] = region
->bo
;
488 if (drm_intel_bufmgr_check_aperture_space(aper_array
,
489 ARRAY_SIZE(aper_array
)) != 0) {
490 intel_batchbuffer_flush(intel
);
494 OUT_BATCH(CMD
| (6 - 2));
496 OUT_BATCH((y1
<< 16) | x1
);
497 OUT_BATCH((y2
<< 16) | x2
);
498 OUT_RELOC_FENCED(region
->bo
,
499 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
501 OUT_BATCH(clear_val
);
504 if (intel
->always_flush_cache
)
505 intel_batchbuffer_emit_mi_flush(intel
);
507 if (buf
== BUFFER_DEPTH
|| buf
== BUFFER_STENCIL
)
508 mask
&= ~(BUFFER_BIT_DEPTH
| BUFFER_BIT_STENCIL
);
515 intelEmitImmediateColorExpandBlit(struct intel_context
*intel
,
517 GLubyte
*src_bits
, GLuint src_size
,
520 drm_intel_bo
*dst_buffer
,
523 GLshort x
, GLshort y
,
524 GLshort w
, GLshort h
,
527 int dwords
= ALIGN(src_size
, 8) / 4;
528 uint32_t opcode
, br13
, blit_cmd
;
530 if (dst_tiling
!= I915_TILING_NONE
) {
531 if (dst_offset
& 4095)
533 if (dst_tiling
== I915_TILING_Y
)
537 assert((logic_op
>= GL_CLEAR
) && (logic_op
<= (GL_CLEAR
+ 0x0f)));
538 assert(dst_pitch
> 0);
543 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
545 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
547 intel_batchbuffer_require_space(intel
,
552 opcode
= XY_SETUP_BLT_CMD
;
554 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
556 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
557 br13
|= br13_for_cpp(cpp
);
559 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
560 if (dst_tiling
!= I915_TILING_NONE
)
561 blit_cmd
|= XY_DST_TILED
;
564 OUT_BATCH(opcode
| (8 - 2));
566 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
567 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
568 OUT_RELOC_FENCED(dst_buffer
,
569 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
571 OUT_BATCH(0); /* bg */
572 OUT_BATCH(fg_color
); /* fg */
573 OUT_BATCH(0); /* pattern base addr */
575 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
576 OUT_BATCH((y
<< 16) | x
);
577 OUT_BATCH(((y
+ h
) << 16) | (x
+ w
));
580 intel_batchbuffer_data(intel
, src_bits
, dwords
* 4);
582 intel_batchbuffer_emit_mi_flush(intel
);
587 /* We don't have a memmove-type blit like some other hardware, so we'll do a
588 * rectangular blit covering a large space, then emit 1-scanline blit at the
589 * end to cover the last if we need.
592 intel_emit_linear_blit(struct intel_context
*intel
,
593 drm_intel_bo
*dst_bo
,
594 unsigned int dst_offset
,
595 drm_intel_bo
*src_bo
,
596 unsigned int src_offset
,
599 struct gl_context
*ctx
= &intel
->ctx
;
600 GLuint pitch
, height
;
603 /* The pitch given to the GPU must be DWORD aligned, and
604 * we want width to match pitch. Max width is (1 << 15 - 1),
605 * rounding that down to the nearest DWORD is 1 << 15 - 4
607 pitch
= ROUND_DOWN_TO(MIN2(size
, (1 << 15) - 1), 4);
608 height
= (pitch
== 0) ? 1 : size
/ pitch
;
609 ok
= intelEmitCopyBlit(intel
, 1,
610 pitch
, src_bo
, src_offset
, I915_TILING_NONE
,
611 pitch
, dst_bo
, dst_offset
, I915_TILING_NONE
,
614 pitch
, height
, /* w, h */
617 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n", pitch
, height
);
619 src_offset
+= pitch
* height
;
620 dst_offset
+= pitch
* height
;
621 size
-= pitch
* height
;
622 assert (size
< (1 << 15));
623 pitch
= ALIGN(size
, 4);
625 ok
= intelEmitCopyBlit(intel
, 1,
626 pitch
, src_bo
, src_offset
, I915_TILING_NONE
,
627 pitch
, dst_bo
, dst_offset
, I915_TILING_NONE
,
633 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n", size
, 1);
638 * Used to initialize the alpha value of an ARGB8888 miptree after copying
639 * into it from an XRGB8888 source.
641 * This is very common with glCopyTexImage2D(). Note that the coordinates are
642 * relative to the start of the miptree, not relative to a slice within the
646 intel_miptree_set_alpha_to_one(struct intel_context
*intel
,
647 struct intel_mipmap_tree
*mt
,
648 int x
, int y
, int width
, int height
)
650 struct intel_region
*region
= mt
->region
;
653 drm_intel_bo
*aper_array
[2];
656 pitch
= region
->pitch
;
659 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
660 __FUNCTION__
, region
->bo
, pitch
, x
, y
, width
, height
);
662 BR13
= br13_for_cpp(cpp
) | 0xf0 << 16;
663 CMD
= XY_COLOR_BLT_CMD
;
664 CMD
|= XY_BLT_WRITE_ALPHA
;
668 /* do space check before going any further */
669 aper_array
[0] = intel
->batch
.bo
;
670 aper_array
[1] = region
->bo
;
672 if (drm_intel_bufmgr_check_aperture_space(aper_array
,
673 ARRAY_SIZE(aper_array
)) != 0) {
674 intel_batchbuffer_flush(intel
);
678 OUT_BATCH(CMD
| (6 - 2));
680 OUT_BATCH((y
<< 16) | x
);
681 OUT_BATCH(((y
+ height
) << 16) | (x
+ width
));
682 OUT_RELOC_FENCED(region
->bo
,
683 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
685 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
688 intel_batchbuffer_emit_mi_flush(intel
);