1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_context.h"
34 #include "intel_mipmap_tree.h"
35 #include "intel_regions.h"
36 #include "intel_tex_layout.h"
37 #include "intel_tex.h"
38 #include "intel_blit.h"
41 #include "brw_blorp.h"
44 #include "main/enums.h"
45 #include "main/formats.h"
46 #include "main/glformats.h"
47 #include "main/texcompress_etc.h"
48 #include "main/teximage.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 target_to_target(GLenum target
)
56 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
57 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
58 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
59 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
60 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
61 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
62 return GL_TEXTURE_CUBE_MAP_ARB
;
70 * Determine which MSAA layout should be used by the MSAA surface being
71 * created, based on the chip generation and the surface type.
73 static enum intel_msaa_layout
74 compute_msaa_layout(struct intel_context
*intel
, gl_format format
, GLenum target
)
76 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
81 switch (_mesa_get_format_base_format(format
)) {
82 case GL_DEPTH_COMPONENT
:
83 case GL_STENCIL_INDEX
:
84 case GL_DEPTH_STENCIL
:
85 return INTEL_MSAA_LAYOUT_IMS
;
87 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
89 * This field must be set to 0 for all SINT MSRTs when all RT channels
92 * In practice this means that we have to disable MCS for all signed
93 * integer MSAA buffers. The alternative, to disable MCS only when one
94 * of the render target channels is disabled, is impractical because it
95 * would require converting between CMS and UMS MSAA layouts on the fly,
98 if (_mesa_get_format_datatype(format
) == GL_INT
) {
99 /* TODO: is this workaround needed for future chipsets? */
100 assert(intel
->gen
== 7);
101 return INTEL_MSAA_LAYOUT_UMS
;
103 /* For now, if we're going to be texturing from this surface,
104 * force UMS, so that the shader doesn't have to do different things
105 * based on whether there's a multisample control surface needing sampled first.
106 * We can't just blindly read the MCS surface in all cases because:
108 * From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
110 * If this field is disabled and the sampling engine <ld_mcs> message
111 * is issued on this surface, the MCS surface may be accessed. Software
112 * must ensure that the surface is defined to avoid GTT errors.
114 if (target
== GL_TEXTURE_2D_MULTISAMPLE
||
115 target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
116 return INTEL_MSAA_LAYOUT_UMS
;
118 return INTEL_MSAA_LAYOUT_CMS
;
126 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
127 * scaled-down bitfield representation of the color buffer which is capable of
128 * recording when blocks of the color buffer are equal to the clear value.
129 * This function returns the block size that will be used by the MCS buffer
130 * corresponding to a certain color miptree.
132 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
133 * beneath the "Fast Color Clear" bullet (p327):
135 * The following table describes the RT alignment
149 * This alignment has the following uses:
151 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
152 * buffer contains 128 blocks horizontally and 256 blocks vertically.
154 * - For figuring out alignment restrictions for a fast clear operation. Fast
155 * clear operations must always clear aligned multiples of 16 blocks
156 * horizontally and 32 blocks vertically.
158 * - For scaling down the coordinates sent through the render pipeline during
159 * a fast clear. X coordinates must be scaled down by 8 times the block
160 * width, and Y coordinates by 16 times the block height.
162 * - For scaling down the coordinates sent through the render pipeline during
163 * a "Render Target Resolve" operation. X coordinates must be scaled down
164 * by half the block width, and Y coordinates by half the block height.
167 intel_get_non_msrt_mcs_alignment(struct intel_context
*intel
,
168 struct intel_mipmap_tree
*mt
,
169 unsigned *width_px
, unsigned *height
)
171 switch (mt
->region
->tiling
) {
173 assert(!"Non-MSRT MCS requires X or Y tiling");
174 /* In release builds, fall through */
176 *width_px
= 32 / mt
->cpp
;
180 *width_px
= 64 / mt
->cpp
;
187 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
190 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
191 * beneath the "Fast Color Clear" bullet (p326):
193 * - Support is limited to tiled render targets.
194 * - Support is for non-mip-mapped and non-array surface types only.
196 * And then later, on p327:
198 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
202 intel_is_non_msrt_mcs_buffer_supported(struct intel_context
*intel
,
203 struct intel_mipmap_tree
*mt
)
206 /* MCS is not supported on the i915 (pre-Gen4) driver */
209 struct brw_context
*brw
= brw_context(&intel
->ctx
);
211 /* MCS support does not exist prior to Gen7 */
215 /* MCS is only supported for color buffers */
216 switch (_mesa_get_format_base_format(mt
->format
)) {
217 case GL_DEPTH_COMPONENT
:
218 case GL_DEPTH_STENCIL
:
219 case GL_STENCIL_INDEX
:
223 if (mt
->region
->tiling
!= I915_TILING_X
&&
224 mt
->region
->tiling
!= I915_TILING_Y
)
226 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
228 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
230 if (mt
->physical_depth0
!= 1)
233 /* There's no point in using an MCS buffer if the surface isn't in a
236 if (!brw
->format_supported_as_render_target
[mt
->format
])
245 * @param for_bo Indicates that the caller is
246 * intel_miptree_create_for_bo(). If true, then do not create
249 struct intel_mipmap_tree
*
250 intel_miptree_create_layout(struct intel_context
*intel
,
261 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
265 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
266 _mesa_lookup_enum_by_nr(target
),
267 _mesa_get_format_name(format
),
268 first_level
, last_level
, mt
);
270 mt
->target
= target_to_target(target
);
272 mt
->first_level
= first_level
;
273 mt
->last_level
= last_level
;
274 mt
->logical_width0
= width0
;
275 mt
->logical_height0
= height0
;
276 mt
->logical_depth0
= depth0
;
278 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
281 /* The cpp is bytes per (1, blockheight)-sized block for compressed
282 * textures. This is why you'll see divides by blockheight all over
285 _mesa_get_format_block_size(format
, &bw
, &bh
);
286 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
287 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
289 mt
->num_samples
= num_samples
;
290 mt
->compressed
= _mesa_is_format_compressed(format
);
291 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
294 if (num_samples
> 1) {
295 /* Adjust width/height/depth for MSAA */
296 mt
->msaa_layout
= compute_msaa_layout(intel
, format
, mt
->target
);
297 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
298 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
300 * "Any of the other messages (sample*, LOD, load4) used with a
301 * (4x) multisampled surface will in-effect sample a surface with
302 * double the height and width as that indicated in the surface
303 * state. Each pixel position on the original-sized surface is
304 * replaced with a 2x2 of samples with the following arrangement:
309 * Thus, when sampling from a multisampled texture, it behaves as
310 * though the layout in memory for (x,y,sample) is:
312 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
313 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
315 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
316 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
318 * However, the actual layout of multisampled data in memory is:
320 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
321 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
323 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
324 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
326 * This pattern repeats for each 2x2 pixel block.
328 * As a result, when calculating the size of our 4-sample buffer for
329 * an odd width or height, we have to align before scaling up because
330 * sample 3 is in that bottom right 2x2 block.
332 switch (num_samples
) {
334 width0
= ALIGN(width0
, 2) * 2;
335 height0
= ALIGN(height0
, 2) * 2;
338 width0
= ALIGN(width0
, 2) * 4;
339 height0
= ALIGN(height0
, 2) * 2;
342 /* num_samples should already have been quantized to 0, 1, 4, or
348 /* Non-interleaved */
349 depth0
*= num_samples
;
353 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
356 switch (mt
->msaa_layout
) {
357 case INTEL_MSAA_LAYOUT_NONE
:
358 case INTEL_MSAA_LAYOUT_IMS
:
359 mt
->array_spacing_lod0
= false;
361 case INTEL_MSAA_LAYOUT_UMS
:
362 case INTEL_MSAA_LAYOUT_CMS
:
363 mt
->array_spacing_lod0
= true;
367 if (target
== GL_TEXTURE_CUBE_MAP
) {
372 mt
->physical_width0
= width0
;
373 mt
->physical_height0
= height0
;
374 mt
->physical_depth0
= depth0
;
377 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
378 (intel
->must_use_separate_stencil
)) {
379 mt
->stencil_mt
= intel_miptree_create(intel
,
389 INTEL_MIPTREE_TILING_ANY
);
390 if (!mt
->stencil_mt
) {
391 intel_miptree_release(&mt
);
395 /* Fix up the Z miptree format for how we're splitting out separate
396 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
398 if (mt
->format
== MESA_FORMAT_S8_Z24
) {
399 mt
->format
= MESA_FORMAT_X8_Z24
;
400 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_X24S8
) {
401 mt
->format
= MESA_FORMAT_Z32_FLOAT
;
404 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
405 _mesa_get_format_name(mt
->format
));
409 intel_get_texture_alignment_unit(intel
, mt
->format
,
410 &mt
->align_w
, &mt
->align_h
);
415 i945_miptree_layout(mt
);
417 i915_miptree_layout(mt
);
419 brw_miptree_layout(intel
, mt
);
426 * \brief Helper function for intel_miptree_create().
429 intel_miptree_choose_tiling(struct intel_context
*intel
,
432 uint32_t num_samples
,
433 enum intel_miptree_tiling_mode requested
,
434 struct intel_mipmap_tree
*mt
)
437 if (format
== MESA_FORMAT_S8
) {
438 /* The stencil buffer is W tiled. However, we request from the kernel a
439 * non-tiled buffer because the GTT is incapable of W fencing.
441 return I915_TILING_NONE
;
444 /* Some usages may want only one type of tiling, like depth miptrees (Y
445 * tiled), or temporary BOs for uploading data once (linear).
448 case INTEL_MIPTREE_TILING_ANY
:
450 case INTEL_MIPTREE_TILING_Y
:
451 return I915_TILING_Y
;
452 case INTEL_MIPTREE_TILING_NONE
:
453 return I915_TILING_NONE
;
456 if (num_samples
> 1) {
457 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
460 * [DevSNB+]: For multi-sample render targets, this field must be
461 * 1. MSRTs can only be tiled.
463 * Our usual reason for preferring X tiling (fast blits using the
464 * blitting engine) doesn't apply to MSAA, since we'll generally be
465 * downsampling or upsampling when blitting between the MSAA buffer
466 * and another buffer, and the blitting engine doesn't support that.
467 * So use Y tiling, since it makes better use of the cache.
469 return I915_TILING_Y
;
472 GLenum base_format
= _mesa_get_format_base_format(format
);
473 if (intel
->gen
>= 4 &&
474 (base_format
== GL_DEPTH_COMPONENT
||
475 base_format
== GL_DEPTH_STENCIL_EXT
))
476 return I915_TILING_Y
;
478 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
480 /* If the width is much smaller than a tile, don't bother tiling. */
481 if (minimum_pitch
< 64)
482 return I915_TILING_NONE
;
484 if (ALIGN(minimum_pitch
, 512) >= 32768) {
485 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
486 mt
->total_width
, mt
->total_height
);
487 return I915_TILING_NONE
;
490 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
492 return I915_TILING_X
;
494 return I915_TILING_Y
| I915_TILING_X
;
497 struct intel_mipmap_tree
*
498 intel_miptree_create(struct intel_context
*intel
,
506 bool expect_accelerated_upload
,
508 enum intel_miptree_tiling_mode requested_tiling
)
510 struct intel_mipmap_tree
*mt
;
511 gl_format tex_format
= format
;
512 gl_format etc_format
= MESA_FORMAT_NONE
;
513 GLuint total_width
, total_height
;
515 if (!intel
->is_baytrail
) {
517 case MESA_FORMAT_ETC1_RGB8
:
518 format
= MESA_FORMAT_RGBX8888_REV
;
520 case MESA_FORMAT_ETC2_RGB8
:
521 format
= MESA_FORMAT_RGBX8888_REV
;
523 case MESA_FORMAT_ETC2_SRGB8
:
524 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
525 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
526 format
= MESA_FORMAT_SARGB8
;
528 case MESA_FORMAT_ETC2_RGBA8_EAC
:
529 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
530 format
= MESA_FORMAT_RGBA8888_REV
;
532 case MESA_FORMAT_ETC2_R11_EAC
:
533 format
= MESA_FORMAT_R16
;
535 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
536 format
= MESA_FORMAT_SIGNED_R16
;
538 case MESA_FORMAT_ETC2_RG11_EAC
:
539 format
= MESA_FORMAT_GR1616
;
541 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
542 format
= MESA_FORMAT_SIGNED_GR1616
;
545 /* Non ETC1 / ETC2 format */
550 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
552 mt
= intel_miptree_create_layout(intel
, target
, format
,
553 first_level
, last_level
, width0
,
557 * pitch == 0 || height == 0 indicates the null texture
559 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
560 intel_miptree_release(&mt
);
564 total_width
= mt
->total_width
;
565 total_height
= mt
->total_height
;
567 if (format
== MESA_FORMAT_S8
) {
568 /* Align to size of W tile, 64x64. */
569 total_width
= ALIGN(total_width
, 64);
570 total_height
= ALIGN(total_height
, 64);
573 uint32_t tiling
= intel_miptree_choose_tiling(intel
, format
, width0
,
574 num_samples
, requested_tiling
,
576 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
578 mt
->etc_format
= etc_format
;
579 mt
->region
= intel_region_alloc(intel
->intelScreen
,
580 y_or_x
? I915_TILING_Y
: tiling
,
584 expect_accelerated_upload
);
586 /* If the region is too large to fit in the aperture, we need to use the
587 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
588 * so we need to fall back to X.
590 if (y_or_x
&& mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
591 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
592 mt
->total_width
, mt
->total_height
);
593 intel_region_release(&mt
->region
);
595 mt
->region
= intel_region_alloc(intel
->intelScreen
,
600 expect_accelerated_upload
);
606 intel_miptree_release(&mt
);
611 /* If this miptree is capable of supporting fast color clears, set
612 * mcs_state appropriately to ensure that fast clears will occur.
613 * Allocation of the MCS miptree will be deferred until the first fast
614 * clear actually occurs.
616 if (intel_is_non_msrt_mcs_buffer_supported(intel
, mt
))
617 mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
623 struct intel_mipmap_tree
*
624 intel_miptree_create_for_bo(struct intel_context
*intel
,
633 struct intel_mipmap_tree
*mt
;
635 struct intel_region
*region
= calloc(1, sizeof(*region
));
639 /* Nothing will be able to use this miptree with the BO if the offset isn't
642 if (tiling
!= I915_TILING_NONE
)
643 assert(offset
% 4096 == 0);
645 /* miptrees can't handle negative pitch. If you need flipping of images,
646 * that's outside of the scope of the mt.
650 mt
= intel_miptree_create_layout(intel
, GL_TEXTURE_2D
, format
,
653 true, 0 /* num_samples */);
657 region
->cpp
= mt
->cpp
;
658 region
->width
= width
;
659 region
->height
= height
;
660 region
->pitch
= pitch
;
661 region
->refcount
= 1;
662 drm_intel_bo_reference(bo
);
664 region
->tiling
= tiling
;
674 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
676 * For a multisample DRI2 buffer, this wraps the given region with
677 * a singlesample miptree, then creates a multisample miptree into which the
678 * singlesample miptree is embedded as a child.
680 struct intel_mipmap_tree
*
681 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
682 unsigned dri_attachment
,
684 uint32_t num_samples
,
685 struct intel_region
*region
)
687 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
688 struct intel_mipmap_tree
*multisample_mt
= NULL
;
690 /* Only the front and back buffers, which are color buffers, are shared
693 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
694 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
695 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
696 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
697 _mesa_get_format_base_format(format
) == GL_RGBA
);
699 singlesample_mt
= intel_miptree_create_for_bo(intel
,
707 if (!singlesample_mt
)
709 singlesample_mt
->region
->name
= region
->name
;
712 /* If this miptree is capable of supporting fast color clears, set
713 * mcs_state appropriately to ensure that fast clears will occur.
714 * Allocation of the MCS miptree will be deferred until the first fast
715 * clear actually occurs.
717 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
718 singlesample_mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
721 if (num_samples
== 0)
722 return singlesample_mt
;
724 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
729 if (!multisample_mt
) {
730 intel_miptree_release(&singlesample_mt
);
734 multisample_mt
->singlesample_mt
= singlesample_mt
;
735 multisample_mt
->need_downsample
= false;
737 if (intel
->is_front_buffer_rendering
&&
738 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
739 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
740 intel_miptree_upsample(intel
, multisample_mt
);
743 return multisample_mt
;
746 struct intel_mipmap_tree
*
747 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
751 uint32_t num_samples
)
753 struct intel_mipmap_tree
*mt
;
757 mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, format
, 0, 0,
758 width
, height
, depth
, true, num_samples
,
759 INTEL_MIPTREE_TILING_ANY
);
763 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
764 ok
= intel_miptree_alloc_mcs(intel
, mt
, num_samples
);
772 intel_miptree_release(&mt
);
777 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
778 struct intel_mipmap_tree
*src
)
783 intel_miptree_release(dst
);
787 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
795 intel_miptree_release(struct intel_mipmap_tree
**mt
)
800 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
801 if (--(*mt
)->refcount
<= 0) {
804 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
806 intel_region_release(&((*mt
)->region
));
807 intel_miptree_release(&(*mt
)->stencil_mt
);
809 intel_miptree_release(&(*mt
)->mcs_mt
);
811 intel_miptree_release(&(*mt
)->singlesample_mt
);
813 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
814 free((*mt
)->level
[i
].slice
);
823 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
824 int *width
, int *height
, int *depth
)
826 switch (image
->TexObject
->Target
) {
827 case GL_TEXTURE_1D_ARRAY
:
828 *width
= image
->Width
;
830 *depth
= image
->Height
;
833 *width
= image
->Width
;
834 *height
= image
->Height
;
835 *depth
= image
->Depth
;
841 * Can the image be pulled into a unified mipmap tree? This mirrors
842 * the completeness test in a lot of ways.
844 * Not sure whether I want to pass gl_texture_image here.
847 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
848 struct gl_texture_image
*image
)
850 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
851 GLuint level
= intelImage
->base
.Base
.Level
;
852 int width
, height
, depth
;
854 /* glTexImage* choose the texture object based on the target passed in, and
855 * objects can't change targets over their lifetimes, so this should be
858 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
860 gl_format mt_format
= mt
->format
;
861 if (mt
->format
== MESA_FORMAT_X8_Z24
&& mt
->stencil_mt
)
862 mt_format
= MESA_FORMAT_S8_Z24
;
863 if (mt
->format
== MESA_FORMAT_Z32_FLOAT
&& mt
->stencil_mt
)
864 mt_format
= MESA_FORMAT_Z32_FLOAT_X24S8
;
865 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
866 mt_format
= mt
->etc_format
;
868 if (image
->TexFormat
!= mt_format
)
871 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
873 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
876 /* Test image dimensions against the base level image adjusted for
877 * minification. This will also catch images not present in the
878 * tree, changed targets, etc.
880 if (mt
->target
== GL_TEXTURE_2D_MULTISAMPLE
||
881 mt
->target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
882 /* nonzero level here is always bogus */
885 if (width
!= mt
->logical_width0
||
886 height
!= mt
->logical_height0
||
887 depth
!= mt
->logical_depth0
) {
892 /* all normal textures, renderbuffers, etc */
893 if (width
!= mt
->level
[level
].width
||
894 height
!= mt
->level
[level
].height
||
895 depth
!= mt
->level
[level
].depth
) {
900 if (image
->NumSamples
!= mt
->num_samples
)
908 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
911 GLuint w
, GLuint h
, GLuint d
)
913 mt
->level
[level
].width
= w
;
914 mt
->level
[level
].height
= h
;
915 mt
->level
[level
].depth
= d
;
916 mt
->level
[level
].level_x
= x
;
917 mt
->level
[level
].level_y
= y
;
919 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
920 level
, w
, h
, d
, x
, y
);
922 assert(mt
->level
[level
].slice
== NULL
);
924 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
925 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
926 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
931 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
932 GLuint level
, GLuint img
,
935 if (img
== 0 && level
== 0)
936 assert(x
== 0 && y
== 0);
938 assert(img
< mt
->level
[level
].depth
);
940 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
941 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
943 DBG("%s level %d img %d pos %d,%d\n",
944 __FUNCTION__
, level
, img
,
945 mt
->level
[level
].slice
[img
].x_offset
,
946 mt
->level
[level
].slice
[img
].y_offset
);
950 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
951 GLuint level
, GLuint slice
,
952 GLuint
*x
, GLuint
*y
)
954 assert(slice
< mt
->level
[level
].depth
);
956 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
957 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
961 * Rendering with tiled buffers requires that the base address of the buffer
962 * be aligned to a page boundary. For renderbuffers, and sometimes with
963 * textures, we may want the surface to point at a texture image level that
964 * isn't at a page boundary.
966 * This function returns an appropriately-aligned base offset
967 * according to the tiling restrictions, plus any required x/y offset
971 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
972 GLuint level
, GLuint slice
,
976 struct intel_region
*region
= mt
->region
;
978 uint32_t mask_x
, mask_y
;
980 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
981 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
983 *tile_x
= x
& mask_x
;
984 *tile_y
= y
& mask_y
;
986 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
991 intel_miptree_copy_slice_sw(struct intel_context
*intel
,
992 struct intel_mipmap_tree
*dst_mt
,
993 struct intel_mipmap_tree
*src_mt
,
1000 int src_stride
, dst_stride
;
1001 int cpp
= dst_mt
->cpp
;
1003 intel_miptree_map(intel
, src_mt
,
1007 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1010 intel_miptree_map(intel
, dst_mt
,
1014 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1018 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1019 _mesa_get_format_name(src_mt
->format
),
1020 src_mt
, src
, src_stride
,
1021 _mesa_get_format_name(dst_mt
->format
),
1022 dst_mt
, dst
, dst_stride
,
1025 int row_size
= cpp
* width
;
1026 if (src_stride
== row_size
&&
1027 dst_stride
== row_size
) {
1028 memcpy(dst
, src
, row_size
* height
);
1030 for (int i
= 0; i
< height
; i
++) {
1031 memcpy(dst
, src
, row_size
);
1037 intel_miptree_unmap(intel
, dst_mt
, level
, slice
);
1038 intel_miptree_unmap(intel
, src_mt
, level
, slice
);
1040 /* Don't forget to copy the stencil data over, too. We could have skipped
1041 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1042 * shuffling the two data sources in/out of temporary storage instead of
1043 * the direct mapping we get this way.
1045 if (dst_mt
->stencil_mt
) {
1046 assert(src_mt
->stencil_mt
);
1047 intel_miptree_copy_slice_sw(intel
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1048 level
, slice
, width
, height
);
1053 intel_miptree_copy_slice(struct intel_context
*intel
,
1054 struct intel_mipmap_tree
*dst_mt
,
1055 struct intel_mipmap_tree
*src_mt
,
1061 gl_format format
= src_mt
->format
;
1062 uint32_t width
= src_mt
->level
[level
].width
;
1063 uint32_t height
= src_mt
->level
[level
].height
;
1071 assert(depth
< src_mt
->level
[level
].depth
);
1072 assert(src_mt
->format
== dst_mt
->format
);
1074 if (dst_mt
->compressed
) {
1075 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1076 width
= ALIGN(width
, dst_mt
->align_w
);
1079 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1080 * below won't apply since we can't do the depth's Y tiling or the
1081 * stencil's W tiling in the blitter.
1083 if (src_mt
->stencil_mt
) {
1084 intel_miptree_copy_slice_sw(intel
,
1091 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1092 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1093 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1095 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1096 _mesa_get_format_name(src_mt
->format
),
1097 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1098 _mesa_get_format_name(dst_mt
->format
),
1099 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1102 if (!intel_miptree_blit(intel
,
1103 src_mt
, level
, slice
, 0, 0, false,
1104 dst_mt
, level
, slice
, 0, 0, false,
1105 width
, height
, GL_COPY
)) {
1106 perf_debug("miptree validate blit for %s failed\n",
1107 _mesa_get_format_name(format
));
1109 intel_miptree_copy_slice_sw(intel
, dst_mt
, src_mt
, level
, slice
,
1115 * Copies the image's current data to the given miptree, and associates that
1116 * miptree with the image.
1118 * If \c invalidate is true, then the actual image data does not need to be
1119 * copied, but the image still needs to be associated to the new miptree (this
1120 * is set to true if we're about to clear the image).
1123 intel_miptree_copy_teximage(struct intel_context
*intel
,
1124 struct intel_texture_image
*intelImage
,
1125 struct intel_mipmap_tree
*dst_mt
,
1128 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1129 struct intel_texture_object
*intel_obj
=
1130 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1131 int level
= intelImage
->base
.Base
.Level
;
1132 int face
= intelImage
->base
.Base
.Face
;
1133 GLuint depth
= intelImage
->base
.Base
.Depth
;
1136 for (int slice
= 0; slice
< depth
; slice
++) {
1137 intel_miptree_copy_slice(intel
, dst_mt
, src_mt
, level
, face
, slice
);
1141 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1142 intel_obj
->needs_validate
= true;
1146 intel_miptree_alloc_mcs(struct intel_context
*intel
,
1147 struct intel_mipmap_tree
*mt
,
1150 assert(intel
->gen
>= 7); /* MCS only used on Gen7+ */
1154 assert(mt
->mcs_mt
== NULL
);
1156 /* Choose the correct format for the MCS buffer. All that really matters
1157 * is that we allocate the right buffer size, since we'll always be
1158 * accessing this miptree using MCS-specific hardware mechanisms, which
1159 * infer the correct format based on num_samples.
1162 switch (num_samples
) {
1164 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1167 format
= MESA_FORMAT_R8
;
1170 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1171 * for each sample, plus 8 padding bits).
1173 format
= MESA_FORMAT_R_UINT32
;
1176 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1180 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1182 * "The MCS surface must be stored as Tile Y."
1184 mt
->mcs_state
= INTEL_MCS_STATE_MSAA
;
1185 mt
->mcs_mt
= intel_miptree_create(intel
,
1191 mt
->logical_height0
,
1194 0 /* num_samples */,
1195 INTEL_MIPTREE_TILING_Y
);
1197 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1199 * When MCS buffer is enabled and bound to MSRT, it is required that it
1200 * is cleared prior to any rendering.
1202 * Since we don't use the MCS buffer for any purpose other than rendering,
1203 * it makes sense to just clear it immediately upon allocation.
1205 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1207 void *data
= intel_miptree_map_raw(intel
, mt
->mcs_mt
);
1208 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1209 intel_miptree_unmap_raw(intel
, mt
->mcs_mt
);
1217 intel_miptree_alloc_non_msrt_mcs(struct intel_context
*intel
,
1218 struct intel_mipmap_tree
*mt
)
1221 assert(!"MCS not supported on i915");
1224 assert(mt
->mcs_mt
== NULL
);
1226 /* The format of the MCS buffer is opaque to the driver; all that matters
1227 * is that we get its size and pitch right. We'll pretend that the format
1228 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1229 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1230 * the block width and then a further factor of 4. Since an MCS tile
1231 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1232 * we'll need to scale the height down by the block height and then a
1233 * further factor of 8.
1235 const gl_format format
= MESA_FORMAT_R_UINT32
;
1236 unsigned block_width_px
;
1237 unsigned block_height
;
1238 intel_get_non_msrt_mcs_alignment(intel
, mt
, &block_width_px
, &block_height
);
1239 unsigned width_divisor
= block_width_px
* 4;
1240 unsigned height_divisor
= block_height
* 8;
1241 unsigned mcs_width
=
1242 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1243 unsigned mcs_height
=
1244 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1245 assert(mt
->logical_depth0
== 1);
1246 mt
->mcs_mt
= intel_miptree_create(intel
,
1255 0 /* num_samples */,
1256 INTEL_MIPTREE_TILING_Y
);
1263 intel_miptree_resolve_color(struct intel_context
*intel
,
1264 struct intel_mipmap_tree
*mt
)
1267 /* Fast color clear is not supported on the i915 (pre-Gen4) driver */
1269 switch (mt
->mcs_state
) {
1270 case INTEL_MCS_STATE_NONE
:
1271 case INTEL_MCS_STATE_MSAA
:
1272 case INTEL_MCS_STATE_RESOLVED
:
1273 /* No resolve needed */
1275 case INTEL_MCS_STATE_UNRESOLVED
:
1276 case INTEL_MCS_STATE_CLEAR
:
1277 brw_blorp_resolve_color(intel
, mt
);
1285 * Make it possible to share the region backing the given miptree with another
1286 * process or another miptree.
1288 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1289 * then discard the MCS buffer, if present. We also set the mcs_state to
1290 * INTEL_MCS_STATE_NONE to ensure that no MCS buffer gets allocated in the
1294 intel_miptree_make_shareable(struct intel_context
*intel
,
1295 struct intel_mipmap_tree
*mt
)
1298 /* Nothing needs to be done for I915 */
1302 /* MCS buffers are also used for multisample buffers, but we can't resolve
1303 * away a multisample MCS buffer because it's an integral part of how the
1304 * pixel data is stored. Fortunately this code path should never be
1305 * reached for multisample buffers.
1307 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1310 intel_miptree_resolve_color(intel
, mt
);
1311 intel_miptree_release(&mt
->mcs_mt
);
1312 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
1319 * \brief Get pointer offset into stencil buffer.
1321 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1322 * must decode the tile's layout in software.
1325 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1327 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1329 * Even though the returned offset is always positive, the return type is
1331 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1332 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1335 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1337 uint32_t tile_size
= 4096;
1338 uint32_t tile_width
= 64;
1339 uint32_t tile_height
= 64;
1340 uint32_t row_size
= 64 * stride
;
1342 uint32_t tile_x
= x
/ tile_width
;
1343 uint32_t tile_y
= y
/ tile_height
;
1345 /* The byte's address relative to the tile's base addres. */
1346 uint32_t byte_x
= x
% tile_width
;
1347 uint32_t byte_y
= y
% tile_height
;
1349 uintptr_t u
= tile_y
* row_size
1350 + tile_x
* tile_size
1351 + 512 * (byte_x
/ 8)
1353 + 32 * ((byte_y
/ 4) % 2)
1354 + 16 * ((byte_x
/ 4) % 2)
1355 + 8 * ((byte_y
/ 2) % 2)
1356 + 4 * ((byte_x
/ 2) % 2)
1361 /* adjust for bit6 swizzling */
1362 if (((byte_x
/ 8) % 2) == 1) {
1363 if (((byte_y
/ 8) % 2) == 0) {
1375 intel_miptree_updownsample(struct intel_context
*intel
,
1376 struct intel_mipmap_tree
*src
,
1377 struct intel_mipmap_tree
*dst
,
1387 brw_blorp_blit_miptrees(intel
,
1388 src
, 0 /* level */, 0 /* layer */,
1389 dst
, 0 /* level */, 0 /* layer */,
1394 false, false /*mirror x, y*/);
1396 if (src
->stencil_mt
) {
1397 brw_blorp_blit_miptrees(intel
,
1398 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1399 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1404 false, false /*mirror x, y*/);
1410 assert_is_flat(struct intel_mipmap_tree
*mt
)
1412 assert(mt
->target
== GL_TEXTURE_2D
);
1413 assert(mt
->first_level
== 0);
1414 assert(mt
->last_level
== 0);
1418 * \brief Downsample from mt to mt->singlesample_mt.
1420 * If the miptree needs no downsample, then skip.
1423 intel_miptree_downsample(struct intel_context
*intel
,
1424 struct intel_mipmap_tree
*mt
)
1426 /* Only flat, renderbuffer-like miptrees are supported. */
1429 if (!mt
->need_downsample
)
1431 intel_miptree_updownsample(intel
,
1432 mt
, mt
->singlesample_mt
,
1434 mt
->logical_height0
);
1435 mt
->need_downsample
= false;
1439 * \brief Upsample from mt->singlesample_mt to mt.
1441 * The upsample is done unconditionally.
1444 intel_miptree_upsample(struct intel_context
*intel
,
1445 struct intel_mipmap_tree
*mt
)
1447 /* Only flat, renderbuffer-like miptrees are supported. */
1449 assert(!mt
->need_downsample
);
1451 intel_miptree_updownsample(intel
,
1452 mt
->singlesample_mt
, mt
,
1454 mt
->logical_height0
);
1458 intel_miptree_map_raw(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
)
1460 /* CPU accesses to color buffers don't understand fast color clears, so
1461 * resolve any pending fast color clears before we map.
1463 intel_miptree_resolve_color(intel
, mt
);
1465 drm_intel_bo
*bo
= mt
->region
->bo
;
1467 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1468 if (drm_intel_bo_busy(bo
)) {
1469 perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
1473 intel_flush(&intel
->ctx
);
1475 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1476 drm_intel_gem_bo_map_gtt(bo
);
1478 drm_intel_bo_map(bo
, true);
1484 intel_miptree_unmap_raw(struct intel_context
*intel
,
1485 struct intel_mipmap_tree
*mt
)
1487 drm_intel_bo_unmap(mt
->region
->bo
);
1491 intel_miptree_map_gtt(struct intel_context
*intel
,
1492 struct intel_mipmap_tree
*mt
,
1493 struct intel_miptree_map
*map
,
1494 unsigned int level
, unsigned int slice
)
1496 unsigned int bw
, bh
;
1498 unsigned int image_x
, image_y
;
1502 /* For compressed formats, the stride is the number of bytes per
1503 * row of blocks. intel_miptree_get_image_offset() already does
1506 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1507 assert(y
% bh
== 0);
1510 base
= intel_miptree_map_raw(intel
, mt
) + mt
->offset
;
1515 /* Note that in the case of cube maps, the caller must have passed the
1516 * slice number referencing the face.
1518 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1522 map
->stride
= mt
->region
->pitch
;
1523 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1526 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1527 map
->x
, map
->y
, map
->w
, map
->h
,
1528 mt
, _mesa_get_format_name(mt
->format
),
1529 x
, y
, map
->ptr
, map
->stride
);
1533 intel_miptree_unmap_gtt(struct intel_context
*intel
,
1534 struct intel_mipmap_tree
*mt
,
1535 struct intel_miptree_map
*map
,
1539 intel_miptree_unmap_raw(intel
, mt
);
1543 intel_miptree_map_blit(struct intel_context
*intel
,
1544 struct intel_mipmap_tree
*mt
,
1545 struct intel_miptree_map
*map
,
1546 unsigned int level
, unsigned int slice
)
1548 map
->mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, mt
->format
,
1552 INTEL_MIPTREE_TILING_NONE
);
1554 fprintf(stderr
, "Failed to allocate blit temporary\n");
1557 map
->stride
= map
->mt
->region
->pitch
;
1559 if (!intel_miptree_blit(intel
,
1561 map
->x
, map
->y
, false,
1564 map
->w
, map
->h
, GL_COPY
)) {
1565 fprintf(stderr
, "Failed to blit\n");
1569 intel_batchbuffer_flush(intel
);
1570 map
->ptr
= intel_miptree_map_raw(intel
, map
->mt
);
1572 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1573 map
->x
, map
->y
, map
->w
, map
->h
,
1574 mt
, _mesa_get_format_name(mt
->format
),
1575 level
, slice
, map
->ptr
, map
->stride
);
1580 intel_miptree_release(&map
->mt
);
1586 intel_miptree_unmap_blit(struct intel_context
*intel
,
1587 struct intel_mipmap_tree
*mt
,
1588 struct intel_miptree_map
*map
,
1592 struct gl_context
*ctx
= &intel
->ctx
;
1594 intel_miptree_unmap_raw(intel
, map
->mt
);
1596 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1597 bool ok
= intel_miptree_blit(intel
,
1601 map
->x
, map
->y
, false,
1602 map
->w
, map
->h
, GL_COPY
);
1603 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1606 intel_miptree_release(&map
->mt
);
1610 intel_miptree_map_s8(struct intel_context
*intel
,
1611 struct intel_mipmap_tree
*mt
,
1612 struct intel_miptree_map
*map
,
1613 unsigned int level
, unsigned int slice
)
1615 map
->stride
= map
->w
;
1616 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1620 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1621 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1622 * invalidate is set, since we'll be writing the whole rectangle from our
1623 * temporary buffer back out.
1625 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1626 uint8_t *untiled_s8_map
= map
->ptr
;
1627 uint8_t *tiled_s8_map
= intel_miptree_map_raw(intel
, mt
);
1628 unsigned int image_x
, image_y
;
1630 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1632 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1633 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1634 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1635 x
+ image_x
+ map
->x
,
1636 y
+ image_y
+ map
->y
,
1637 intel
->has_swizzling
);
1638 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1642 intel_miptree_unmap_raw(intel
, mt
);
1644 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1645 map
->x
, map
->y
, map
->w
, map
->h
,
1646 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1648 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1649 map
->x
, map
->y
, map
->w
, map
->h
,
1650 mt
, map
->ptr
, map
->stride
);
1655 intel_miptree_unmap_s8(struct intel_context
*intel
,
1656 struct intel_mipmap_tree
*mt
,
1657 struct intel_miptree_map
*map
,
1661 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1662 unsigned int image_x
, image_y
;
1663 uint8_t *untiled_s8_map
= map
->ptr
;
1664 uint8_t *tiled_s8_map
= intel_miptree_map_raw(intel
, mt
);
1666 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1668 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1669 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1670 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1673 intel
->has_swizzling
);
1674 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1678 intel_miptree_unmap_raw(intel
, mt
);
1685 intel_miptree_map_etc(struct intel_context
*intel
,
1686 struct intel_mipmap_tree
*mt
,
1687 struct intel_miptree_map
*map
,
1691 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1692 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1693 assert(mt
->format
== MESA_FORMAT_RGBX8888_REV
);
1696 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1697 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1699 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1700 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1701 map
->w
, map
->h
, 1));
1702 map
->ptr
= map
->buffer
;
1706 intel_miptree_unmap_etc(struct intel_context
*intel
,
1707 struct intel_mipmap_tree
*mt
,
1708 struct intel_miptree_map
*map
,
1714 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1719 uint8_t *dst
= intel_miptree_map_raw(intel
, mt
)
1720 + image_y
* mt
->region
->pitch
1721 + image_x
* mt
->region
->cpp
;
1723 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1724 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1725 map
->ptr
, map
->stride
,
1728 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1729 map
->ptr
, map
->stride
,
1730 map
->w
, map
->h
, mt
->etc_format
);
1732 intel_miptree_unmap_raw(intel
, mt
);
1737 * Mapping function for packed depth/stencil miptrees backed by real separate
1738 * miptrees for depth and stencil.
1740 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1741 * separate from the depth buffer. Yet at the GL API level, we have to expose
1742 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1743 * be able to map that memory for texture storage and glReadPixels-type
1744 * operations. We give Mesa core that access by mallocing a temporary and
1745 * copying the data between the actual backing store and the temporary.
1748 intel_miptree_map_depthstencil(struct intel_context
*intel
,
1749 struct intel_mipmap_tree
*mt
,
1750 struct intel_miptree_map
*map
,
1751 unsigned int level
, unsigned int slice
)
1753 struct intel_mipmap_tree
*z_mt
= mt
;
1754 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1755 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1756 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1758 map
->stride
= map
->w
* packed_bpp
;
1759 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1763 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1764 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1765 * invalidate is set, since we'll be writing the whole rectangle from our
1766 * temporary buffer back out.
1768 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1769 uint32_t *packed_map
= map
->ptr
;
1770 uint8_t *s_map
= intel_miptree_map_raw(intel
, s_mt
);
1771 uint32_t *z_map
= intel_miptree_map_raw(intel
, z_mt
);
1772 unsigned int s_image_x
, s_image_y
;
1773 unsigned int z_image_x
, z_image_y
;
1775 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1776 &s_image_x
, &s_image_y
);
1777 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1778 &z_image_x
, &z_image_y
);
1780 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1781 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1782 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1783 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1786 intel
->has_swizzling
);
1787 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1788 (z_mt
->region
->pitch
/ 4) +
1789 (map_x
+ z_image_x
));
1790 uint8_t s
= s_map
[s_offset
];
1791 uint32_t z
= z_map
[z_offset
];
1793 if (map_z32f_x24s8
) {
1794 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1795 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1797 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1802 intel_miptree_unmap_raw(intel
, s_mt
);
1803 intel_miptree_unmap_raw(intel
, z_mt
);
1805 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1807 map
->x
, map
->y
, map
->w
, map
->h
,
1808 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1809 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1810 map
->ptr
, map
->stride
);
1812 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1813 map
->x
, map
->y
, map
->w
, map
->h
,
1814 mt
, map
->ptr
, map
->stride
);
1819 intel_miptree_unmap_depthstencil(struct intel_context
*intel
,
1820 struct intel_mipmap_tree
*mt
,
1821 struct intel_miptree_map
*map
,
1825 struct intel_mipmap_tree
*z_mt
= mt
;
1826 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1827 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1829 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1830 uint32_t *packed_map
= map
->ptr
;
1831 uint8_t *s_map
= intel_miptree_map_raw(intel
, s_mt
);
1832 uint32_t *z_map
= intel_miptree_map_raw(intel
, z_mt
);
1833 unsigned int s_image_x
, s_image_y
;
1834 unsigned int z_image_x
, z_image_y
;
1836 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1837 &s_image_x
, &s_image_y
);
1838 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1839 &z_image_x
, &z_image_y
);
1841 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1842 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1843 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1844 x
+ s_image_x
+ map
->x
,
1845 y
+ s_image_y
+ map
->y
,
1846 intel
->has_swizzling
);
1847 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
1848 (z_mt
->region
->pitch
/ 4) +
1851 if (map_z32f_x24s8
) {
1852 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
1853 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
1855 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
1856 s_map
[s_offset
] = packed
>> 24;
1857 z_map
[z_offset
] = packed
;
1862 intel_miptree_unmap_raw(intel
, s_mt
);
1863 intel_miptree_unmap_raw(intel
, z_mt
);
1865 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
1867 map
->x
, map
->y
, map
->w
, map
->h
,
1868 z_mt
, _mesa_get_format_name(z_mt
->format
),
1869 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1870 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1871 map
->ptr
, map
->stride
);
1878 * Create and attach a map to the miptree at (level, slice). Return the
1881 static struct intel_miptree_map
*
1882 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
1891 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
1896 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
1897 mt
->level
[level
].slice
[slice
].map
= map
;
1909 * Release the map at (level, slice).
1912 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
1916 struct intel_miptree_map
**map
;
1918 map
= &mt
->level
[level
].slice
[slice
].map
;
1924 intel_miptree_map_singlesample(struct intel_context
*intel
,
1925 struct intel_mipmap_tree
*mt
,
1936 struct intel_miptree_map
*map
;
1938 assert(mt
->num_samples
<= 1);
1940 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
1947 if (mt
->format
== MESA_FORMAT_S8
) {
1948 intel_miptree_map_s8(intel
, mt
, map
, level
, slice
);
1949 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
1950 !(mode
& BRW_MAP_DIRECT_BIT
)) {
1951 intel_miptree_map_etc(intel
, mt
, map
, level
, slice
);
1952 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
1953 intel_miptree_map_depthstencil(intel
, mt
, map
, level
, slice
);
1955 /* See intel_miptree_blit() for details on the 32k pitch limit. */
1956 else if (intel
->has_llc
&&
1957 !(mode
& GL_MAP_WRITE_BIT
) &&
1959 (mt
->region
->tiling
== I915_TILING_X
||
1960 (intel
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
1961 mt
->region
->pitch
< 32768) {
1962 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
1963 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
1964 mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
1965 assert(mt
->region
->pitch
< 32768);
1966 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
1968 intel_miptree_map_gtt(intel
, mt
, map
, level
, slice
);
1971 *out_ptr
= map
->ptr
;
1972 *out_stride
= map
->stride
;
1974 if (map
->ptr
== NULL
)
1975 intel_miptree_release_map(mt
, level
, slice
);
1979 intel_miptree_unmap_singlesample(struct intel_context
*intel
,
1980 struct intel_mipmap_tree
*mt
,
1984 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
1986 assert(mt
->num_samples
<= 1);
1991 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
1992 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
1994 if (mt
->format
== MESA_FORMAT_S8
) {
1995 intel_miptree_unmap_s8(intel
, mt
, map
, level
, slice
);
1996 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
1997 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
1998 intel_miptree_unmap_etc(intel
, mt
, map
, level
, slice
);
1999 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2000 intel_miptree_unmap_depthstencil(intel
, mt
, map
, level
, slice
);
2001 } else if (map
->mt
) {
2002 intel_miptree_unmap_blit(intel
, mt
, map
, level
, slice
);
2004 intel_miptree_unmap_gtt(intel
, mt
, map
, level
, slice
);
2007 intel_miptree_release_map(mt
, level
, slice
);
2011 intel_miptree_map_multisample(struct intel_context
*intel
,
2012 struct intel_mipmap_tree
*mt
,
2023 struct intel_miptree_map
*map
;
2025 assert(mt
->num_samples
> 1);
2027 /* Only flat, renderbuffer-like miptrees are supported. */
2028 if (mt
->target
!= GL_TEXTURE_2D
||
2029 mt
->first_level
!= 0 ||
2030 mt
->last_level
!= 0) {
2031 _mesa_problem(&intel
->ctx
, "attempt to map a multisample miptree for "
2032 "which (target, first_level, last_level != "
2033 "(GL_TEXTURE_2D, 0, 0)");
2037 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2041 if (!mt
->singlesample_mt
) {
2042 mt
->singlesample_mt
=
2043 intel_miptree_create_for_renderbuffer(intel
,
2046 mt
->logical_height0
,
2048 if (!mt
->singlesample_mt
)
2051 map
->singlesample_mt_is_tmp
= true;
2052 mt
->need_downsample
= true;
2055 intel_miptree_downsample(intel
, mt
);
2056 intel_miptree_map_singlesample(intel
, mt
->singlesample_mt
,
2060 out_ptr
, out_stride
);
2064 intel_miptree_release_map(mt
, level
, slice
);
2070 intel_miptree_unmap_multisample(struct intel_context
*intel
,
2071 struct intel_mipmap_tree
*mt
,
2075 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2077 assert(mt
->num_samples
> 1);
2082 intel_miptree_unmap_singlesample(intel
, mt
->singlesample_mt
, level
, slice
);
2084 mt
->need_downsample
= false;
2085 if (map
->mode
& GL_MAP_WRITE_BIT
)
2086 intel_miptree_upsample(intel
, mt
);
2088 if (map
->singlesample_mt_is_tmp
)
2089 intel_miptree_release(&mt
->singlesample_mt
);
2091 intel_miptree_release_map(mt
, level
, slice
);
2095 intel_miptree_map(struct intel_context
*intel
,
2096 struct intel_mipmap_tree
*mt
,
2107 if (mt
->num_samples
<= 1)
2108 intel_miptree_map_singlesample(intel
, mt
,
2112 out_ptr
, out_stride
);
2114 intel_miptree_map_multisample(intel
, mt
,
2118 out_ptr
, out_stride
);
2122 intel_miptree_unmap(struct intel_context
*intel
,
2123 struct intel_mipmap_tree
*mt
,
2127 if (mt
->num_samples
<= 1)
2128 intel_miptree_unmap_singlesample(intel
, mt
, level
, slice
);
2130 intel_miptree_unmap_multisample(intel
, mt
, level
, slice
);