1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_context.h"
34 #include "intel_mipmap_tree.h"
35 #include "intel_regions.h"
36 #include "intel_resolve_map.h"
37 #include "intel_tex_layout.h"
38 #include "intel_tex.h"
39 #include "intel_blit.h"
42 #include "brw_blorp.h"
45 #include "main/enums.h"
46 #include "main/formats.h"
47 #include "main/glformats.h"
48 #include "main/texcompress_etc.h"
49 #include "main/teximage.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 target_to_target(GLenum target
)
57 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
:
58 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB
:
59 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB
:
60 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB
:
61 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB
:
62 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB
:
63 return GL_TEXTURE_CUBE_MAP_ARB
;
71 * Determine which MSAA layout should be used by the MSAA surface being
72 * created, based on the chip generation and the surface type.
74 static enum intel_msaa_layout
75 compute_msaa_layout(struct intel_context
*intel
, gl_format format
, GLenum target
)
77 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
79 return INTEL_MSAA_LAYOUT_IMS
;
81 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
82 switch (_mesa_get_format_base_format(format
)) {
83 case GL_DEPTH_COMPONENT
:
84 case GL_STENCIL_INDEX
:
85 case GL_DEPTH_STENCIL
:
86 return INTEL_MSAA_LAYOUT_IMS
;
88 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
90 * This field must be set to 0 for all SINT MSRTs when all RT channels
93 * In practice this means that we have to disable MCS for all signed
94 * integer MSAA buffers. The alternative, to disable MCS only when one
95 * of the render target channels is disabled, is impractical because it
96 * would require converting between CMS and UMS MSAA layouts on the fly,
99 if (_mesa_get_format_datatype(format
) == GL_INT
) {
100 /* TODO: is this workaround needed for future chipsets? */
101 assert(intel
->gen
== 7);
102 return INTEL_MSAA_LAYOUT_UMS
;
104 /* For now, if we're going to be texturing from this surface,
105 * force UMS, so that the shader doesn't have to do different things
106 * based on whether there's a multisample control surface needing sampled first.
107 * We can't just blindly read the MCS surface in all cases because:
109 * From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
111 * If this field is disabled and the sampling engine <ld_mcs> message
112 * is issued on this surface, the MCS surface may be accessed. Software
113 * must ensure that the surface is defined to avoid GTT errors.
115 if (target
== GL_TEXTURE_2D_MULTISAMPLE
||
116 target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
117 return INTEL_MSAA_LAYOUT_UMS
;
119 return INTEL_MSAA_LAYOUT_CMS
;
127 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
128 * scaled-down bitfield representation of the color buffer which is capable of
129 * recording when blocks of the color buffer are equal to the clear value.
130 * This function returns the block size that will be used by the MCS buffer
131 * corresponding to a certain color miptree.
133 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
134 * beneath the "Fast Color Clear" bullet (p327):
136 * The following table describes the RT alignment
150 * This alignment has the following uses:
152 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
153 * buffer contains 128 blocks horizontally and 256 blocks vertically.
155 * - For figuring out alignment restrictions for a fast clear operation. Fast
156 * clear operations must always clear aligned multiples of 16 blocks
157 * horizontally and 32 blocks vertically.
159 * - For scaling down the coordinates sent through the render pipeline during
160 * a fast clear. X coordinates must be scaled down by 8 times the block
161 * width, and Y coordinates by 16 times the block height.
163 * - For scaling down the coordinates sent through the render pipeline during
164 * a "Render Target Resolve" operation. X coordinates must be scaled down
165 * by half the block width, and Y coordinates by half the block height.
168 intel_get_non_msrt_mcs_alignment(struct intel_context
*intel
,
169 struct intel_mipmap_tree
*mt
,
170 unsigned *width_px
, unsigned *height
)
172 switch (mt
->region
->tiling
) {
174 assert(!"Non-MSRT MCS requires X or Y tiling");
175 /* In release builds, fall through */
177 *width_px
= 32 / mt
->cpp
;
181 *width_px
= 64 / mt
->cpp
;
188 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
191 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
192 * beneath the "Fast Color Clear" bullet (p326):
194 * - Support is limited to tiled render targets.
195 * - Support is for non-mip-mapped and non-array surface types only.
197 * And then later, on p327:
199 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
203 intel_is_non_msrt_mcs_buffer_supported(struct intel_context
*intel
,
204 struct intel_mipmap_tree
*mt
)
207 /* MCS is not supported on the i915 (pre-Gen4) driver */
210 struct brw_context
*brw
= brw_context(&intel
->ctx
);
212 /* MCS support does not exist prior to Gen7 */
216 /* MCS is only supported for color buffers */
217 switch (_mesa_get_format_base_format(mt
->format
)) {
218 case GL_DEPTH_COMPONENT
:
219 case GL_DEPTH_STENCIL
:
220 case GL_STENCIL_INDEX
:
224 if (mt
->region
->tiling
!= I915_TILING_X
&&
225 mt
->region
->tiling
!= I915_TILING_Y
)
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
231 if (mt
->physical_depth0
!= 1)
234 /* There's no point in using an MCS buffer if the surface isn't in a
237 if (!brw
->format_supported_as_render_target
[mt
->format
])
246 * @param for_bo Indicates that the caller is
247 * intel_miptree_create_for_bo(). If true, then do not create
250 struct intel_mipmap_tree
*
251 intel_miptree_create_layout(struct intel_context
*intel
,
262 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
264 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
265 _mesa_lookup_enum_by_nr(target
),
266 _mesa_get_format_name(format
),
267 first_level
, last_level
, mt
);
269 mt
->target
= target_to_target(target
);
271 mt
->first_level
= first_level
;
272 mt
->last_level
= last_level
;
273 mt
->logical_width0
= width0
;
274 mt
->logical_height0
= height0
;
275 mt
->logical_depth0
= depth0
;
277 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
280 /* The cpp is bytes per (1, blockheight)-sized block for compressed
281 * textures. This is why you'll see divides by blockheight all over
284 _mesa_get_format_block_size(format
, &bw
, &bh
);
285 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
286 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
288 mt
->num_samples
= num_samples
;
289 mt
->compressed
= _mesa_is_format_compressed(format
);
290 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
293 if (num_samples
> 1) {
294 /* Adjust width/height/depth for MSAA */
295 mt
->msaa_layout
= compute_msaa_layout(intel
, format
, mt
->target
);
296 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
297 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
299 * "Any of the other messages (sample*, LOD, load4) used with a
300 * (4x) multisampled surface will in-effect sample a surface with
301 * double the height and width as that indicated in the surface
302 * state. Each pixel position on the original-sized surface is
303 * replaced with a 2x2 of samples with the following arrangement:
308 * Thus, when sampling from a multisampled texture, it behaves as
309 * though the layout in memory for (x,y,sample) is:
311 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
312 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
314 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
315 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
317 * However, the actual layout of multisampled data in memory is:
319 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
320 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
322 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
323 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
325 * This pattern repeats for each 2x2 pixel block.
327 * As a result, when calculating the size of our 4-sample buffer for
328 * an odd width or height, we have to align before scaling up because
329 * sample 3 is in that bottom right 2x2 block.
331 switch (num_samples
) {
333 width0
= ALIGN(width0
, 2) * 2;
334 height0
= ALIGN(height0
, 2) * 2;
337 width0
= ALIGN(width0
, 2) * 4;
338 height0
= ALIGN(height0
, 2) * 2;
341 /* num_samples should already have been quantized to 0, 1, 4, or
347 /* Non-interleaved */
348 depth0
*= num_samples
;
352 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
355 switch (mt
->msaa_layout
) {
356 case INTEL_MSAA_LAYOUT_NONE
:
357 case INTEL_MSAA_LAYOUT_IMS
:
358 mt
->array_spacing_lod0
= false;
360 case INTEL_MSAA_LAYOUT_UMS
:
361 case INTEL_MSAA_LAYOUT_CMS
:
362 mt
->array_spacing_lod0
= true;
366 if (target
== GL_TEXTURE_CUBE_MAP
) {
371 mt
->physical_width0
= width0
;
372 mt
->physical_height0
= height0
;
373 mt
->physical_depth0
= depth0
;
376 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
377 (intel
->must_use_separate_stencil
||
378 (intel
->has_separate_stencil
&&
379 intel
->vtbl
.is_hiz_depth_format(intel
, format
)))) {
380 mt
->stencil_mt
= intel_miptree_create(intel
,
390 INTEL_MIPTREE_TILING_ANY
);
391 if (!mt
->stencil_mt
) {
392 intel_miptree_release(&mt
);
396 /* Fix up the Z miptree format for how we're splitting out separate
397 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
399 if (mt
->format
== MESA_FORMAT_S8_Z24
) {
400 mt
->format
= MESA_FORMAT_X8_Z24
;
401 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_X24S8
) {
402 mt
->format
= MESA_FORMAT_Z32_FLOAT
;
405 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
406 _mesa_get_format_name(mt
->format
));
410 intel_get_texture_alignment_unit(intel
, mt
->format
,
411 &mt
->align_w
, &mt
->align_h
);
416 i945_miptree_layout(mt
);
418 i915_miptree_layout(mt
);
420 brw_miptree_layout(intel
, mt
);
427 * \brief Helper function for intel_miptree_create().
430 intel_miptree_choose_tiling(struct intel_context
*intel
,
433 uint32_t num_samples
,
434 enum intel_miptree_tiling_mode requested
,
435 struct intel_mipmap_tree
*mt
)
438 if (format
== MESA_FORMAT_S8
) {
439 /* The stencil buffer is W tiled. However, we request from the kernel a
440 * non-tiled buffer because the GTT is incapable of W fencing.
442 return I915_TILING_NONE
;
445 /* Some usages may want only one type of tiling, like depth miptrees (Y
446 * tiled), or temporary BOs for uploading data once (linear).
449 case INTEL_MIPTREE_TILING_ANY
:
451 case INTEL_MIPTREE_TILING_Y
:
452 return I915_TILING_Y
;
453 case INTEL_MIPTREE_TILING_NONE
:
454 return I915_TILING_NONE
;
457 if (num_samples
> 1) {
458 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
461 * [DevSNB+]: For multi-sample render targets, this field must be
462 * 1. MSRTs can only be tiled.
464 * Our usual reason for preferring X tiling (fast blits using the
465 * blitting engine) doesn't apply to MSAA, since we'll generally be
466 * downsampling or upsampling when blitting between the MSAA buffer
467 * and another buffer, and the blitting engine doesn't support that.
468 * So use Y tiling, since it makes better use of the cache.
470 return I915_TILING_Y
;
473 GLenum base_format
= _mesa_get_format_base_format(format
);
474 if (intel
->gen
>= 4 &&
475 (base_format
== GL_DEPTH_COMPONENT
||
476 base_format
== GL_DEPTH_STENCIL_EXT
))
477 return I915_TILING_Y
;
479 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
481 /* If the width is much smaller than a tile, don't bother tiling. */
482 if (minimum_pitch
< 64)
483 return I915_TILING_NONE
;
485 if (ALIGN(minimum_pitch
, 512) >= 32768) {
486 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
487 mt
->total_width
, mt
->total_height
);
488 return I915_TILING_NONE
;
491 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
493 return I915_TILING_X
;
495 return I915_TILING_Y
| I915_TILING_X
;
498 struct intel_mipmap_tree
*
499 intel_miptree_create(struct intel_context
*intel
,
507 bool expect_accelerated_upload
,
509 enum intel_miptree_tiling_mode requested_tiling
)
511 struct intel_mipmap_tree
*mt
;
512 gl_format tex_format
= format
;
513 gl_format etc_format
= MESA_FORMAT_NONE
;
514 GLuint total_width
, total_height
;
516 if (!intel
->is_baytrail
) {
518 case MESA_FORMAT_ETC1_RGB8
:
519 format
= MESA_FORMAT_RGBX8888_REV
;
521 case MESA_FORMAT_ETC2_RGB8
:
522 format
= MESA_FORMAT_RGBX8888_REV
;
524 case MESA_FORMAT_ETC2_SRGB8
:
525 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
526 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
527 format
= MESA_FORMAT_SARGB8
;
529 case MESA_FORMAT_ETC2_RGBA8_EAC
:
530 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
531 format
= MESA_FORMAT_RGBA8888_REV
;
533 case MESA_FORMAT_ETC2_R11_EAC
:
534 format
= MESA_FORMAT_R16
;
536 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
537 format
= MESA_FORMAT_SIGNED_R16
;
539 case MESA_FORMAT_ETC2_RG11_EAC
:
540 format
= MESA_FORMAT_GR1616
;
542 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
543 format
= MESA_FORMAT_SIGNED_GR1616
;
546 /* Non ETC1 / ETC2 format */
551 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
553 mt
= intel_miptree_create_layout(intel
, target
, format
,
554 first_level
, last_level
, width0
,
558 * pitch == 0 || height == 0 indicates the null texture
560 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
561 intel_miptree_release(&mt
);
565 total_width
= mt
->total_width
;
566 total_height
= mt
->total_height
;
568 if (format
== MESA_FORMAT_S8
) {
569 /* Align to size of W tile, 64x64. */
570 total_width
= ALIGN(total_width
, 64);
571 total_height
= ALIGN(total_height
, 64);
574 uint32_t tiling
= intel_miptree_choose_tiling(intel
, format
, width0
,
575 num_samples
, requested_tiling
,
577 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
579 mt
->etc_format
= etc_format
;
580 mt
->region
= intel_region_alloc(intel
->intelScreen
,
581 y_or_x
? I915_TILING_Y
: tiling
,
585 expect_accelerated_upload
);
587 /* If the region is too large to fit in the aperture, we need to use the
588 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
589 * so we need to fall back to X.
591 if (y_or_x
&& mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
592 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
593 mt
->total_width
, mt
->total_height
);
594 intel_region_release(&mt
->region
);
596 mt
->region
= intel_region_alloc(intel
->intelScreen
,
601 expect_accelerated_upload
);
607 intel_miptree_release(&mt
);
612 /* If this miptree is capable of supporting fast color clears, set
613 * mcs_state appropriately to ensure that fast clears will occur.
614 * Allocation of the MCS miptree will be deferred until the first fast
615 * clear actually occurs.
617 if (intel_is_non_msrt_mcs_buffer_supported(intel
, mt
))
618 mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
624 struct intel_mipmap_tree
*
625 intel_miptree_create_for_bo(struct intel_context
*intel
,
634 struct intel_mipmap_tree
*mt
;
636 struct intel_region
*region
= calloc(1, sizeof(*region
));
640 /* Nothing will be able to use this miptree with the BO if the offset isn't
643 if (tiling
!= I915_TILING_NONE
)
644 assert(offset
% 4096 == 0);
646 /* miptrees can't handle negative pitch. If you need flipping of images,
647 * that's outside of the scope of the mt.
651 mt
= intel_miptree_create_layout(intel
, GL_TEXTURE_2D
, format
,
654 true, 0 /* num_samples */);
658 region
->cpp
= mt
->cpp
;
659 region
->width
= width
;
660 region
->height
= height
;
661 region
->pitch
= pitch
;
662 region
->refcount
= 1;
663 drm_intel_bo_reference(bo
);
665 region
->tiling
= tiling
;
675 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree.
677 * For a multisample DRI2 buffer, this wraps the given region with
678 * a singlesample miptree, then creates a multisample miptree into which the
679 * singlesample miptree is embedded as a child.
681 struct intel_mipmap_tree
*
682 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
683 unsigned dri_attachment
,
685 uint32_t num_samples
,
686 struct intel_region
*region
)
688 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
689 struct intel_mipmap_tree
*multisample_mt
= NULL
;
691 /* Only the front and back buffers, which are color buffers, are shared
694 assert(dri_attachment
== __DRI_BUFFER_BACK_LEFT
||
695 dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
696 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
);
697 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
698 _mesa_get_format_base_format(format
) == GL_RGBA
);
700 singlesample_mt
= intel_miptree_create_for_bo(intel
,
708 if (!singlesample_mt
)
710 singlesample_mt
->region
->name
= region
->name
;
713 /* If this miptree is capable of supporting fast color clears, set
714 * mcs_state appropriately to ensure that fast clears will occur.
715 * Allocation of the MCS miptree will be deferred until the first fast
716 * clear actually occurs.
718 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
719 singlesample_mt
->mcs_state
= INTEL_MCS_STATE_RESOLVED
;
722 if (num_samples
== 0)
723 return singlesample_mt
;
725 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
730 if (!multisample_mt
) {
731 intel_miptree_release(&singlesample_mt
);
735 multisample_mt
->singlesample_mt
= singlesample_mt
;
736 multisample_mt
->need_downsample
= false;
738 if (intel
->is_front_buffer_rendering
&&
739 (dri_attachment
== __DRI_BUFFER_FRONT_LEFT
||
740 dri_attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
)) {
741 intel_miptree_upsample(intel
, multisample_mt
);
744 return multisample_mt
;
747 struct intel_mipmap_tree
*
748 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
752 uint32_t num_samples
)
754 struct intel_mipmap_tree
*mt
;
758 mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, format
, 0, 0,
759 width
, height
, depth
, true, num_samples
,
760 INTEL_MIPTREE_TILING_ANY
);
764 if (intel
->vtbl
.is_hiz_depth_format(intel
, format
)) {
765 ok
= intel_miptree_alloc_hiz(intel
, mt
);
770 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
771 ok
= intel_miptree_alloc_mcs(intel
, mt
, num_samples
);
779 intel_miptree_release(&mt
);
784 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
785 struct intel_mipmap_tree
*src
)
790 intel_miptree_release(dst
);
794 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
802 intel_miptree_release(struct intel_mipmap_tree
**mt
)
807 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
808 if (--(*mt
)->refcount
<= 0) {
811 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
813 intel_region_release(&((*mt
)->region
));
814 intel_miptree_release(&(*mt
)->stencil_mt
);
815 intel_miptree_release(&(*mt
)->hiz_mt
);
817 intel_miptree_release(&(*mt
)->mcs_mt
);
819 intel_miptree_release(&(*mt
)->singlesample_mt
);
820 intel_resolve_map_clear(&(*mt
)->hiz_map
);
822 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
823 free((*mt
)->level
[i
].slice
);
832 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
833 int *width
, int *height
, int *depth
)
835 switch (image
->TexObject
->Target
) {
836 case GL_TEXTURE_1D_ARRAY
:
837 *width
= image
->Width
;
839 *depth
= image
->Height
;
842 *width
= image
->Width
;
843 *height
= image
->Height
;
844 *depth
= image
->Depth
;
850 * Can the image be pulled into a unified mipmap tree? This mirrors
851 * the completeness test in a lot of ways.
853 * Not sure whether I want to pass gl_texture_image here.
856 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
857 struct gl_texture_image
*image
)
859 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
860 GLuint level
= intelImage
->base
.Base
.Level
;
861 int width
, height
, depth
;
863 /* glTexImage* choose the texture object based on the target passed in, and
864 * objects can't change targets over their lifetimes, so this should be
867 assert(target_to_target(image
->TexObject
->Target
) == mt
->target
);
869 gl_format mt_format
= mt
->format
;
870 if (mt
->format
== MESA_FORMAT_X8_Z24
&& mt
->stencil_mt
)
871 mt_format
= MESA_FORMAT_S8_Z24
;
872 if (mt
->format
== MESA_FORMAT_Z32_FLOAT
&& mt
->stencil_mt
)
873 mt_format
= MESA_FORMAT_Z32_FLOAT_X24S8
;
874 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
875 mt_format
= mt
->etc_format
;
877 if (image
->TexFormat
!= mt_format
)
880 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
882 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
885 /* Test image dimensions against the base level image adjusted for
886 * minification. This will also catch images not present in the
887 * tree, changed targets, etc.
889 if (mt
->target
== GL_TEXTURE_2D_MULTISAMPLE
||
890 mt
->target
== GL_TEXTURE_2D_MULTISAMPLE_ARRAY
) {
891 /* nonzero level here is always bogus */
894 if (width
!= mt
->logical_width0
||
895 height
!= mt
->logical_height0
||
896 depth
!= mt
->logical_depth0
) {
901 /* all normal textures, renderbuffers, etc */
902 if (width
!= mt
->level
[level
].width
||
903 height
!= mt
->level
[level
].height
||
904 depth
!= mt
->level
[level
].depth
) {
909 if (image
->NumSamples
!= mt
->num_samples
)
917 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
920 GLuint w
, GLuint h
, GLuint d
)
922 mt
->level
[level
].width
= w
;
923 mt
->level
[level
].height
= h
;
924 mt
->level
[level
].depth
= d
;
925 mt
->level
[level
].level_x
= x
;
926 mt
->level
[level
].level_y
= y
;
928 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__
,
929 level
, w
, h
, d
, x
, y
);
931 assert(mt
->level
[level
].slice
== NULL
);
933 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
934 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
935 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
940 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
941 GLuint level
, GLuint img
,
944 if (img
== 0 && level
== 0)
945 assert(x
== 0 && y
== 0);
947 assert(img
< mt
->level
[level
].depth
);
949 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
950 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
952 DBG("%s level %d img %d pos %d,%d\n",
953 __FUNCTION__
, level
, img
,
954 mt
->level
[level
].slice
[img
].x_offset
,
955 mt
->level
[level
].slice
[img
].y_offset
);
959 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
960 GLuint level
, GLuint slice
,
961 GLuint
*x
, GLuint
*y
)
963 assert(slice
< mt
->level
[level
].depth
);
965 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
966 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
970 * Rendering with tiled buffers requires that the base address of the buffer
971 * be aligned to a page boundary. For renderbuffers, and sometimes with
972 * textures, we may want the surface to point at a texture image level that
973 * isn't at a page boundary.
975 * This function returns an appropriately-aligned base offset
976 * according to the tiling restrictions, plus any required x/y offset
980 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
981 GLuint level
, GLuint slice
,
985 struct intel_region
*region
= mt
->region
;
987 uint32_t mask_x
, mask_y
;
989 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
990 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
992 *tile_x
= x
& mask_x
;
993 *tile_y
= y
& mask_y
;
995 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
1000 intel_miptree_copy_slice_sw(struct intel_context
*intel
,
1001 struct intel_mipmap_tree
*dst_mt
,
1002 struct intel_mipmap_tree
*src_mt
,
1009 int src_stride
, dst_stride
;
1010 int cpp
= dst_mt
->cpp
;
1012 intel_miptree_map(intel
, src_mt
,
1016 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1019 intel_miptree_map(intel
, dst_mt
,
1023 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1027 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1028 _mesa_get_format_name(src_mt
->format
),
1029 src_mt
, src
, src_stride
,
1030 _mesa_get_format_name(dst_mt
->format
),
1031 dst_mt
, dst
, dst_stride
,
1034 int row_size
= cpp
* width
;
1035 if (src_stride
== row_size
&&
1036 dst_stride
== row_size
) {
1037 memcpy(dst
, src
, row_size
* height
);
1039 for (int i
= 0; i
< height
; i
++) {
1040 memcpy(dst
, src
, row_size
);
1046 intel_miptree_unmap(intel
, dst_mt
, level
, slice
);
1047 intel_miptree_unmap(intel
, src_mt
, level
, slice
);
1049 /* Don't forget to copy the stencil data over, too. We could have skipped
1050 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1051 * shuffling the two data sources in/out of temporary storage instead of
1052 * the direct mapping we get this way.
1054 if (dst_mt
->stencil_mt
) {
1055 assert(src_mt
->stencil_mt
);
1056 intel_miptree_copy_slice_sw(intel
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1057 level
, slice
, width
, height
);
1062 intel_miptree_copy_slice(struct intel_context
*intel
,
1063 struct intel_mipmap_tree
*dst_mt
,
1064 struct intel_mipmap_tree
*src_mt
,
1070 gl_format format
= src_mt
->format
;
1071 uint32_t width
= src_mt
->level
[level
].width
;
1072 uint32_t height
= src_mt
->level
[level
].height
;
1080 assert(depth
< src_mt
->level
[level
].depth
);
1081 assert(src_mt
->format
== dst_mt
->format
);
1083 if (dst_mt
->compressed
) {
1084 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1085 width
= ALIGN(width
, dst_mt
->align_w
);
1088 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1089 * below won't apply since we can't do the depth's Y tiling or the
1090 * stencil's W tiling in the blitter.
1092 if (src_mt
->stencil_mt
) {
1093 intel_miptree_copy_slice_sw(intel
,
1100 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1101 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1102 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1104 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1105 _mesa_get_format_name(src_mt
->format
),
1106 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1107 _mesa_get_format_name(dst_mt
->format
),
1108 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1111 if (!intel_miptree_blit(intel
,
1112 src_mt
, level
, slice
, 0, 0, false,
1113 dst_mt
, level
, slice
, 0, 0, false,
1114 width
, height
, GL_COPY
)) {
1115 perf_debug("miptree validate blit for %s failed\n",
1116 _mesa_get_format_name(format
));
1118 intel_miptree_copy_slice_sw(intel
, dst_mt
, src_mt
, level
, slice
,
1124 * Copies the image's current data to the given miptree, and associates that
1125 * miptree with the image.
1127 * If \c invalidate is true, then the actual image data does not need to be
1128 * copied, but the image still needs to be associated to the new miptree (this
1129 * is set to true if we're about to clear the image).
1132 intel_miptree_copy_teximage(struct intel_context
*intel
,
1133 struct intel_texture_image
*intelImage
,
1134 struct intel_mipmap_tree
*dst_mt
,
1137 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1138 struct intel_texture_object
*intel_obj
=
1139 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1140 int level
= intelImage
->base
.Base
.Level
;
1141 int face
= intelImage
->base
.Base
.Face
;
1142 GLuint depth
= intelImage
->base
.Base
.Depth
;
1145 for (int slice
= 0; slice
< depth
; slice
++) {
1146 intel_miptree_copy_slice(intel
, dst_mt
, src_mt
, level
, face
, slice
);
1150 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1151 intel_obj
->needs_validate
= true;
1155 intel_miptree_alloc_mcs(struct intel_context
*intel
,
1156 struct intel_mipmap_tree
*mt
,
1159 assert(intel
->gen
>= 7); /* MCS only used on Gen7+ */
1163 assert(mt
->mcs_mt
== NULL
);
1165 /* Choose the correct format for the MCS buffer. All that really matters
1166 * is that we allocate the right buffer size, since we'll always be
1167 * accessing this miptree using MCS-specific hardware mechanisms, which
1168 * infer the correct format based on num_samples.
1171 switch (num_samples
) {
1173 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1176 format
= MESA_FORMAT_R8
;
1179 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1180 * for each sample, plus 8 padding bits).
1182 format
= MESA_FORMAT_R_UINT32
;
1185 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1189 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1191 * "The MCS surface must be stored as Tile Y."
1193 mt
->mcs_state
= INTEL_MCS_STATE_MSAA
;
1194 mt
->mcs_mt
= intel_miptree_create(intel
,
1200 mt
->logical_height0
,
1203 0 /* num_samples */,
1204 INTEL_MIPTREE_TILING_Y
);
1206 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1208 * When MCS buffer is enabled and bound to MSRT, it is required that it
1209 * is cleared prior to any rendering.
1211 * Since we don't use the MCS buffer for any purpose other than rendering,
1212 * it makes sense to just clear it immediately upon allocation.
1214 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1216 void *data
= intel_miptree_map_raw(intel
, mt
->mcs_mt
);
1217 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1218 intel_miptree_unmap_raw(intel
, mt
->mcs_mt
);
1226 intel_miptree_alloc_non_msrt_mcs(struct intel_context
*intel
,
1227 struct intel_mipmap_tree
*mt
)
1230 assert(!"MCS not supported on i915");
1233 assert(mt
->mcs_mt
== NULL
);
1235 /* The format of the MCS buffer is opaque to the driver; all that matters
1236 * is that we get its size and pitch right. We'll pretend that the format
1237 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1238 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1239 * the block width and then a further factor of 4. Since an MCS tile
1240 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1241 * we'll need to scale the height down by the block height and then a
1242 * further factor of 8.
1244 const gl_format format
= MESA_FORMAT_R_UINT32
;
1245 unsigned block_width_px
;
1246 unsigned block_height
;
1247 intel_get_non_msrt_mcs_alignment(intel
, mt
, &block_width_px
, &block_height
);
1248 unsigned width_divisor
= block_width_px
* 4;
1249 unsigned height_divisor
= block_height
* 8;
1250 unsigned mcs_width
=
1251 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1252 unsigned mcs_height
=
1253 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1254 assert(mt
->logical_depth0
== 1);
1255 mt
->mcs_mt
= intel_miptree_create(intel
,
1264 0 /* num_samples */,
1265 INTEL_MIPTREE_TILING_Y
);
1273 * Helper for intel_miptree_alloc_hiz() that sets
1274 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1275 * \c has_hiz was set.
1278 intel_miptree_slice_enable_hiz(struct intel_context
*intel
,
1279 struct intel_mipmap_tree
*mt
,
1285 if (intel
->is_haswell
) {
1286 /* Disable HiZ for some slices to work around a hardware bug.
1288 * Haswell hardware fails to respect
1289 * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y when during HiZ
1290 * ambiguate operations. The failure is inconsistent and affected by
1291 * other GPU contexts. Running a heavy GPU workload in a separate
1292 * process causes the failure rate to drop to nearly 0.
1294 * To workaround the bug, we enable HiZ only when we can guarantee that
1295 * the Depth Coordinate Offset fields will be set to 0. The function
1296 * brw_get_depthstencil_tile_masks() is used to calculate the fields,
1297 * and the function is sometimes called in such a way that the presence
1298 * of an attached stencil buffer changes the fuction's return value.
1300 * The largest tile size considered by brw_get_depthstencil_tile_masks()
1301 * is that of the stencil buffer. Therefore, if this hiz slice's
1302 * corresponding depth slice has an offset that is aligned to the
1303 * stencil buffer tile size, 64x64 pixels, then
1304 * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y is set to 0.
1306 uint32_t depth_x_offset
= mt
->level
[level
].slice
[layer
].x_offset
;
1307 uint32_t depth_y_offset
= mt
->level
[level
].slice
[layer
].y_offset
;
1308 if ((depth_x_offset
& 63) || (depth_y_offset
& 63)) {
1313 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1320 intel_miptree_alloc_hiz(struct intel_context
*intel
,
1321 struct intel_mipmap_tree
*mt
)
1323 assert(mt
->hiz_mt
== NULL
);
1324 mt
->hiz_mt
= intel_miptree_create(intel
,
1330 mt
->logical_height0
,
1334 INTEL_MIPTREE_TILING_ANY
);
1339 /* Mark that all slices need a HiZ resolve. */
1340 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1341 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1342 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1343 if (!intel_miptree_slice_enable_hiz(intel
, mt
, level
, layer
))
1346 head
->next
= malloc(sizeof(*head
->next
));
1347 head
->next
->prev
= head
;
1348 head
->next
->next
= NULL
;
1351 head
->level
= level
;
1352 head
->layer
= layer
;
1353 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1361 * Does the miptree slice have hiz enabled?
1364 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1368 intel_miptree_check_level_layer(mt
, level
, layer
);
1369 return mt
->level
[level
].slice
[layer
].has_hiz
;
1373 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1377 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1380 intel_resolve_map_set(&mt
->hiz_map
,
1381 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1386 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1390 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1393 intel_resolve_map_set(&mt
->hiz_map
,
1394 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1398 intel_miptree_slice_resolve(struct intel_context
*intel
,
1399 struct intel_mipmap_tree
*mt
,
1402 enum gen6_hiz_op need
)
1404 intel_miptree_check_level_layer(mt
, level
, layer
);
1406 struct intel_resolve_map
*item
=
1407 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1409 if (!item
|| item
->need
!= need
)
1412 intel_hiz_exec(intel
, mt
, level
, layer
, need
);
1413 intel_resolve_map_remove(item
);
1418 intel_miptree_slice_resolve_hiz(struct intel_context
*intel
,
1419 struct intel_mipmap_tree
*mt
,
1423 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
1424 GEN6_HIZ_OP_HIZ_RESOLVE
);
1428 intel_miptree_slice_resolve_depth(struct intel_context
*intel
,
1429 struct intel_mipmap_tree
*mt
,
1433 return intel_miptree_slice_resolve(intel
, mt
, level
, layer
,
1434 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1438 intel_miptree_all_slices_resolve(struct intel_context
*intel
,
1439 struct intel_mipmap_tree
*mt
,
1440 enum gen6_hiz_op need
)
1442 bool did_resolve
= false;
1443 struct intel_resolve_map
*i
, *next
;
1445 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1447 if (i
->need
!= need
)
1450 intel_hiz_exec(intel
, mt
, i
->level
, i
->layer
, need
);
1451 intel_resolve_map_remove(i
);
1459 intel_miptree_all_slices_resolve_hiz(struct intel_context
*intel
,
1460 struct intel_mipmap_tree
*mt
)
1462 return intel_miptree_all_slices_resolve(intel
, mt
,
1463 GEN6_HIZ_OP_HIZ_RESOLVE
);
1467 intel_miptree_all_slices_resolve_depth(struct intel_context
*intel
,
1468 struct intel_mipmap_tree
*mt
)
1470 return intel_miptree_all_slices_resolve(intel
, mt
,
1471 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1476 intel_miptree_resolve_color(struct intel_context
*intel
,
1477 struct intel_mipmap_tree
*mt
)
1480 /* Fast color clear is not supported on the i915 (pre-Gen4) driver */
1482 switch (mt
->mcs_state
) {
1483 case INTEL_MCS_STATE_NONE
:
1484 case INTEL_MCS_STATE_MSAA
:
1485 case INTEL_MCS_STATE_RESOLVED
:
1486 /* No resolve needed */
1488 case INTEL_MCS_STATE_UNRESOLVED
:
1489 case INTEL_MCS_STATE_CLEAR
:
1490 brw_blorp_resolve_color(intel
, mt
);
1498 * Make it possible to share the region backing the given miptree with another
1499 * process or another miptree.
1501 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1502 * then discard the MCS buffer, if present. We also set the mcs_state to
1503 * INTEL_MCS_STATE_NONE to ensure that no MCS buffer gets allocated in the
1507 intel_miptree_make_shareable(struct intel_context
*intel
,
1508 struct intel_mipmap_tree
*mt
)
1511 /* Nothing needs to be done for I915 */
1515 /* MCS buffers are also used for multisample buffers, but we can't resolve
1516 * away a multisample MCS buffer because it's an integral part of how the
1517 * pixel data is stored. Fortunately this code path should never be
1518 * reached for multisample buffers.
1520 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1523 intel_miptree_resolve_color(intel
, mt
);
1524 intel_miptree_release(&mt
->mcs_mt
);
1525 mt
->mcs_state
= INTEL_MCS_STATE_NONE
;
1532 * \brief Get pointer offset into stencil buffer.
1534 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1535 * must decode the tile's layout in software.
1538 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1540 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1542 * Even though the returned offset is always positive, the return type is
1544 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1545 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1548 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1550 uint32_t tile_size
= 4096;
1551 uint32_t tile_width
= 64;
1552 uint32_t tile_height
= 64;
1553 uint32_t row_size
= 64 * stride
;
1555 uint32_t tile_x
= x
/ tile_width
;
1556 uint32_t tile_y
= y
/ tile_height
;
1558 /* The byte's address relative to the tile's base addres. */
1559 uint32_t byte_x
= x
% tile_width
;
1560 uint32_t byte_y
= y
% tile_height
;
1562 uintptr_t u
= tile_y
* row_size
1563 + tile_x
* tile_size
1564 + 512 * (byte_x
/ 8)
1566 + 32 * ((byte_y
/ 4) % 2)
1567 + 16 * ((byte_x
/ 4) % 2)
1568 + 8 * ((byte_y
/ 2) % 2)
1569 + 4 * ((byte_x
/ 2) % 2)
1574 /* adjust for bit6 swizzling */
1575 if (((byte_x
/ 8) % 2) == 1) {
1576 if (((byte_y
/ 8) % 2) == 0) {
1588 intel_miptree_updownsample(struct intel_context
*intel
,
1589 struct intel_mipmap_tree
*src
,
1590 struct intel_mipmap_tree
*dst
,
1600 brw_blorp_blit_miptrees(intel
,
1601 src
, 0 /* level */, 0 /* layer */,
1602 dst
, 0 /* level */, 0 /* layer */,
1607 false, false /*mirror x, y*/);
1609 if (src
->stencil_mt
) {
1610 brw_blorp_blit_miptrees(intel
,
1611 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1612 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1617 false, false /*mirror x, y*/);
1623 assert_is_flat(struct intel_mipmap_tree
*mt
)
1625 assert(mt
->target
== GL_TEXTURE_2D
);
1626 assert(mt
->first_level
== 0);
1627 assert(mt
->last_level
== 0);
1631 * \brief Downsample from mt to mt->singlesample_mt.
1633 * If the miptree needs no downsample, then skip.
1636 intel_miptree_downsample(struct intel_context
*intel
,
1637 struct intel_mipmap_tree
*mt
)
1639 /* Only flat, renderbuffer-like miptrees are supported. */
1642 if (!mt
->need_downsample
)
1644 intel_miptree_updownsample(intel
,
1645 mt
, mt
->singlesample_mt
,
1647 mt
->logical_height0
);
1648 mt
->need_downsample
= false;
1652 * \brief Upsample from mt->singlesample_mt to mt.
1654 * The upsample is done unconditionally.
1657 intel_miptree_upsample(struct intel_context
*intel
,
1658 struct intel_mipmap_tree
*mt
)
1660 /* Only flat, renderbuffer-like miptrees are supported. */
1662 assert(!mt
->need_downsample
);
1664 intel_miptree_updownsample(intel
,
1665 mt
->singlesample_mt
, mt
,
1667 mt
->logical_height0
);
1671 intel_miptree_map_raw(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
)
1673 /* CPU accesses to color buffers don't understand fast color clears, so
1674 * resolve any pending fast color clears before we map.
1676 intel_miptree_resolve_color(intel
, mt
);
1678 drm_intel_bo
*bo
= mt
->region
->bo
;
1680 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1681 if (drm_intel_bo_busy(bo
)) {
1682 perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
1686 intel_flush(&intel
->ctx
);
1688 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1689 drm_intel_gem_bo_map_gtt(bo
);
1691 drm_intel_bo_map(bo
, true);
1697 intel_miptree_unmap_raw(struct intel_context
*intel
,
1698 struct intel_mipmap_tree
*mt
)
1700 drm_intel_bo_unmap(mt
->region
->bo
);
1704 intel_miptree_map_gtt(struct intel_context
*intel
,
1705 struct intel_mipmap_tree
*mt
,
1706 struct intel_miptree_map
*map
,
1707 unsigned int level
, unsigned int slice
)
1709 unsigned int bw
, bh
;
1711 unsigned int image_x
, image_y
;
1715 /* For compressed formats, the stride is the number of bytes per
1716 * row of blocks. intel_miptree_get_image_offset() already does
1719 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1720 assert(y
% bh
== 0);
1723 base
= intel_miptree_map_raw(intel
, mt
) + mt
->offset
;
1728 /* Note that in the case of cube maps, the caller must have passed the
1729 * slice number referencing the face.
1731 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1735 map
->stride
= mt
->region
->pitch
;
1736 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1739 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1740 map
->x
, map
->y
, map
->w
, map
->h
,
1741 mt
, _mesa_get_format_name(mt
->format
),
1742 x
, y
, map
->ptr
, map
->stride
);
1746 intel_miptree_unmap_gtt(struct intel_context
*intel
,
1747 struct intel_mipmap_tree
*mt
,
1748 struct intel_miptree_map
*map
,
1752 intel_miptree_unmap_raw(intel
, mt
);
1756 intel_miptree_map_blit(struct intel_context
*intel
,
1757 struct intel_mipmap_tree
*mt
,
1758 struct intel_miptree_map
*map
,
1759 unsigned int level
, unsigned int slice
)
1761 map
->mt
= intel_miptree_create(intel
, GL_TEXTURE_2D
, mt
->format
,
1765 INTEL_MIPTREE_TILING_NONE
);
1767 fprintf(stderr
, "Failed to allocate blit temporary\n");
1770 map
->stride
= map
->mt
->region
->pitch
;
1772 if (!intel_miptree_blit(intel
,
1774 map
->x
, map
->y
, false,
1777 map
->w
, map
->h
, GL_COPY
)) {
1778 fprintf(stderr
, "Failed to blit\n");
1782 intel_batchbuffer_flush(intel
);
1783 map
->ptr
= intel_miptree_map_raw(intel
, map
->mt
);
1785 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1786 map
->x
, map
->y
, map
->w
, map
->h
,
1787 mt
, _mesa_get_format_name(mt
->format
),
1788 level
, slice
, map
->ptr
, map
->stride
);
1793 intel_miptree_release(&map
->mt
);
1799 intel_miptree_unmap_blit(struct intel_context
*intel
,
1800 struct intel_mipmap_tree
*mt
,
1801 struct intel_miptree_map
*map
,
1805 struct gl_context
*ctx
= &intel
->ctx
;
1807 intel_miptree_unmap_raw(intel
, map
->mt
);
1809 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1810 bool ok
= intel_miptree_blit(intel
,
1814 map
->x
, map
->y
, false,
1815 map
->w
, map
->h
, GL_COPY
);
1816 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1819 intel_miptree_release(&map
->mt
);
1823 intel_miptree_map_s8(struct intel_context
*intel
,
1824 struct intel_mipmap_tree
*mt
,
1825 struct intel_miptree_map
*map
,
1826 unsigned int level
, unsigned int slice
)
1828 map
->stride
= map
->w
;
1829 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1833 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1834 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1835 * invalidate is set, since we'll be writing the whole rectangle from our
1836 * temporary buffer back out.
1838 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1839 uint8_t *untiled_s8_map
= map
->ptr
;
1840 uint8_t *tiled_s8_map
= intel_miptree_map_raw(intel
, mt
);
1841 unsigned int image_x
, image_y
;
1843 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1845 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1846 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1847 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1848 x
+ image_x
+ map
->x
,
1849 y
+ image_y
+ map
->y
,
1850 intel
->has_swizzling
);
1851 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1855 intel_miptree_unmap_raw(intel
, mt
);
1857 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1858 map
->x
, map
->y
, map
->w
, map
->h
,
1859 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1861 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1862 map
->x
, map
->y
, map
->w
, map
->h
,
1863 mt
, map
->ptr
, map
->stride
);
1868 intel_miptree_unmap_s8(struct intel_context
*intel
,
1869 struct intel_mipmap_tree
*mt
,
1870 struct intel_miptree_map
*map
,
1874 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1875 unsigned int image_x
, image_y
;
1876 uint8_t *untiled_s8_map
= map
->ptr
;
1877 uint8_t *tiled_s8_map
= intel_miptree_map_raw(intel
, mt
);
1879 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1881 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1882 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1883 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1886 intel
->has_swizzling
);
1887 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1891 intel_miptree_unmap_raw(intel
, mt
);
1898 intel_miptree_map_etc(struct intel_context
*intel
,
1899 struct intel_mipmap_tree
*mt
,
1900 struct intel_miptree_map
*map
,
1904 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1905 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1906 assert(mt
->format
== MESA_FORMAT_RGBX8888_REV
);
1909 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1910 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1912 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1913 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1914 map
->w
, map
->h
, 1));
1915 map
->ptr
= map
->buffer
;
1919 intel_miptree_unmap_etc(struct intel_context
*intel
,
1920 struct intel_mipmap_tree
*mt
,
1921 struct intel_miptree_map
*map
,
1927 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1932 uint8_t *dst
= intel_miptree_map_raw(intel
, mt
)
1933 + image_y
* mt
->region
->pitch
1934 + image_x
* mt
->region
->cpp
;
1936 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1937 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1938 map
->ptr
, map
->stride
,
1941 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1942 map
->ptr
, map
->stride
,
1943 map
->w
, map
->h
, mt
->etc_format
);
1945 intel_miptree_unmap_raw(intel
, mt
);
1950 * Mapping function for packed depth/stencil miptrees backed by real separate
1951 * miptrees for depth and stencil.
1953 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1954 * separate from the depth buffer. Yet at the GL API level, we have to expose
1955 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1956 * be able to map that memory for texture storage and glReadPixels-type
1957 * operations. We give Mesa core that access by mallocing a temporary and
1958 * copying the data between the actual backing store and the temporary.
1961 intel_miptree_map_depthstencil(struct intel_context
*intel
,
1962 struct intel_mipmap_tree
*mt
,
1963 struct intel_miptree_map
*map
,
1964 unsigned int level
, unsigned int slice
)
1966 struct intel_mipmap_tree
*z_mt
= mt
;
1967 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1968 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
1969 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1971 map
->stride
= map
->w
* packed_bpp
;
1972 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1976 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1977 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1978 * invalidate is set, since we'll be writing the whole rectangle from our
1979 * temporary buffer back out.
1981 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1982 uint32_t *packed_map
= map
->ptr
;
1983 uint8_t *s_map
= intel_miptree_map_raw(intel
, s_mt
);
1984 uint32_t *z_map
= intel_miptree_map_raw(intel
, z_mt
);
1985 unsigned int s_image_x
, s_image_y
;
1986 unsigned int z_image_x
, z_image_y
;
1988 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1989 &s_image_x
, &s_image_y
);
1990 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1991 &z_image_x
, &z_image_y
);
1993 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1994 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1995 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1996 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1999 intel
->has_swizzling
);
2000 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2001 (z_mt
->region
->pitch
/ 4) +
2002 (map_x
+ z_image_x
));
2003 uint8_t s
= s_map
[s_offset
];
2004 uint32_t z
= z_map
[z_offset
];
2006 if (map_z32f_x24s8
) {
2007 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2008 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2010 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2015 intel_miptree_unmap_raw(intel
, s_mt
);
2016 intel_miptree_unmap_raw(intel
, z_mt
);
2018 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2020 map
->x
, map
->y
, map
->w
, map
->h
,
2021 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2022 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2023 map
->ptr
, map
->stride
);
2025 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2026 map
->x
, map
->y
, map
->w
, map
->h
,
2027 mt
, map
->ptr
, map
->stride
);
2032 intel_miptree_unmap_depthstencil(struct intel_context
*intel
,
2033 struct intel_mipmap_tree
*mt
,
2034 struct intel_miptree_map
*map
,
2038 struct intel_mipmap_tree
*z_mt
= mt
;
2039 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2040 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z32_FLOAT
;
2042 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2043 uint32_t *packed_map
= map
->ptr
;
2044 uint8_t *s_map
= intel_miptree_map_raw(intel
, s_mt
);
2045 uint32_t *z_map
= intel_miptree_map_raw(intel
, z_mt
);
2046 unsigned int s_image_x
, s_image_y
;
2047 unsigned int z_image_x
, z_image_y
;
2049 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2050 &s_image_x
, &s_image_y
);
2051 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2052 &z_image_x
, &z_image_y
);
2054 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2055 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2056 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2057 x
+ s_image_x
+ map
->x
,
2058 y
+ s_image_y
+ map
->y
,
2059 intel
->has_swizzling
);
2060 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2061 (z_mt
->region
->pitch
/ 4) +
2064 if (map_z32f_x24s8
) {
2065 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2066 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2068 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2069 s_map
[s_offset
] = packed
>> 24;
2070 z_map
[z_offset
] = packed
;
2075 intel_miptree_unmap_raw(intel
, s_mt
);
2076 intel_miptree_unmap_raw(intel
, z_mt
);
2078 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2080 map
->x
, map
->y
, map
->w
, map
->h
,
2081 z_mt
, _mesa_get_format_name(z_mt
->format
),
2082 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2083 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2084 map
->ptr
, map
->stride
);
2091 * Create and attach a map to the miptree at (level, slice). Return the
2094 static struct intel_miptree_map
*
2095 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2104 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2109 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2110 mt
->level
[level
].slice
[slice
].map
= map
;
2122 * Release the map at (level, slice).
2125 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2129 struct intel_miptree_map
**map
;
2131 map
= &mt
->level
[level
].slice
[slice
].map
;
2137 intel_miptree_map_singlesample(struct intel_context
*intel
,
2138 struct intel_mipmap_tree
*mt
,
2149 struct intel_miptree_map
*map
;
2151 assert(mt
->num_samples
<= 1);
2153 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2160 intel_miptree_slice_resolve_depth(intel
, mt
, level
, slice
);
2161 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2162 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2165 if (mt
->format
== MESA_FORMAT_S8
) {
2166 intel_miptree_map_s8(intel
, mt
, map
, level
, slice
);
2167 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2168 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2169 intel_miptree_map_etc(intel
, mt
, map
, level
, slice
);
2170 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2171 intel_miptree_map_depthstencil(intel
, mt
, map
, level
, slice
);
2173 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2174 else if (intel
->has_llc
&&
2175 !(mode
& GL_MAP_WRITE_BIT
) &&
2177 (mt
->region
->tiling
== I915_TILING_X
||
2178 (intel
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2179 mt
->region
->pitch
< 32768) {
2180 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
2181 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2182 mt
->region
->bo
->size
>= intel
->max_gtt_map_object_size
) {
2183 assert(mt
->region
->pitch
< 32768);
2184 intel_miptree_map_blit(intel
, mt
, map
, level
, slice
);
2186 intel_miptree_map_gtt(intel
, mt
, map
, level
, slice
);
2189 *out_ptr
= map
->ptr
;
2190 *out_stride
= map
->stride
;
2192 if (map
->ptr
== NULL
)
2193 intel_miptree_release_map(mt
, level
, slice
);
2197 intel_miptree_unmap_singlesample(struct intel_context
*intel
,
2198 struct intel_mipmap_tree
*mt
,
2202 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2204 assert(mt
->num_samples
<= 1);
2209 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2210 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2212 if (mt
->format
== MESA_FORMAT_S8
) {
2213 intel_miptree_unmap_s8(intel
, mt
, map
, level
, slice
);
2214 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2215 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2216 intel_miptree_unmap_etc(intel
, mt
, map
, level
, slice
);
2217 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2218 intel_miptree_unmap_depthstencil(intel
, mt
, map
, level
, slice
);
2219 } else if (map
->mt
) {
2220 intel_miptree_unmap_blit(intel
, mt
, map
, level
, slice
);
2222 intel_miptree_unmap_gtt(intel
, mt
, map
, level
, slice
);
2225 intel_miptree_release_map(mt
, level
, slice
);
2229 intel_miptree_map_multisample(struct intel_context
*intel
,
2230 struct intel_mipmap_tree
*mt
,
2241 struct intel_miptree_map
*map
;
2243 assert(mt
->num_samples
> 1);
2245 /* Only flat, renderbuffer-like miptrees are supported. */
2246 if (mt
->target
!= GL_TEXTURE_2D
||
2247 mt
->first_level
!= 0 ||
2248 mt
->last_level
!= 0) {
2249 _mesa_problem(&intel
->ctx
, "attempt to map a multisample miptree for "
2250 "which (target, first_level, last_level != "
2251 "(GL_TEXTURE_2D, 0, 0)");
2255 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2259 if (!mt
->singlesample_mt
) {
2260 mt
->singlesample_mt
=
2261 intel_miptree_create_for_renderbuffer(intel
,
2264 mt
->logical_height0
,
2266 if (!mt
->singlesample_mt
)
2269 map
->singlesample_mt_is_tmp
= true;
2270 mt
->need_downsample
= true;
2273 intel_miptree_downsample(intel
, mt
);
2274 intel_miptree_map_singlesample(intel
, mt
->singlesample_mt
,
2278 out_ptr
, out_stride
);
2282 intel_miptree_release_map(mt
, level
, slice
);
2288 intel_miptree_unmap_multisample(struct intel_context
*intel
,
2289 struct intel_mipmap_tree
*mt
,
2293 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2295 assert(mt
->num_samples
> 1);
2300 intel_miptree_unmap_singlesample(intel
, mt
->singlesample_mt
, level
, slice
);
2302 mt
->need_downsample
= false;
2303 if (map
->mode
& GL_MAP_WRITE_BIT
)
2304 intel_miptree_upsample(intel
, mt
);
2306 if (map
->singlesample_mt_is_tmp
)
2307 intel_miptree_release(&mt
->singlesample_mt
);
2309 intel_miptree_release_map(mt
, level
, slice
);
2313 intel_miptree_map(struct intel_context
*intel
,
2314 struct intel_mipmap_tree
*mt
,
2325 if (mt
->num_samples
<= 1)
2326 intel_miptree_map_singlesample(intel
, mt
,
2330 out_ptr
, out_stride
);
2332 intel_miptree_map_multisample(intel
, mt
,
2336 out_ptr
, out_stride
);
2340 intel_miptree_unmap(struct intel_context
*intel
,
2341 struct intel_mipmap_tree
*mt
,
2345 if (mt
->num_samples
<= 1)
2346 intel_miptree_unmap_singlesample(intel
, mt
, level
, slice
);
2348 intel_miptree_unmap_multisample(intel
, mt
, level
, slice
);