1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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14 * The above copyright notice and this permission notice (including the
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18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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28 #ifndef INTEL_MIPMAP_TREE_H
29 #define INTEL_MIPMAP_TREE_H
33 #include "intel_regions.h"
39 /* A layer on top of the intel_regions code which adds:
41 * - Code to size and layout a region to hold a set of mipmaps.
42 * - Query to determine if a new image fits in an existing tree.
44 * - maybe able to remove refcounting from intel_region?
47 * The fixed mipmap layout of intel hardware where one offset
48 * specifies the position of all images in a mipmap hierachy
49 * complicates the implementation of GL texture image commands,
50 * compared to hardware where each image is specified with an
53 * In an ideal world, each texture object would be associated with a
54 * single bufmgr buffer or 2d intel_region, and all the images within
55 * the texture object would slot into the tree as they arrive. The
56 * reality can be a little messier, as images can arrive from the user
57 * with sizes that don't fit in the existing tree, or in an order
58 * where the tree layout cannot be guessed immediately.
60 * This structure encodes an idealized mipmap tree. The GL image
61 * commands build these where possible, otherwise store the images in
62 * temporary system buffers.
65 struct intel_texture_image
;
68 * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
69 * depthstencil-split-to-separate-stencil miptree, we'll normally make a
70 * tmeporary and recreate the kind of data requested by Mesa core, since we're
71 * satisfying some glGetTexImage() request or something.
73 * However, occasionally you want to actually map the miptree's current data
74 * without transcoding back. This flag to intel_miptree_map() gets you that.
76 #define BRW_MAP_DIRECT_BIT 0x80000000
78 struct intel_miptree_map
{
79 /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
81 /** Region of interest for the map. */
83 /** Possibly malloced temporary buffer for the mapping. */
85 /** Possible pointer to a temporary linear miptree for the mapping. */
86 struct intel_mipmap_tree
*mt
;
87 /** Pointer to the start of (map_x, map_y) returned by the mapping. */
89 /** Stride of the mapping. */
93 * intel_mipmap_tree::singlesample_mt is temporary storage that persists
94 * only for the duration of the map.
96 bool singlesample_mt_is_tmp
;
100 * Describes the location of each texture image within a texture region.
102 struct intel_mipmap_level
104 /** Offset to this miptree level, used in computing x_offset. */
106 /** Offset to this miptree level, used in computing y_offset. */
112 * \brief Number of 2D slices in this miplevel.
114 * The exact semantics of depth varies according to the texture target:
115 * - For GL_TEXTURE_CUBE_MAP, depth is 6.
116 * - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
117 * identical for all miplevels in the texture.
118 * - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
119 * value, like width and height, varies with miplevel.
120 * - For other texture types, depth is 1.
125 * \brief List of 2D images in this mipmap level.
127 * This may be a list of cube faces, array slices in 2D array texture, or
128 * layers in a 3D texture. The list's length is \c depth.
130 struct intel_mipmap_slice
{
132 * \name Offset to slice
135 * Hardware formats are so diverse that that there is no unified way to
136 * compute the slice offsets, so we store them in this table.
138 * The (x, y) offset to slice \c s at level \c l relative the miptrees
141 * x = mt->level[l].slice[s].x_offset
142 * y = mt->level[l].slice[s].y_offset
149 * Mapping information. Persistent for the duration of
150 * intel_miptree_map/unmap on this slice.
152 struct intel_miptree_map
*map
;
157 * Enum for keeping track of the different MSAA layouts supported by Gen7.
159 enum intel_msaa_layout
162 * Ordinary surface with no MSAA.
164 INTEL_MSAA_LAYOUT_NONE
,
167 * Interleaved Multisample Surface. The additional samples are
168 * accommodated by scaling up the width and the height of the surface so
169 * that all the samples corresponding to a pixel are located at nearby
172 INTEL_MSAA_LAYOUT_IMS
,
175 * Uncompressed Multisample Surface. The surface is stored as a 2D array,
176 * with array slice n containing all pixel data for sample n.
178 INTEL_MSAA_LAYOUT_UMS
,
181 * Compressed Multisample Surface. The surface is stored as in
182 * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
183 * (Multisample Control Surface) buffer. Each pixel in the MCS buffer
184 * indicates the mapping from sample number to array slice. This allows
185 * the common case (where all samples constituting a pixel have the same
186 * color value) to be stored efficiently by just using a single array
189 INTEL_MSAA_LAYOUT_CMS
,
195 * Enum for keeping track of the state of an MCS buffer associated with a
196 * miptree. This determines when fast clear related operations are needed.
198 * Fast clear works by deferring the memory writes that would be used to clear
199 * the buffer, so that instead of performing them at the time of the clear
200 * operation, the hardware automatically performs them at the time that the
201 * buffer is later accessed for rendering. The MCS buffer keeps track of
202 * which regions of the buffer still have pending clear writes.
204 * This enum keeps track of the driver's knowledge of the state of the MCS
207 * MCS buffers only exist on Gen7+.
212 * There is no MCS buffer for this miptree, and one should never be
215 INTEL_MCS_STATE_NONE
,
218 * An MCS buffer exists for this miptree, and it is used for MSAA purposes.
220 INTEL_MCS_STATE_MSAA
,
223 * No deferred clears are pending for this miptree, and the contents of the
224 * color buffer are entirely correct. An MCS buffer may or may not exist
225 * for this miptree. If it does exist, it is entirely in the "no deferred
226 * clears pending" state. If it does not exist, it will be created the
227 * first time a fast color clear is executed.
229 * In this state, the color buffer can be used for purposes other than
230 * rendering without needing a render target resolve.
232 INTEL_MCS_STATE_RESOLVED
,
235 * An MCS buffer exists for this miptree, and deferred clears are pending
236 * for some regions of the color buffer, as indicated by the MCS buffer.
237 * The contents of the color buffer are only correct for the regions where
238 * the MCS buffer doesn't indicate a deferred clear.
240 * In this state, a render target resolve must be performed before the
241 * color buffer can be used for purposes other than rendering.
243 INTEL_MCS_STATE_UNRESOLVED
,
246 * An MCS buffer exists for this miptree, and deferred clears are pending
247 * for the entire color buffer, and the contents of the MCS buffer reflect
248 * this. The contents of the color buffer are undefined.
250 * In this state, a render target resolve must be performed before the
251 * color buffer can be used for purposes other than rendering.
253 * If the client attempts to clear a buffer which is already in this state,
254 * the clear can be safely skipped, since the buffer is already clear.
256 INTEL_MCS_STATE_CLEAR
,
260 struct intel_mipmap_tree
262 /* Effectively the key:
267 * Generally, this is just the same as the gl_texture_image->TexFormat or
268 * gl_renderbuffer->Format.
270 * However, for textures and renderbuffers with packed depth/stencil formats
271 * on hardware where we want or need to use separate stencil, there will be
272 * two miptrees for storing the data. If the depthstencil texture or rb is
273 * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
274 * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
275 * MESA_FORMAT_X8_Z24.
277 * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
278 * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
282 /** This variable stores the value of ETC compressed texture format */
283 gl_format etc_format
;
286 * The X offset of each image in the miptree must be aligned to this. See
287 * the "Alignment Unit Size" section of the BSpec.
289 unsigned int align_w
;
290 unsigned int align_h
; /**< \see align_w */
296 * Level zero image dimensions. These dimensions correspond to the
297 * physical layout of data in memory. Accordingly, they account for the
298 * extra width, height, and or depth that must be allocated in order to
299 * accommodate multisample formats, and they account for the extra factor
300 * of 6 in depth that must be allocated in order to accommodate cubemap
303 GLuint physical_width0
, physical_height0
, physical_depth0
;
310 * Level zero image dimensions. These dimensions correspond to the
311 * logical width, height, and depth of the region as seen by client code.
312 * Accordingly, they do not account for the extra width, height, and/or
313 * depth that must be allocated in order to accommodate multisample
314 * formats, nor do they account for the extra factor of 6 in depth that
315 * must be allocated in order to accommodate cubemap textures.
317 uint32_t logical_width0
, logical_height0
, logical_depth0
;
320 * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
321 * if the surface only contains LOD 0, and hence no space is for LOD's
322 * other than 0 in between array slices.
324 * Corresponds to the surface_array_spacing bit in gen7_surface_state.
326 bool array_spacing_lod0
;
329 * MSAA layout used by this buffer.
331 enum intel_msaa_layout msaa_layout
;
333 /* Derived from the above:
338 /* Includes image offset tables:
340 struct intel_mipmap_level level
[MAX_TEXTURE_LEVELS
];
342 /* The data is held here:
344 struct intel_region
*region
;
346 /* Offset into region bo where miptree starts:
351 * \brief Singlesample miptree.
353 * This is used under two cases.
355 * --- Case 1: As persistent singlesample storage for multisample window
356 * system front and back buffers ---
358 * Suppose that the window system FBO was created with a multisample
359 * config. Let `back_irb` be the `intel_renderbuffer` for the FBO's back
360 * buffer. Then `back_irb` contains two miptrees: a parent multisample
361 * miptree (back_irb->mt) and a child singlesample miptree
362 * (back_irb->mt->singlesample_mt). The DRM buffer shared with DRI2
363 * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
364 * data. The singlesample miptree is created at the same time as and
365 * persists for the lifetime of its parent multisample miptree.
367 * When access to the singlesample data is needed, such as at
368 * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
369 * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
371 * This description of the back buffer applies analogously to the front
375 * --- Case 2: As temporary singlesample storage for mapping multisample
378 * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
379 * for which case 1 does not apply (that is, `mt` does not belong to
380 * a front or back buffer). Then `mt->singlesample_mt` is null at the
381 * start of the call. intel_miptree_map will create a temporary
382 * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
383 * `mt` to `mt->singlesample_mt` if necessary, then map
384 * `mt->singlesample_mt`. The temporary miptree is later deleted during
385 * intel_miptree_unmap.
387 struct intel_mipmap_tree
*singlesample_mt
;
390 * \brief A downsample is needed from this miptree to singlesample_mt.
392 bool need_downsample
;
395 * \brief Stencil miptree for depthstencil textures.
397 * This miptree is used for depthstencil textures and renderbuffers that
398 * require separate stencil. It always has the true copy of the stencil
399 * bits, regardless of mt->format.
401 * \see intel_miptree_map_depthstencil()
402 * \see intel_miptree_unmap_depthstencil()
404 struct intel_mipmap_tree
*stencil_mt
;
408 * \brief MCS miptree.
410 * This miptree contains the "multisample control surface", which stores
411 * the necessary information to implement compressed MSAA
412 * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
414 * NULL if no MCS miptree is in use for this surface.
416 struct intel_mipmap_tree
*mcs_mt
;
419 * MCS state for this buffer.
421 enum intel_mcs_state mcs_state
;
425 * The SURFACE_STATE bits associated with the last fast color clear to this
426 * color mipmap tree, if any.
428 * This value will only ever contain ones in bits 28-31, so it is safe to
429 * OR into dword 7 of SURFACE_STATE.
431 uint32_t fast_clear_color_value
;
433 /* These are also refcounted:
438 enum intel_miptree_tiling_mode
{
439 INTEL_MIPTREE_TILING_ANY
,
440 INTEL_MIPTREE_TILING_Y
,
441 INTEL_MIPTREE_TILING_NONE
,
445 intel_is_non_msrt_mcs_buffer_supported(struct intel_context
*intel
,
446 struct intel_mipmap_tree
*mt
);
449 intel_get_non_msrt_mcs_alignment(struct intel_context
*intel
,
450 struct intel_mipmap_tree
*mt
,
451 unsigned *width_px
, unsigned *height
);
454 intel_miptree_alloc_non_msrt_mcs(struct intel_context
*intel
,
455 struct intel_mipmap_tree
*mt
);
457 struct intel_mipmap_tree
*intel_miptree_create(struct intel_context
*intel
,
465 bool expect_accelerated_upload
,
467 enum intel_miptree_tiling_mode
);
469 struct intel_mipmap_tree
*
470 intel_miptree_create_layout(struct intel_context
*intel
,
481 struct intel_mipmap_tree
*
482 intel_miptree_create_for_bo(struct intel_context
*intel
,
491 struct intel_mipmap_tree
*
492 intel_miptree_create_for_dri2_buffer(struct intel_context
*intel
,
493 unsigned dri_attachment
,
495 uint32_t num_samples
,
496 struct intel_region
*region
);
499 * Create a miptree appropriate as the storage for a non-texture renderbuffer.
500 * The miptree has the following properties:
501 * - The target is GL_TEXTURE_2D.
502 * - There are no levels other than the base level 0.
505 struct intel_mipmap_tree
*
506 intel_miptree_create_for_renderbuffer(struct intel_context
*intel
,
510 uint32_t num_samples
);
512 /** \brief Assert that the level and layer are valid for the miptree. */
514 intel_miptree_check_level_layer(struct intel_mipmap_tree
*mt
,
518 assert(level
>= mt
->first_level
);
519 assert(level
<= mt
->last_level
);
520 assert(layer
< mt
->level
[level
].depth
);
523 int intel_miptree_pitch_align (struct intel_context
*intel
,
524 struct intel_mipmap_tree
*mt
,
528 void intel_miptree_reference(struct intel_mipmap_tree
**dst
,
529 struct intel_mipmap_tree
*src
);
531 void intel_miptree_release(struct intel_mipmap_tree
**mt
);
533 /* Check if an image fits an existing mipmap tree layout
535 bool intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
536 struct gl_texture_image
*image
);
539 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
540 GLuint level
, GLuint slice
,
541 GLuint
*x
, GLuint
*y
);
544 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
545 int *width
, int *height
, int *depth
);
548 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
549 GLuint level
, GLuint slice
,
553 void intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
556 GLuint w
, GLuint h
, GLuint d
);
558 void intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
560 GLuint img
, GLuint x
, GLuint y
);
563 intel_miptree_copy_teximage(struct intel_context
*intel
,
564 struct intel_texture_image
*intelImage
,
565 struct intel_mipmap_tree
*dst_mt
, bool invalidate
);
568 * Copy the stencil data from \c mt->stencil_mt->region to \c mt->region for
569 * the given miptree slice.
571 * \see intel_mipmap_tree::stencil_mt
574 intel_miptree_s8z24_scatter(struct intel_context
*intel
,
575 struct intel_mipmap_tree
*mt
,
580 * Copy the stencil data in \c mt->stencil_mt->region to \c mt->region for the
581 * given miptree slice.
583 * \see intel_mipmap_tree::stencil_mt
586 intel_miptree_s8z24_gather(struct intel_context
*intel
,
587 struct intel_mipmap_tree
*mt
,
592 intel_miptree_alloc_mcs(struct intel_context
*intel
,
593 struct intel_mipmap_tree
*mt
,
599 * Update the fast clear state for a miptree to indicate that it has been used
603 intel_miptree_used_for_rendering(struct intel_mipmap_tree
*mt
)
606 /* Nothing needs to be done for I915, since it doesn't support fast
610 /* If the buffer was previously in fast clear state, change it to
611 * unresolved state, since it won't be guaranteed to be clear after
614 if (mt
->mcs_state
== INTEL_MCS_STATE_CLEAR
)
615 mt
->mcs_state
= INTEL_MCS_STATE_UNRESOLVED
;
620 intel_miptree_resolve_color(struct intel_context
*intel
,
621 struct intel_mipmap_tree
*mt
);
624 intel_miptree_make_shareable(struct intel_context
*intel
,
625 struct intel_mipmap_tree
*mt
);
628 intel_miptree_downsample(struct intel_context
*intel
,
629 struct intel_mipmap_tree
*mt
);
632 intel_miptree_upsample(struct intel_context
*intel
,
633 struct intel_mipmap_tree
*mt
);
635 /* i915_mipmap_tree.c:
637 void i915_miptree_layout(struct intel_mipmap_tree
*mt
);
638 void i945_miptree_layout(struct intel_mipmap_tree
*mt
);
639 void brw_miptree_layout(struct intel_context
*intel
,
640 struct intel_mipmap_tree
*mt
);
642 void *intel_miptree_map_raw(struct intel_context
*intel
,
643 struct intel_mipmap_tree
*mt
);
645 void intel_miptree_unmap_raw(struct intel_context
*intel
,
646 struct intel_mipmap_tree
*mt
);
649 intel_miptree_map(struct intel_context
*intel
,
650 struct intel_mipmap_tree
*mt
,
662 intel_miptree_unmap(struct intel_context
*intel
,
663 struct intel_mipmap_tree
*mt
,