1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 /* Provide additional functionality on top of bufmgr buffers:
29 * - 2d semantics and blit operations
30 * - refcounting of buffers for multiple images in a buffer.
31 * - refcounting of buffer mappings.
32 * - some logic for moving the buffers to the best memory pools for
35 * Most of this is to make it easier to implement the fixed-layout
36 * mipmap tree required by intel hardware in the face of GL's
37 * programming interface where each image can be specifed in random
38 * order and it isn't clear what layout the tree should have until the
42 #include <sys/ioctl.h>
45 #include "main/hash.h"
46 #include "intel_context.h"
47 #include "intel_regions.h"
48 #include "intel_blit.h"
49 #include "intel_buffer_objects.h"
50 #include "intel_bufmgr.h"
51 #include "intel_batchbuffer.h"
53 #define FILE_DEBUG_FLAG DEBUG_REGION
55 /* This should be set to the maximum backtrace size desired.
56 * Set it to 0 to disable backtrace debugging.
58 #define DEBUG_BACKTRACE_SIZE 0
60 #if DEBUG_BACKTRACE_SIZE == 0
61 /* Use the standard debug output */
62 #define _DBG(...) DBG(__VA_ARGS__)
64 /* Use backtracing debug output */
65 #define _DBG(...) {debug_backtrace(); DBG(__VA_ARGS__);}
67 /* Backtracing debug support */
73 void *trace
[DEBUG_BACKTRACE_SIZE
];
74 char **strings
= NULL
;
78 traceSize
= backtrace(trace
, DEBUG_BACKTRACE_SIZE
);
79 strings
= backtrace_symbols(trace
, traceSize
);
80 if (strings
== NULL
) {
85 /* Spit out all the strings with a colon separator. Ignore
86 * the first, since we don't really care about the call
87 * to debug_backtrace() itself. Skip until the final "/" in
88 * the trace to avoid really long lines.
90 for (i
= 1; i
< traceSize
; i
++) {
91 char *p
= strings
[i
], *slash
= strings
[i
];
101 /* Free up the memory, and we're done */
107 static struct intel_region
*
108 intel_region_alloc_internal(struct intel_screen
*screen
,
110 GLuint width
, GLuint height
, GLuint pitch
,
111 uint32_t tiling
, drm_intel_bo
*buffer
)
113 struct intel_region
*region
;
115 region
= calloc(sizeof(*region
), 1);
120 region
->width
= width
;
121 region
->height
= height
;
122 region
->pitch
= pitch
;
123 region
->refcount
= 1;
125 region
->tiling
= tiling
;
127 _DBG("%s <-- %p\n", __FUNCTION__
, region
);
131 struct intel_region
*
132 intel_region_alloc(struct intel_screen
*screen
,
134 GLuint cpp
, GLuint width
, GLuint height
,
135 bool expect_accelerated_upload
)
137 drm_intel_bo
*buffer
;
138 unsigned long flags
= 0;
139 unsigned long aligned_pitch
;
140 struct intel_region
*region
;
142 if (expect_accelerated_upload
)
143 flags
|= BO_ALLOC_FOR_RENDER
;
145 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "region",
147 &tiling
, &aligned_pitch
, flags
);
151 region
= intel_region_alloc_internal(screen
, cpp
, width
, height
,
152 aligned_pitch
, tiling
, buffer
);
153 if (region
== NULL
) {
154 drm_intel_bo_unreference(buffer
);
162 intel_region_flink(struct intel_region
*region
, uint32_t *name
)
164 if (region
->name
== 0) {
165 if (drm_intel_bo_flink(region
->bo
, ®ion
->name
))
169 *name
= region
->name
;
174 struct intel_region
*
175 intel_region_alloc_for_handle(struct intel_screen
*screen
,
177 GLuint width
, GLuint height
, GLuint pitch
,
178 GLuint handle
, const char *name
)
180 struct intel_region
*region
;
181 drm_intel_bo
*buffer
;
183 uint32_t bit_6_swizzle
, tiling
;
185 buffer
= intel_bo_gem_create_from_name(screen
->bufmgr
, name
, handle
);
188 ret
= drm_intel_bo_get_tiling(buffer
, &tiling
, &bit_6_swizzle
);
190 fprintf(stderr
, "Couldn't get tiling of buffer %d (%s): %s\n",
191 handle
, name
, strerror(-ret
));
192 drm_intel_bo_unreference(buffer
);
196 region
= intel_region_alloc_internal(screen
, cpp
,
197 width
, height
, pitch
, tiling
, buffer
);
198 if (region
== NULL
) {
199 drm_intel_bo_unreference(buffer
);
203 region
->name
= handle
;
208 struct intel_region
*
209 intel_region_alloc_for_fd(struct intel_screen
*screen
,
211 GLuint width
, GLuint height
, GLuint pitch
,
213 int fd
, const char *name
)
215 struct intel_region
*region
;
216 drm_intel_bo
*buffer
;
218 uint32_t bit_6_swizzle
, tiling
;
220 buffer
= drm_intel_bo_gem_create_from_prime(screen
->bufmgr
, fd
, size
);
223 ret
= drm_intel_bo_get_tiling(buffer
, &tiling
, &bit_6_swizzle
);
225 fprintf(stderr
, "Couldn't get tiling of buffer (%s): %s\n",
226 name
, strerror(-ret
));
227 drm_intel_bo_unreference(buffer
);
231 region
= intel_region_alloc_internal(screen
, cpp
,
232 width
, height
, pitch
, tiling
, buffer
);
233 if (region
== NULL
) {
234 drm_intel_bo_unreference(buffer
);
242 intel_region_reference(struct intel_region
**dst
, struct intel_region
*src
)
244 _DBG("%s: %p(%d) -> %p(%d)\n", __FUNCTION__
,
245 *dst
, *dst
? (*dst
)->refcount
: 0, src
, src
? src
->refcount
: 0);
249 intel_region_release(dst
);
258 intel_region_release(struct intel_region
**region_handle
)
260 struct intel_region
*region
= *region_handle
;
262 if (region
== NULL
) {
263 _DBG("%s NULL\n", __FUNCTION__
);
267 _DBG("%s %p %d\n", __FUNCTION__
, region
, region
->refcount
- 1);
269 ASSERT(region
->refcount
> 0);
272 if (region
->refcount
== 0) {
273 drm_intel_bo_unreference(region
->bo
);
277 *region_handle
= NULL
;
281 * This function computes masks that may be used to select the bits of the X
282 * and Y coordinates that indicate the offset within a tile. If the region is
283 * untiled, the masks are set to 0.
286 intel_region_get_tile_masks(struct intel_region
*region
,
287 uint32_t *mask_x
, uint32_t *mask_y
,
288 bool map_stencil_as_y_tiled
)
290 int cpp
= region
->cpp
;
291 uint32_t tiling
= region
->tiling
;
293 if (map_stencil_as_y_tiled
)
294 tiling
= I915_TILING_Y
;
299 case I915_TILING_NONE
:
300 *mask_x
= *mask_y
= 0;
303 *mask_x
= 512 / cpp
- 1;
307 *mask_x
= 128 / cpp
- 1;
314 * Compute the offset (in bytes) from the start of the region to the given x
315 * and y coordinate. For tiled regions, caller must ensure that x and y are
316 * multiples of the tile size.
319 intel_region_get_aligned_offset(struct intel_region
*region
, uint32_t x
,
320 uint32_t y
, bool map_stencil_as_y_tiled
)
322 int cpp
= region
->cpp
;
323 uint32_t pitch
= region
->pitch
;
324 uint32_t tiling
= region
->tiling
;
326 if (map_stencil_as_y_tiled
) {
327 tiling
= I915_TILING_Y
;
329 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
330 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
331 * the resulting region is twice the pitch of the original region, since
332 * each row in the Y-tiled view corresponds to two rows in the actual
333 * W-tiled surface. So we need to correct the pitch before computing
342 case I915_TILING_NONE
:
343 return y
* pitch
+ x
* cpp
;
345 assert((x
% (512 / cpp
)) == 0);
346 assert((y
% 8) == 0);
347 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
349 assert((x
% (128 / cpp
)) == 0);
350 assert((y
% 32) == 0);
351 return y
* pitch
+ x
/ (128 / cpp
) * 4096;