1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 * Render unclipped vertex buffers by emitting vertices directly to
30 * dma buffers. Use strip/fan hardware acceleration where possible.
33 #include "main/glheader.h"
34 #include "main/context.h"
35 #include "main/macros.h"
36 #include "main/imports.h"
37 #include "main/mtypes.h"
38 #include "main/enums.h"
40 #include "math/m_xform.h"
42 #include "tnl/t_context.h"
43 #include "tnl/t_vertex.h"
44 #include "tnl/t_pipeline.h"
46 #include "intel_screen.h"
47 #include "intel_context.h"
48 #include "intel_tris.h"
49 #include "intel_batchbuffer.h"
50 #include "intel_reg.h"
53 * Render unclipped vertex buffers by emitting vertices directly to
54 * dma buffers. Use strip/fan hardware primitives where possible.
55 * Try to simulate missing primitives with indexed vertices.
57 #define HAVE_POINTS 0 /* Has it, but can't use because subpixel has to
58 * be adjusted for points on the INTEL/I845G
61 #define HAVE_LINE_STRIPS 1
62 #define HAVE_TRIANGLES 1
63 #define HAVE_TRI_STRIPS 1
64 #define HAVE_TRI_STRIP_1 0 /* has it, template can't use it yet */
65 #define HAVE_TRI_FANS 1
66 #define HAVE_POLYGONS 1
68 #define HAVE_QUAD_STRIPS 0
72 static uint32_t hw_prim
[GL_POLYGON
+ 1] = {
85 static const GLenum reduced_prim
[GL_POLYGON
+ 1] = {
98 static const int scale_prim
[GL_POLYGON
+ 1] = {
99 0, /* fallback case */
106 0, /* fallback case */
107 0, /* fallback case */
113 intelDmaPrimitive(struct intel_context
*intel
, GLenum prim
)
116 fprintf(stderr
, "%s %s\n", __FUNCTION__
, _mesa_lookup_enum_by_nr(prim
));
117 INTEL_FIREVERTICES(intel
);
118 intel
->vtbl
.reduced_primitive_state(intel
, reduced_prim
[prim
]);
119 intel_set_prim(intel
, hw_prim
[prim
]);
122 static INLINE GLuint
intel_get_vb_max(struct intel_context
*intel
)
126 if (intel
->intelScreen
->no_vbo
)
127 ret
= intel
->batch
->size
- 1500;
130 ret
/= (intel
->vertex_size
* 4);
134 static INLINE GLuint
intel_get_current_max(struct intel_context
*intel
)
137 if (intel
->intelScreen
->no_vbo
)
138 return intel_get_vb_max(intel
);
140 return (INTEL_VB_SIZE
- intel
->prim
.current_offset
) / (intel
->vertex_size
* 4);
143 #define LOCAL_VARS struct intel_context *intel = intel_context(ctx)
144 #define INIT( prim ) \
146 intelDmaPrimitive( intel, prim ); \
149 #define FLUSH() INTEL_FIREVERTICES(intel)
151 #define GET_SUBSEQUENT_VB_MAX_VERTS() intel_get_vb_max(intel)
152 #define GET_CURRENT_VB_MAX_VERTS() intel_get_current_max(intel)
154 #define ALLOC_VERTS(nr) intel_get_prim_space(intel, nr)
156 #define EMIT_VERTS( ctx, j, nr, buf ) \
157 _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf )
159 #define TAG(x) intel_##x
160 #include "tnl_dd/t_dd_dmatmp.h"
163 /**********************************************************************/
164 /* Render pipeline stage */
165 /**********************************************************************/
167 /* Heuristic to choose between the two render paths:
170 choose_render(struct intel_context
*intel
, struct vertex_buffer
*VB
)
172 int vertsz
= intel
->vertex_size
;
174 int cost_fallback
= 0;
178 int rprim
= intel
->reduced_primitive
;
181 for (i
= 0; i
< VB
->PrimitiveCount
; i
++) {
182 GLuint prim
= VB
->Primitive
[i
].mode
;
183 GLuint length
= VB
->Primitive
[i
].count
;
189 nr_rverts
+= length
* scale_prim
[prim
& PRIM_MODE_MASK
];
191 if (reduced_prim
[prim
& PRIM_MODE_MASK
] != rprim
) {
193 rprim
= reduced_prim
[prim
& PRIM_MODE_MASK
];
197 /* One point for each generated primitive:
199 cost_render
= nr_prims
;
200 cost_fallback
= nr_rprims
;
202 /* One point for every 1024 dwords (4k) of dma:
204 cost_render
+= (vertsz
* i
) / 1024;
205 cost_fallback
+= (vertsz
* nr_rverts
) / 1024;
208 fprintf(stderr
, "cost render: %d fallback: %d\n",
209 cost_render
, cost_fallback
);
211 if (cost_render
> cost_fallback
)
219 intel_run_render(GLcontext
* ctx
, struct tnl_pipeline_stage
*stage
)
221 struct intel_context
*intel
= intel_context(ctx
);
222 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
223 struct vertex_buffer
*VB
= &tnl
->vb
;
226 intel
->vtbl
.render_prevalidate( intel
);
228 /* Don't handle clipping or indexed vertices.
230 if (intel
->RenderIndex
!= 0 ||
231 !intel_validate_render(ctx
, VB
) || !choose_render(intel
, VB
)) {
235 tnl
->clipspace
.new_inputs
|= VERT_BIT_POS
;
237 tnl
->Driver
.Render
.Start(ctx
);
239 for (i
= 0; i
< VB
->PrimitiveCount
; i
++) {
240 GLuint prim
= _tnl_translate_prim(&VB
->Primitive
[i
]);
241 GLuint start
= VB
->Primitive
[i
].start
;
242 GLuint length
= VB
->Primitive
[i
].count
;
247 intel_render_tab_verts
[prim
& PRIM_MODE_MASK
] (ctx
, start
,
248 start
+ length
, prim
);
251 tnl
->Driver
.Render
.Finish(ctx
);
253 INTEL_FIREVERTICES(intel
);
255 return GL_FALSE
; /* finished the pipe */
258 static const struct tnl_pipeline_stage _intel_render_stage
= {
264 intel_run_render
/* run */
267 const struct tnl_pipeline_stage
*intel_pipeline
[] = {
268 &_tnl_vertex_transform_stage
,
269 &_tnl_normal_transform_stage
,
270 &_tnl_lighting_stage
,
271 &_tnl_fog_coordinate_stage
,
273 &_tnl_texture_transform_stage
,
274 &_tnl_point_attenuation_stage
,
275 &_tnl_vertex_program_stage
,
277 &_intel_render_stage
, /* ADD: unclipped rastersetup-to-dma */