src/mesa/drivers/dri/i915/intel_tex_layout.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   *   Michel Dänzer <daenzer@vmware.com>
  31   */
  32
  33 #include "intel_mipmap_tree.h"
  34 #include "intel_tex_layout.h"
  35 #include "intel_context.h"
  36
  37 #include "main/image.h"
  38 #include "main/macros.h"
  39
  40 static unsigned int
  41 intel_horizontal_texture_alignment_unit(struct intel_context *intel,
  42                                        mesa_format format)
  43 {
  44    /**
  45     * From the "Alignment Unit Size" section of various specs, namely:
  46     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
  47     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
  48     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
  49     * - BSpec (for Ivybridge and slight variations in separate stencil)
  50     *
  51     * +----------------------------------------------------------------------+
  52     * |                                        | alignment unit width  ("i") |
  53     * | Surface Property                       |-----------------------------|
  54     * |                                        | 915 | 965 | ILK | SNB | IVB |
  55     * +----------------------------------------------------------------------+
  56     * | YUV 4:2:2 format                       |  8  |  4  |  4  |  4  |  4  |
  57     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
  58     * | FXT1  compressed format                |  8  |  8  |  8  |  8  |  8  |
  59     * | Depth Buffer (16-bit)                  |  4  |  4  |  4  |  4  |  8  |
  60     * | Depth Buffer (other)                   |  4  |  4  |  4  |  4  |  4  |
  61     * | Separate Stencil Buffer                | N/A | N/A |  8  |  8  |  8  |
  62     * | All Others                             |  4  |  4  |  4  |  4  |  4  |
  63     * +----------------------------------------------------------------------+
  64     *
  65     * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
  66     * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
  67     */
  68     if (_mesa_is_format_compressed(format)) {
  69        /* The hardware alignment requirements for compressed textures
  70         * happen to match the block boundaries.
  71         */
  72       unsigned int i, j;
  73       _mesa_get_format_block_size(format, &i, &j);
  74       return i;
  75     }
  76
  77    return 4;
  78 }
  79
  80 static unsigned int
  81 intel_vertical_texture_alignment_unit(struct intel_context *intel,
  82                                      mesa_format format)
  83 {
  84    /**
  85     * From the "Alignment Unit Size" section of various specs, namely:
  86     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
  87     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
  88     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
  89     * - BSpec (for Ivybridge and slight variations in separate stencil)
  90     *
  91     * +----------------------------------------------------------------------+
  92     * |                                        | alignment unit height ("j") |
  93     * | Surface Property                       |-----------------------------|
  94     * |                                        | 915 | 965 | ILK | SNB | IVB |
  95     * +----------------------------------------------------------------------+
  96     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
  97     * | FXT1  compressed format                |  4  |  4  |  4  |  4  |  4  |
  98     * | Depth Buffer                           |  2  |  2  |  2  |  4  |  4  |
  99     * | Separate Stencil Buffer                | N/A | N/A | N/A |  4  |  8  |
 100     * | All Others                             |  2  |  2  |  2  |  2  |  2  |
 101     * +----------------------------------------------------------------------+
 102     *
 103     * On SNB+, non-special cases can be overridden by setting the SURFACE_STATE
 104     * "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4.
 105     */
 106    if (_mesa_is_format_compressed(format))
 107       return 4;
 108
 109    return 2;
 110 }
 111
 112 void
 113 intel_get_texture_alignment_unit(struct intel_context *intel,
 114                                  mesa_format format,
 115                                  unsigned int *w, unsigned int *h)
 116 {
 117    *w = intel_horizontal_texture_alignment_unit(intel, format);
 118    *h = intel_vertical_texture_alignment_unit(intel, format);
 119 }
 120
 121 void i945_miptree_layout_2d(struct intel_mipmap_tree *mt)
 122 {
 123    GLuint level;
 124    GLuint x = 0;
 125    GLuint y = 0;
 126    GLuint width = mt->physical_width0;
 127    GLuint height = mt->physical_height0;
 128    GLuint depth = mt->physical_depth0; /* number of array layers. */
 129
 130    mt->total_width = mt->physical_width0;
 131
 132    if (mt->compressed) {
 133        mt->total_width = ALIGN(mt->physical_width0, mt->align_w);
 134    }
 135
 136    /* May need to adjust width to accommodate the placement of
 137     * the 2nd mipmap.  This occurs when the alignment
 138     * constraints of mipmap placement push the right edge of the
 139     * 2nd mipmap out past the width of its parent.
 140     */
 141    if (mt->first_level != mt->last_level) {
 142        GLuint mip1_width;
 143
 144        if (mt->compressed) {
 145           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 146              ALIGN(minify(mt->physical_width0, 2), mt->align_w);
 147        } else {
 148           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 149              minify(mt->physical_width0, 2);
 150        }
 151
 152        if (mip1_width > mt->total_width) {
 153            mt->total_width = mip1_width;
 154        }
 155    }
 156
 157    mt->total_height = 0;
 158
 159    for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {
 160       GLuint img_height;
 161
 162       intel_miptree_set_level_info(mt, level, x, y, width,
 163                                    height, depth);
 164
 165       img_height = ALIGN(height, mt->align_h);
 166       if (mt->compressed)
 167          img_height /= mt->align_h;
 168
 169       /* Because the images are packed better, the final offset
 170        * might not be the maximal one:
 171        */
 172       mt->total_height = MAX2(mt->total_height, y + img_height);
 173
 174       /* Layout_below: step right after second mipmap.
 175        */
 176       if (level == mt->first_level + 1) {
 177          x += ALIGN(width, mt->align_w);
 178       }
 179       else {
 180          y += img_height;
 181       }
 182
 183       width  = minify(width, 1);
 184       height = minify(height, 1);
 185    }
 186 }