src/mesa/drivers/dri/i915tex/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "glheader.h"
  31 #include "mtypes.h"
  32 #include "imports.h"
  33 #include "macros.h"
  34 #include "colormac.h"
  35
  36 #include "tnl/t_context.h"
  37 #include "tnl/t_vertex.h"
  38
  39 #include "intel_batchbuffer.h"
  40 #include "intel_tex.h"
  41 #include "intel_regions.h"
  42
  43 #include "i915_reg.h"
  44 #include "i915_context.h"
  45
  46 static void
  47 i915_render_start(struct intel_context *intel)
  48 {
  49    struct i915_context *i915 = i915_context(&intel->ctx);
  50
  51    i915ValidateFragmentProgram(i915);
  52 }
  53
  54
  55 static void
  56 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  57 {
  58    struct i915_context *i915 = i915_context(&intel->ctx);
  59    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  60
  61    st1 &= ~ST1_ENABLE;
  62
  63    switch (rprim) {
  64    case GL_TRIANGLES:
  65       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  66          st1 |= ST1_ENABLE;
  67       break;
  68    case GL_LINES:
  69    case GL_POINTS:
  70    default:
  71       break;
  72    }
  73
  74    i915->intel.reduced_primitive = rprim;
  75
  76    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  77       INTEL_FIREVERTICES(intel);
  78
  79       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  80       i915->state.Stipple[I915_STPREG_ST1] = st1;
  81    }
  82 }
  83
  84
  85 /* Pull apart the vertex format registers and figure out how large a
  86  * vertex is supposed to be.
  87  */
  88 static GLboolean
  89 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
  90 {
  91    struct i915_context *i915 = i915_context(&intel->ctx);
  92    int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
  93    int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
  94    int i, sz = 0;
  95
  96    switch (lis4 & S4_VFMT_XYZW_MASK) {
  97    case S4_VFMT_XY:
  98       sz = 2;
  99       break;
 100    case S4_VFMT_XYZ:
 101       sz = 3;
 102       break;
 103    case S4_VFMT_XYW:
 104       sz = 3;
 105       break;
 106    case S4_VFMT_XYZW:
 107       sz = 4;
 108       break;
 109    default:
 110       fprintf(stderr, "no xyzw specified\n");
 111       return 0;
 112    }
 113
 114    if (lis4 & S4_VFMT_SPEC_FOG)
 115       sz++;
 116    if (lis4 & S4_VFMT_COLOR)
 117       sz++;
 118    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 119       sz++;
 120    if (lis4 & S4_VFMT_POINT_WIDTH)
 121       sz++;
 122    if (lis4 & S4_VFMT_FOG_PARAM)
 123       sz++;
 124
 125    for (i = 0; i < 8; i++) {
 126       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 127       case TEXCOORDFMT_2D:
 128          sz += 2;
 129          break;
 130       case TEXCOORDFMT_3D:
 131          sz += 3;
 132          break;
 133       case TEXCOORDFMT_4D:
 134          sz += 4;
 135          break;
 136       case TEXCOORDFMT_1D:
 137          sz += 1;
 138          break;
 139       case TEXCOORDFMT_2D_16:
 140          sz += 1;
 141          break;
 142       case TEXCOORDFMT_4D_16:
 143          sz += 2;
 144          break;
 145       case TEXCOORDFMT_NOT_PRESENT:
 146          break;
 147       default:
 148          fprintf(stderr, "bad texcoord fmt %d\n", i);
 149          return GL_FALSE;
 150       }
 151       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 152    }
 153
 154    if (sz != expected)
 155       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 156
 157    return sz == expected;
 158 }
 159
 160
 161 static void
 162 i915_emit_invarient_state(struct intel_context *intel)
 163 {
 164    BATCH_LOCALS;
 165
 166    BEGIN_BATCH(200, 0);
 167
 168    OUT_BATCH(_3DSTATE_AA_CMD |
 169              AA_LINE_ECAAR_WIDTH_ENABLE |
 170              AA_LINE_ECAAR_WIDTH_1_0 |
 171              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 172
 173    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 174    OUT_BATCH(0);
 175
 176    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 177    OUT_BATCH(0);
 178
 179    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 180    OUT_BATCH(0);
 181
 182    /* Don't support texture crossbar yet */
 183    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 184              CSB_TCB(0, 0) |
 185              CSB_TCB(1, 1) |
 186              CSB_TCB(2, 2) |
 187              CSB_TCB(3, 3) |
 188              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 189
 190    OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 191              ENABLE_POINT_RASTER_RULE |
 192              OGL_POINT_RASTER_RULE |
 193              ENABLE_LINE_STRIP_PROVOKE_VRTX |
 194              ENABLE_TRI_FAN_PROVOKE_VRTX |
 195              LINE_STRIP_PROVOKE_VRTX(1) |
 196              TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
 197
 198    /* Need to initialize this to zero.
 199     */
 200    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (1));
 201    OUT_BATCH(0);
 202
 203    /* XXX: Use this */
 204    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 205
 206    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 207    OUT_BATCH(0);
 208    OUT_BATCH(0);
 209
 210    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 211
 212    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 213    OUT_BATCH(0);
 214
 215
 216    /* Don't support twosided stencil yet */
 217    OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
 218
 219    ADVANCE_BATCH();
 220 }
 221
 222
 223 #define emit(intel, state, size )                    \
 224    intel_batchbuffer_data(intel->batch, state, size, 0 )
 225
 226 static GLuint
 227 get_dirty(struct i915_hw_state *state)
 228 {
 229    GLuint dirty;
 230
 231    /* Workaround the multitex hang - if one texture unit state is
 232     * modified, emit all texture units.
 233     */
 234    dirty = state->active & ~state->emitted;
 235    if (dirty & I915_UPLOAD_TEX_ALL)
 236       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 237    dirty = state->active & ~state->emitted;
 238    return dirty;
 239 }
 240
 241
 242 static GLuint
 243 get_state_size(struct i915_hw_state *state)
 244 {
 245    GLuint dirty = get_dirty(state);
 246    GLuint i;
 247    GLuint sz = 0;
 248
 249    if (dirty & I915_UPLOAD_CTX)
 250       sz += sizeof(state->Ctx);
 251
 252    if (dirty & I915_UPLOAD_BUFFERS)
 253       sz += sizeof(state->Buffer);
 254
 255    if (dirty & I915_UPLOAD_STIPPLE)
 256       sz += sizeof(state->Stipple);
 257
 258    if (dirty & I915_UPLOAD_FOG)
 259       sz += sizeof(state->Fog);
 260
 261    if (dirty & I915_UPLOAD_TEX_ALL) {
 262       int nr = 0;
 263       for (i = 0; i < I915_TEX_UNITS; i++)
 264          if (dirty & I915_UPLOAD_TEX(i))
 265             nr++;
 266
 267       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 268    }
 269
 270    if (dirty & I915_UPLOAD_CONSTANTS)
 271       sz += state->ConstantSize * sizeof(GLuint);
 272
 273    if (dirty & I915_UPLOAD_PROGRAM)
 274       sz += state->ProgramSize * sizeof(GLuint);
 275
 276    return sz;
 277 }
 278
 279
 280 /* Push the state into the sarea and/or texture memory.
 281  */
 282 static void
 283 i915_emit_state(struct intel_context *intel)
 284 {
 285    struct i915_context *i915 = i915_context(&intel->ctx);
 286    struct i915_hw_state *state = i915->current;
 287    int i;
 288    GLuint dirty;
 289    BATCH_LOCALS;
 290
 291    /* We don't hold the lock at this point, so want to make sure that
 292     * there won't be a buffer wrap.
 293     *
 294     * It might be better to talk about explicit places where
 295     * scheduling is allowed, rather than assume that it is whenever a
 296     * batchbuffer fills up.
 297     */
 298    intel_batchbuffer_require_space(intel->batch, get_state_size(state), 0);
 299
 300    /* Do this here as we may have flushed the batchbuffer above,
 301     * causing more state to be dirty!
 302     */
 303    dirty = get_dirty(state);
 304
 305    if (INTEL_DEBUG & DEBUG_STATE)
 306       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 307
 308    if (dirty & I915_UPLOAD_INVARIENT) {
 309       if (INTEL_DEBUG & DEBUG_STATE)
 310          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 311       i915_emit_invarient_state(intel);
 312    }
 313
 314    if (dirty & I915_UPLOAD_CTX) {
 315       if (INTEL_DEBUG & DEBUG_STATE)
 316          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 317
 318       emit(intel, state->Ctx, sizeof(state->Ctx));
 319    }
 320
 321    if (dirty & I915_UPLOAD_BUFFERS) {
 322       if (INTEL_DEBUG & DEBUG_STATE)
 323          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 324       BEGIN_BATCH(I915_DEST_SETUP_SIZE + 2, 0);
 325       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 326       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 327       OUT_RELOC(state->draw_region->buffer,
 328                 DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
 329                 DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
 330                 state->draw_region->draw_offset);
 331
 332       if (state->depth_region) {
 333          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 334          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 335          OUT_RELOC(state->depth_region->buffer,
 336                    DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
 337                    DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
 338                    state->depth_region->draw_offset);
 339       }
 340
 341       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 342       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 343       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 344       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 345       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 346       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 347       ADVANCE_BATCH();
 348    }
 349
 350    if (dirty & I915_UPLOAD_STIPPLE) {
 351       if (INTEL_DEBUG & DEBUG_STATE)
 352          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 353       emit(intel, state->Stipple, sizeof(state->Stipple));
 354    }
 355
 356    if (dirty & I915_UPLOAD_FOG) {
 357       if (INTEL_DEBUG & DEBUG_STATE)
 358          fprintf(stderr, "I915_UPLOAD_FOG:\n");
 359       emit(intel, state->Fog, sizeof(state->Fog));
 360    }
 361
 362    /* Combine all the dirty texture state into a single command to
 363     * avoid lockups on I915 hardware.
 364     */
 365    if (dirty & I915_UPLOAD_TEX_ALL) {
 366       int nr = 0;
 367
 368       for (i = 0; i < I915_TEX_UNITS; i++)
 369          if (dirty & I915_UPLOAD_TEX(i))
 370             nr++;
 371
 372       BEGIN_BATCH(2 + nr * 3, 0);
 373       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 374       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 375       for (i = 0; i < I915_TEX_UNITS; i++)
 376          if (dirty & I915_UPLOAD_TEX(i)) {
 377
 378             if (state->tex_buffer[i]) {
 379                OUT_RELOC(state->tex_buffer[i],
 380                          DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
 381                          DRM_BO_MASK_MEM | DRM_BO_FLAG_READ,
 382                          state->tex_offset[i]);
 383             }
 384             else {
 385                assert(i == 0);
 386                assert(state == &i915->meta);
 387                OUT_BATCH(0);
 388             }
 389
 390             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 391             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 392          }
 393       ADVANCE_BATCH();
 394
 395       BEGIN_BATCH(2 + nr * 3, 0);
 396       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 397       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 398       for (i = 0; i < I915_TEX_UNITS; i++)
 399          if (dirty & I915_UPLOAD_TEX(i)) {
 400             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 401             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 402             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 403          }
 404       ADVANCE_BATCH();
 405    }
 406
 407    if (dirty & I915_UPLOAD_CONSTANTS) {
 408       if (INTEL_DEBUG & DEBUG_STATE)
 409          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 410       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 411    }
 412
 413    if (dirty & I915_UPLOAD_PROGRAM) {
 414       if (INTEL_DEBUG & DEBUG_STATE)
 415          fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 416
 417       assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 418
 419       emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 420       if (INTEL_DEBUG & DEBUG_STATE)
 421          i915_disassemble_program(state->Program, state->ProgramSize);
 422    }
 423
 424    state->emitted |= dirty;
 425 }
 426
 427 static void
 428 i915_destroy_context(struct intel_context *intel)
 429 {
 430    _tnl_free_vertices(&intel->ctx);
 431 }
 432
 433
 434 /**
 435  * Set the drawing regions for the color and depth/stencil buffers.
 436  * This involves setting the pitch, cpp and buffer ID/location.
 437  * Also set pixel format for color and Z rendering
 438  * Used for setting both regular and meta state.
 439  */
 440 void
 441 i915_state_draw_region(struct intel_context *intel,
 442                        struct i915_hw_state *state,
 443                        struct intel_region *color_region,
 444                        struct intel_region *depth_region)
 445 {
 446    struct i915_context *i915 = i915_context(&intel->ctx);
 447    GLuint value;
 448
 449    ASSERT(state == &i915->state || state == &i915->meta);
 450
 451    if (state->draw_region != color_region) {
 452       intel_region_release(&state->draw_region);
 453       intel_region_reference(&state->draw_region, color_region);
 454    }
 455    if (state->depth_region != depth_region) {
 456       intel_region_release(&state->depth_region);
 457       intel_region_reference(&state->depth_region, depth_region);
 458    }
 459
 460    /*
 461     * Set stride/cpp values
 462     */
 463    if (color_region) {
 464       state->Buffer[I915_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 465       state->Buffer[I915_DESTREG_CBUFADDR1] =
 466          (BUF_3D_ID_COLOR_BACK |
 467           BUF_3D_PITCH(color_region->pitch * color_region->cpp) |
 468           BUF_3D_USE_FENCE);
 469    }
 470
 471    if (depth_region) {
 472       state->Buffer[I915_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 473       state->Buffer[I915_DESTREG_DBUFADDR1] =
 474          (BUF_3D_ID_DEPTH |
 475           BUF_3D_PITCH(depth_region->pitch * depth_region->cpp) |
 476           BUF_3D_USE_FENCE);
 477    }
 478
 479    /*
 480     * Compute/set I915_DESTREG_DV1 value
 481     */
 482    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 483             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 484             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 485    if (color_region && color_region->cpp == 4) {
 486       value |= DV_PF_8888;
 487    }
 488    else {
 489       value |= (DITHER_FULL_ALWAYS | DV_PF_565);
 490    }
 491    if (depth_region && depth_region->cpp == 4) {
 492       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 493    }
 494    else {
 495       value |= DEPTH_FRMT_16_FIXED;
 496    }
 497    state->Buffer[I915_DESTREG_DV1] = value;
 498
 499    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 500 }
 501
 502
 503 static void
 504 i915_set_draw_region(struct intel_context *intel,
 505                      struct intel_region *color_region,
 506                      struct intel_region *depth_region)
 507 {
 508    struct i915_context *i915 = i915_context(&intel->ctx);
 509    i915_state_draw_region(intel, &i915->state, color_region, depth_region);
 510 }
 511
 512
 513
 514 static void
 515 i915_lost_hardware(struct intel_context *intel)
 516 {
 517    struct i915_context *i915 = i915_context(&intel->ctx);
 518    i915->state.emitted = 0;
 519 }
 520
 521 static GLuint
 522 i915_flush_cmd(void)
 523 {
 524    return MI_FLUSH | FLUSH_MAP_CACHE;
 525 }
 526
 527 static void
 528 i915_assert_not_dirty( struct intel_context *intel )
 529 {
 530    struct i915_context *i915 = i915_context(&intel->ctx);
 531    struct i915_hw_state *state = i915->current;
 532    GLuint dirty = get_dirty(state);
 533    assert(!dirty);
 534 }
 535
 536
 537 void
 538 i915InitVtbl(struct i915_context *i915)
 539 {
 540    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 541    i915->intel.vtbl.destroy = i915_destroy_context;
 542    i915->intel.vtbl.emit_state = i915_emit_state;
 543    i915->intel.vtbl.lost_hardware = i915_lost_hardware;
 544    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 545    i915->intel.vtbl.render_start = i915_render_start;
 546    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 547    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 548    i915->intel.vtbl.flush_cmd = i915_flush_cmd;
 549    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 550 }