src/mesa/drivers/dri/i915tex/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_batchbuffer.h"
  29 #include "intel_ioctl.h"
  30
  31 /* Relocations in kernel space:
  32  *    - pass dma buffer seperately
  33  *    - memory manager knows how to patch
  34  *    - pass list of dependent buffers
  35  *    - pass relocation list
  36  *
  37  * Either:
  38  *    - get back an offset for buffer to fire
  39  *    - memory manager knows how to fire buffer
  40  *
  41  * Really want the buffer to be AGP and pinned.
  42  *
  43  */
  44
  45 /* Cliprect fence: The highest fence protecting a dma buffer
  46  * containing explicit cliprect information.  Like the old drawable
  47  * lock but irq-driven.  X server must wait for this fence to expire
  48  * before changing cliprects [and then doing sw rendering?].  For
  49  * other dma buffers, the scheduler will grab current cliprect info
  50  * and mix into buffer.  X server must hold the lock while changing
  51  * cliprects???  Make per-drawable.  Need cliprects in shared memory
  52  * -- beats storing them with every cmd buffer in the queue.
  53  *
  54  * ==> X server must wait for this fence to expire before touching the
  55  * framebuffer with new cliprects.
  56  *
  57  * ==> Cliprect-dependent buffers associated with a
  58  * cliprect-timestamp.  All of the buffers associated with a timestamp
  59  * must go to hardware before any buffer with a newer timestamp.
  60  *
  61  * ==> Dma should be queued per-drawable for correct X/GL
  62  * synchronization.  Or can fences be used for this?
  63  *
  64  * Applies to: Blit operations, metaops, X server operations -- X
  65  * server automatically waits on its own dma to complete before
  66  * modifying cliprects ???
  67  */
  68
  69 static void
  70 intel_dump_batchbuffer(GLuint offset, GLuint * ptr, GLuint count)
  71 {
  72    int i;
  73    fprintf(stderr, "\n\n\nSTART BATCH (%d dwords):\n", count / 4);
  74    for (i = 0; i < count / 4; i += 4)
  75       fprintf(stderr, "0x%x:\t0x%08x 0x%08x 0x%08x 0x%08x\n",
  76               offset + i * 4, ptr[i], ptr[i + 1], ptr[i + 2], ptr[i + 3]);
  77    fprintf(stderr, "END BATCH\n\n\n");
  78 }
  79
  80 /*======================================================================
  81  * Public functions
  82  */
  83 struct intel_batchbuffer *
  84 intel_batchbuffer_alloc(struct intel_context *intel)
  85 {
  86    struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
  87
  88    batch->intel = intel;
  89    batch->buf = dri_bo_alloc(intel->intelScreen->bufmgr, "batchbuffer",
  90                              intel->intelScreen->maxBatchSize, 4096,
  91                              DRM_BO_FLAG_MEM_TT |
  92                              DRM_BO_FLAG_EXE, 0);
  93    dri_bo_map(batch->buf, GL_TRUE);
  94    batch->map = batch->buf->virtual;
  95    batch->size = intel->intelScreen->maxBatchSize;
  96    batch->ptr = batch->map;
  97
  98    batch->last_fence = NULL;
  99    intel_batchbuffer_reset(batch);
 100    return batch;
 101 }
 102
 103 void
 104 intel_batchbuffer_free(struct intel_batchbuffer *batch)
 105 {
 106    if (batch->last_fence) {
 107       dri_fence_wait(batch->last_fence);
 108       dri_fence_unreference(batch->last_fence);
 109       batch->last_fence = NULL;
 110    }
 111    if (batch->map) {
 112       dri_bo_unmap(batch->buf);
 113       batch->map = NULL;
 114    }
 115    dri_bo_unreference(batch->buf);
 116    batch->buf = NULL;
 117    free(batch);
 118 }
 119
 120 /* TODO: Push this whole function into bufmgr.
 121  */
 122 static void
 123 do_flush_locked(struct intel_batchbuffer *batch,
 124                 GLuint used,
 125                 GLboolean ignore_cliprects, GLboolean allow_unlock)
 126 {
 127    GLuint *ptr;
 128    GLuint i;
 129    struct intel_context *intel = batch->intel;
 130    dri_fence *fo;
 131    GLboolean performed_rendering = GL_FALSE;
 132
 133    assert(batch->buf->virtual != NULL);
 134    ptr = batch->buf->virtual;
 135
 136    for (i = 0; i < batch->nr_relocs; i++) {
 137       struct buffer_reloc *r = &batch->reloc[i];
 138
 139       if (r->validate_flags & DRM_BO_FLAG_WRITE)
 140          performed_rendering = GL_TRUE;
 141
 142       dri_bo_validate(r->buf, r->validate_flags);
 143       ptr[r->offset / 4] = r->buf->offset + r->delta;
 144       dri_bo_unreference(r->buf);
 145    }
 146
 147    if (INTEL_DEBUG & DEBUG_BATCH)
 148       intel_dump_batchbuffer(0, ptr, used);
 149
 150    dri_bo_unmap(batch->buf);
 151    batch->map = NULL;
 152    batch->ptr = NULL;
 153
 154    dri_bo_validate(batch->buf, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_EXE);
 155
 156    batch->list_count = 0;
 157    batch->nr_relocs = 0;
 158    batch->flags = 0;
 159
 160    /* Throw away non-effective packets.  Won't work once we have
 161     * hardware contexts which would preserve statechanges beyond a
 162     * single buffer.
 163     */
 164
 165    if (!(intel->numClipRects == 0 && !ignore_cliprects)) {
 166       intel_batch_ioctl(batch->intel,
 167                         batch->buf->offset,
 168                         used, ignore_cliprects, allow_unlock);
 169    }
 170
 171    /* Associate a fence with the validated buffers, and note that we included
 172     * a flush at the end.
 173     */
 174    fo = dri_fence_validated(intel->intelScreen->bufmgr,
 175                             "Batch fence", GL_TRUE);
 176
 177    if (performed_rendering) {
 178       dri_fence_unreference(batch->last_fence);
 179       batch->last_fence = fo;
 180    } else {
 181      /* If we didn't validate any buffers for writing by the card, we don't
 182       * need to track the fence for glFinish().
 183       */
 184       dri_fence_unreference(fo);
 185    }
 186
 187    if (intel->numClipRects == 0 && !ignore_cliprects) {
 188       if (allow_unlock) {
 189          /* If we are not doing any actual user-visible rendering,
 190           * do a sched_yield to keep the app from pegging the cpu while
 191           * achieving nothing.
 192           */
 193          UNLOCK_HARDWARE(intel);
 194          sched_yield();
 195          LOCK_HARDWARE(intel);
 196       }
 197       intel->vtbl.lost_hardware(intel);
 198    }
 199 }
 200
 201
 202 void
 203 intel_batchbuffer_flush(struct intel_batchbuffer *batch)
 204 {
 205    struct intel_context *intel = batch->intel;
 206    GLuint used = batch->ptr - batch->map;
 207    GLboolean was_locked = intel->locked;
 208
 209    if (used == 0)
 210       return;
 211
 212    /* Add the MI_BATCH_BUFFER_END.  Always add an MI_FLUSH - this is a
 213     * performance drain that we would like to avoid.
 214     */
 215    if (used & 4) {
 216       ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
 217       ((int *) batch->ptr)[1] = 0;
 218       ((int *) batch->ptr)[2] = MI_BATCH_BUFFER_END;
 219       used += 12;
 220    }
 221    else {
 222       ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
 223       ((int *) batch->ptr)[1] = MI_BATCH_BUFFER_END;
 224       used += 8;
 225    }
 226
 227    /* TODO: Just pass the relocation list and dma buffer up to the
 228     * kernel.
 229     */
 230    if (!was_locked)
 231       LOCK_HARDWARE(intel);
 232
 233    do_flush_locked(batch, used, !(batch->flags & INTEL_BATCH_CLIPRECTS),
 234                    GL_FALSE);
 235
 236    if (!was_locked)
 237       UNLOCK_HARDWARE(intel);
 238
 239    /* Reset the buffer:
 240     */
 241    intel_batchbuffer_reset(batch);
 242 }
 243
 244 void
 245 intel_batchbuffer_finish(struct intel_batchbuffer *batch)
 246 {
 247    intel_batchbuffer_flush(batch);
 248    if (batch->last_fence != NULL)
 249       dri_fence_wait(batch->last_fence);
 250 }
 251
 252
 253 /*  This is the only way buffers get added to the validate list.
 254  */
 255 GLboolean
 256 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
 257                              dri_bo *buffer,
 258                              GLuint flags, GLuint delta)
 259 {
 260    struct buffer_reloc *r = &batch->reloc[batch->nr_relocs++];
 261
 262    assert(batch->nr_relocs <= MAX_RELOCS);
 263
 264    dri_bo_reference(buffer);
 265    r->buf = buffer;
 266    r->offset = batch->ptr - batch->map;
 267    r->delta = delta;
 268    r->validate_flags = flags;
 269
 270    batch->ptr += 4;
 271    return GL_TRUE;
 272 }
 273
 274
 275
 276 void
 277 intel_batchbuffer_data(struct intel_batchbuffer *batch,
 278                        const void *data, GLuint bytes, GLuint flags)
 279 {
 280    assert((bytes & 3) == 0);
 281    intel_batchbuffer_require_space(batch, bytes, flags);
 282    __memcpy(batch->ptr, data, bytes);
 283    batch->ptr += bytes;
 284 }