src/mesa/drivers/dri/i915tex/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
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  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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  26  **************************************************************************/
  27
  28 #include "intel_batchbuffer.h"
  29 #include "intel_ioctl.h"
  30
  31 /* Relocations in kernel space:
  32  *    - pass dma buffer seperately
  33  *    - memory manager knows how to patch
  34  *    - pass list of dependent buffers
  35  *    - pass relocation list
  36  *
  37  * Either:
  38  *    - get back an offset for buffer to fire
  39  *    - memory manager knows how to fire buffer
  40  *
  41  * Really want the buffer to be AGP and pinned.
  42  *
  43  */
  44
  45 /* Cliprect fence: The highest fence protecting a dma buffer
  46  * containing explicit cliprect information.  Like the old drawable
  47  * lock but irq-driven.  X server must wait for this fence to expire
  48  * before changing cliprects [and then doing sw rendering?].  For
  49  * other dma buffers, the scheduler will grab current cliprect info
  50  * and mix into buffer.  X server must hold the lock while changing
  51  * cliprects???  Make per-drawable.  Need cliprects in shared memory
  52  * -- beats storing them with every cmd buffer in the queue.
  53  *
  54  * ==> X server must wait for this fence to expire before touching the
  55  * framebuffer with new cliprects.
  56  *
  57  * ==> Cliprect-dependent buffers associated with a
  58  * cliprect-timestamp.  All of the buffers associated with a timestamp
  59  * must go to hardware before any buffer with a newer timestamp.
  60  *
  61  * ==> Dma should be queued per-drawable for correct X/GL
  62  * synchronization.  Or can fences be used for this?
  63  *
  64  * Applies to: Blit operations, metaops, X server operations -- X
  65  * server automatically waits on its own dma to complete before
  66  * modifying cliprects ???
  67  */
  68
  69 static void
  70 intel_dump_batchbuffer(GLuint offset, GLuint * ptr, GLuint count)
  71 {
  72    int i;
  73    fprintf(stderr, "\n\n\nSTART BATCH (%d dwords):\n", count / 4);
  74    for (i = 0; i < count / 4; i += 4)
  75       fprintf(stderr, "0x%x:\t0x%08x 0x%08x 0x%08x 0x%08x\n",
  76               offset + i * 4, ptr[i], ptr[i + 1], ptr[i + 2], ptr[i + 3]);
  77    fprintf(stderr, "END BATCH\n\n\n");
  78 }
  79
  80 void
  81 intel_batchbuffer_reset(struct intel_batchbuffer *batch)
  82 {
  83
  84    int i;
  85
  86    /*
  87     * Get a new, free batchbuffer.
  88     */
  89
  90    batch->size =  batch->intel->intelScreen->maxBatchSize;
  91    driBOData(batch->buffer, batch->size, NULL, 0);
  92
  93    driBOResetList(&batch->list);
  94
  95    /*
  96     * Unreference buffers previously on the relocation list.
  97     */
  98
  99    for (i = 0; i < batch->nr_relocs; i++) {
 100       struct buffer_reloc *r = &batch->reloc[i];
 101       driBOUnReference(r->buf);
 102    }
 103
 104    batch->list_count = 0;
 105    batch->nr_relocs = 0;
 106    batch->flags = 0;
 107
 108    /*
 109     * We don't refcount the batchbuffer itself since we can't destroy it
 110     * while it's on the list.
 111     */
 112
 113
 114    driBOAddListItem(&batch->list, batch->buffer,
 115                     DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_EXE,
 116                     DRM_BO_MASK_MEM | DRM_BO_FLAG_EXE);
 117
 118
 119    batch->map = driBOMap(batch->buffer, DRM_BO_FLAG_WRITE, 0);
 120    batch->ptr = batch->map;
 121 }
 122
 123 /*======================================================================
 124  * Public functions
 125  */
 126 struct intel_batchbuffer *
 127 intel_batchbuffer_alloc(struct intel_context *intel)
 128 {
 129    struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
 130
 131    batch->intel = intel;
 132
 133    driGenBuffers(intel->intelScreen->batchPool, "batchbuffer", 1,
 134                  &batch->buffer, 4096,
 135                  DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_EXE, 0);
 136    batch->last_fence = NULL;
 137    driBOCreateList(20, &batch->list);
 138    intel_batchbuffer_reset(batch);
 139    return batch;
 140 }
 141
 142 void
 143 intel_batchbuffer_free(struct intel_batchbuffer *batch)
 144 {
 145    if (batch->last_fence) {
 146       driFenceFinish(batch->last_fence,
 147       DRM_FENCE_TYPE_EXE | DRM_I915_FENCE_TYPE_RW, GL_FALSE);
 148       driFenceUnReference(batch->last_fence);
 149       batch->last_fence = NULL;
 150    }
 151    if (batch->map) {
 152       driBOUnmap(batch->buffer);
 153       batch->map = NULL;
 154    }
 155    driBOUnReference(batch->buffer);
 156    batch->buffer = NULL;
 157    free(batch);
 158 }
 159
 160 /* TODO: Push this whole function into bufmgr.
 161  */
 162 static void
 163 do_flush_locked(struct intel_batchbuffer *batch,
 164                 GLuint used,
 165                 GLboolean ignore_cliprects, GLboolean allow_unlock)
 166 {
 167    GLuint *ptr;
 168    GLuint i;
 169    struct intel_context *intel = batch->intel;
 170    unsigned fenceFlags;
 171    struct _DriFenceObject *fo;
 172
 173    driBOValidateList(batch->intel->driFd, &batch->list);
 174
 175    /* Apply the relocations.  This nasty map indicates to me that the
 176     * whole task should be done internally by the memory manager, and
 177     * that dma buffers probably need to be pinned within agp space.
 178     */
 179    ptr = (GLuint *) driBOMap(batch->buffer, DRM_BO_FLAG_WRITE,
 180                              DRM_BO_HINT_ALLOW_UNFENCED_MAP);
 181
 182
 183    for (i = 0; i < batch->nr_relocs; i++) {
 184       struct buffer_reloc *r = &batch->reloc[i];
 185
 186       ptr[r->offset / 4] = driBOOffset(r->buf) + r->delta;
 187    }
 188
 189    if (INTEL_DEBUG & DEBUG_BATCH)
 190       intel_dump_batchbuffer(0, ptr, used);
 191
 192    driBOUnmap(batch->buffer);
 193    batch->map = NULL;
 194
 195    /* Throw away non-effective packets.  Won't work once we have
 196     * hardware contexts which would preserve statechanges beyond a
 197     * single buffer.
 198     */
 199
 200    if (!(intel->numClipRects == 0 && !ignore_cliprects)) {
 201       intel_batch_ioctl(batch->intel,
 202                         driBOOffset(batch->buffer),
 203                         used, ignore_cliprects, allow_unlock);
 204    }
 205
 206
 207    /*
 208     * Kernel fencing. The flags tells the kernel that we've
 209     * programmed an MI_FLUSH.
 210     */
 211
 212    fenceFlags = DRM_I915_FENCE_FLAG_FLUSHED;
 213    fo = driFenceBuffers(batch->intel->driFd,
 214                         "Batch fence", fenceFlags);
 215
 216    /*
 217     * User space fencing.
 218     */
 219
 220    driBOFence(batch->buffer, fo);
 221
 222    if (driFenceType(fo) == DRM_FENCE_TYPE_EXE) {
 223
 224      /*
 225       * Oops. We only validated a batch buffer. This means we
 226       * didn't do any proper rendering. Discard this fence object.
 227       */
 228
 229       driFenceUnReference(fo);
 230    } else {
 231       driFenceUnReference(batch->last_fence);
 232       batch->last_fence = fo;
 233       for (i = 0; i < batch->nr_relocs; i++) {
 234         struct buffer_reloc *r = &batch->reloc[i];
 235         driBOFence(r->buf, fo);
 236       }
 237    }
 238
 239    if (intel->numClipRects == 0 && !ignore_cliprects) {
 240       if (allow_unlock) {
 241          UNLOCK_HARDWARE(intel);
 242          sched_yield();
 243          LOCK_HARDWARE(intel);
 244       }
 245       intel->vtbl.lost_hardware(intel);
 246    }
 247 }
 248
 249
 250 struct _DriFenceObject *
 251 intel_batchbuffer_flush(struct intel_batchbuffer *batch)
 252 {
 253    struct intel_context *intel = batch->intel;
 254    GLuint used = batch->ptr - batch->map;
 255    GLboolean was_locked = intel->locked;
 256
 257    if (used == 0)
 258       return batch->last_fence;
 259
 260    /* Add the MI_BATCH_BUFFER_END.  Always add an MI_FLUSH - this is a
 261     * performance drain that we would like to avoid.
 262     */
 263    if (used & 4) {
 264       ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
 265       ((int *) batch->ptr)[1] = 0;
 266       ((int *) batch->ptr)[2] = MI_BATCH_BUFFER_END;
 267       used += 12;
 268    }
 269    else {
 270       ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
 271       ((int *) batch->ptr)[1] = MI_BATCH_BUFFER_END;
 272       used += 8;
 273    }
 274
 275    driBOUnmap(batch->buffer);
 276    batch->ptr = NULL;
 277    batch->map = NULL;
 278
 279    /* TODO: Just pass the relocation list and dma buffer up to the
 280     * kernel.
 281     */
 282    if (!was_locked)
 283       LOCK_HARDWARE(intel);
 284
 285    do_flush_locked(batch, used, !(batch->flags & INTEL_BATCH_CLIPRECTS),
 286                    GL_FALSE);
 287
 288    if (!was_locked)
 289       UNLOCK_HARDWARE(intel);
 290
 291    /* Reset the buffer:
 292     */
 293    intel_batchbuffer_reset(batch);
 294    return batch->last_fence;
 295 }
 296
 297 void
 298 intel_batchbuffer_finish(struct intel_batchbuffer *batch)
 299 {
 300    struct _DriFenceObject *fence = intel_batchbuffer_flush(batch);
 301    driFenceReference(fence);
 302    driFenceFinish(fence, 3, GL_FALSE);
 303    driFenceUnReference(fence);
 304 }
 305
 306
 307 /*  This is the only way buffers get added to the validate list.
 308  */
 309 GLboolean
 310 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
 311                              struct _DriBufferObject *buffer,
 312                              GLuint flags, GLuint mask, GLuint delta)
 313 {
 314    assert(batch->nr_relocs < MAX_RELOCS);
 315
 316    driBOAddListItem(&batch->list, buffer, flags, mask);
 317
 318    {
 319       struct buffer_reloc *r = &batch->reloc[batch->nr_relocs++];
 320       driBOReference(buffer);
 321       r->buf = buffer;
 322       r->offset = batch->ptr - batch->map;
 323       r->delta = delta;
 324    }
 325
 326    batch->ptr += 4;
 327    return GL_TRUE;
 328 }
 329
 330
 331
 332 void
 333 intel_batchbuffer_data(struct intel_batchbuffer *batch,
 334                        const void *data, GLuint bytes, GLuint flags)
 335 {
 336    assert((bytes & 3) == 0);
 337    intel_batchbuffer_require_space(batch, bytes, flags);
 338    __memcpy(batch->ptr, data, bytes);
 339    batch->ptr += bytes;
 340 }