Convert i915tex to the new interface and make it compile.
[mesa.git] / src / mesa / drivers / dri / i915tex / intel_ioctl.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include <stdio.h>
30 #include <unistd.h>
31 #include <errno.h>
32 #include <sched.h>
33
34 #include "mtypes.h"
35 #include "context.h"
36 #include "swrast/swrast.h"
37
38 #include "intel_context.h"
39 #include "intel_ioctl.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_blit.h"
42 #include "intel_regions.h"
43 #include "drm.h"
44
45 #define FILE_DEBUG_FLAG DEBUG_IOCTL
46
47 int
48 intelEmitIrqLocked(intelScreenPrivate *intelScreen)
49 {
50 drmI830IrqEmit ie;
51 int ret, seq;
52
53 ie.irq_seq = &seq;
54
55 ret = drmCommandWriteRead(intelScreen->driScrnPriv->fd,
56 DRM_I830_IRQ_EMIT, &ie, sizeof(ie));
57 if (ret) {
58 fprintf(stderr, "%s: drmI830IrqEmit: %d\n", __FUNCTION__, ret);
59 exit(1);
60 }
61
62 DBG("%s --> %d\n", __FUNCTION__, seq);
63
64 return seq;
65 }
66
67 void
68 intelWaitIrq(intelScreenPrivate *intelScreen, int seq)
69 {
70 drm_i915_irq_wait_t iw;
71 int ret;
72
73 DBG("%s %d\n", __FUNCTION__, seq);
74
75 iw.irq_seq = seq;
76
77 do {
78 ret = drmCommandWrite(intelScreen->driScrnPriv->fd,
79 DRM_I830_IRQ_WAIT, &iw, sizeof(iw));
80 } while (ret == -EAGAIN || ret == -EINTR);
81
82 if (ret) {
83 fprintf(stderr, "%s: drmI830IrqWait: %d\n", __FUNCTION__, ret);
84 exit(1);
85 }
86 }
87
88
89 void
90 intel_batch_ioctl(struct intel_context *intel,
91 GLuint start_offset,
92 GLuint used,
93 GLboolean ignore_cliprects, GLboolean allow_unlock)
94 {
95 drmI830BatchBuffer batch;
96
97 assert(intel->locked);
98 assert(used);
99
100 DBG("%s used %d offset %x..%x ignore_cliprects %d\n",
101 __FUNCTION__,
102 used, start_offset, start_offset + used, ignore_cliprects);
103
104 /* Throw away non-effective packets. Won't work once we have
105 * hardware contexts which would preserve statechanges beyond a
106 * single buffer.
107 */
108
109
110
111 batch.start = start_offset;
112 batch.used = used;
113 batch.cliprects = intel->pClipRects;
114 batch.num_cliprects = ignore_cliprects ? 0 : intel->numClipRects;
115 batch.DR1 = 0;
116 batch.DR4 = ((((GLuint) intel->drawX) & 0xffff) |
117 (((GLuint) intel->drawY) << 16));
118
119 DBG("%s: 0x%x..0x%x DR4: %x cliprects: %d\n",
120 __FUNCTION__,
121 batch.start,
122 batch.start + batch.used * 4, batch.DR4, batch.num_cliprects);
123
124 if (drmCommandWrite(intel->driFd, DRM_I830_BATCHBUFFER, &batch,
125 sizeof(batch))) {
126 fprintf(stderr, "DRM_I830_BATCHBUFFER: %d\n", -errno);
127 UNLOCK_HARDWARE(intel);
128 exit(1);
129 }
130
131 /* FIXME: use hardware contexts to avoid 'losing' hardware after
132 * each buffer flush.
133 */
134 intel->vtbl.lost_hardware(intel);
135 }