2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "blorp_priv.h"
29 #include "brw_compiler.h"
31 #include "brw_state.h"
34 blorp_init(struct blorp_context
*blorp
, void *driver_ctx
,
35 struct isl_device
*isl_dev
)
37 blorp
->driver_ctx
= driver_ctx
;
38 blorp
->isl_dev
= isl_dev
;
42 blorp_finish(struct blorp_context
*blorp
)
44 blorp
->driver_ctx
= NULL
;
48 brw_blorp_surface_info_init(struct brw_context
*brw
,
49 struct brw_blorp_surface_info
*info
,
50 const struct brw_blorp_surf
*surf
,
51 unsigned int level
, unsigned int layer
,
52 enum isl_format format
, bool is_render_target
)
54 /* Layer is a physical layer, so if this is a 2D multisample array texture
55 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
56 * be a multiple of num_samples.
58 unsigned layer_multiplier
= 1;
59 if (surf
->surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
60 assert(layer
% surf
->surf
->samples
== 0);
61 layer_multiplier
= surf
->surf
->samples
;
64 if (format
== ISL_FORMAT_UNSUPPORTED
)
65 format
= surf
->surf
->format
;
67 if (format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
68 /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
69 * a render target, which would prevent us from blitting to 24-bit
70 * depth. The miptree consists of 32 bits per pixel, arranged as 24-bit
71 * depth values interleaved with 8 "don't care" bits. Since depth
72 * values don't require any blending, it doesn't matter how we interpret
73 * the bit pattern as long as we copy the right amount of data, so just
74 * map it as 8-bit BGRA.
76 format
= ISL_FORMAT_B8G8R8A8_UNORM
;
77 } else if (surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
78 assert(surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
79 /* Prior to Broadwell, we can't render to R8_UINT */
81 format
= ISL_FORMAT_R8_UNORM
;
84 info
->surf
= *surf
->surf
;
86 info
->offset
= surf
->offset
;
88 info
->aux_usage
= surf
->aux_usage
;
89 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
90 info
->aux_surf
= *surf
->aux_surf
;
91 info
->aux_bo
= surf
->aux_bo
;
92 info
->aux_offset
= surf
->aux_offset
;
95 info
->clear_color
= surf
->clear_color
;
97 info
->view
= (struct isl_view
) {
98 .usage
= is_render_target
? ISL_SURF_USAGE_RENDER_TARGET_BIT
:
99 ISL_SURF_USAGE_TEXTURE_BIT
,
104 ISL_CHANNEL_SELECT_RED
,
105 ISL_CHANNEL_SELECT_GREEN
,
106 ISL_CHANNEL_SELECT_BLUE
,
107 ISL_CHANNEL_SELECT_ALPHA
,
111 if (!is_render_target
&&
112 (info
->surf
.dim
== ISL_SURF_DIM_3D
||
113 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)) {
114 /* 3-D textures don't support base_array layer and neither do 2-D
115 * multisampled textures on IVB so we need to pass it through the
116 * sampler in those cases. These are also two cases where we are
117 * guaranteed that we won't be doing any funny surface hacks.
119 info
->view
.base_array_layer
= 0;
120 info
->view
.array_len
= MAX2(info
->surf
.logical_level0_px
.depth
,
121 info
->surf
.logical_level0_px
.array_len
);
122 info
->z_offset
= layer
/ layer_multiplier
;
124 info
->view
.base_array_layer
= layer
/ layer_multiplier
;
125 info
->view
.array_len
= 1;
132 brw_blorp_params_init(struct brw_blorp_params
*params
)
134 memset(params
, 0, sizeof(*params
));
135 params
->hiz_op
= GEN6_HIZ_OP_NONE
;
136 params
->fast_clear_op
= 0;
137 params
->num_draw_buffers
= 1;
138 params
->num_layers
= 1;
142 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key
*wm_key
)
144 memset(wm_key
, 0, sizeof(*wm_key
));
145 wm_key
->nr_color_regions
= 1;
146 for (int i
= 0; i
< MAX_SAMPLERS
; i
++)
147 wm_key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;
151 nir_uniform_type_size(const struct glsl_type
*type
)
153 /* Only very basic types are allowed */
154 assert(glsl_type_is_vector_or_scalar(type
));
155 assert(glsl_get_bit_size(type
) == 32);
157 return glsl_get_vector_elements(type
) * 4;
161 brw_blorp_compile_nir_shader(struct brw_context
*brw
, struct nir_shader
*nir
,
162 const struct brw_wm_prog_key
*wm_key
,
164 struct brw_blorp_prog_data
*prog_data
,
165 unsigned *program_size
)
167 const struct brw_compiler
*compiler
= brw
->intelScreen
->compiler
;
169 void *mem_ctx
= ralloc_context(NULL
);
171 /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
172 * enabled, may end up completely replacing the nir_shader. Therefore, we
173 * own it and might as well put it in our context for easy cleanup.
175 ralloc_steal(mem_ctx
, nir
);
177 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
;
179 struct brw_wm_prog_data wm_prog_data
;
180 memset(&wm_prog_data
, 0, sizeof(wm_prog_data
));
182 wm_prog_data
.base
.nr_params
= 0;
183 wm_prog_data
.base
.param
= NULL
;
185 /* BLORP always just uses the first two binding table entries */
186 wm_prog_data
.binding_table
.render_target_start
= 0;
187 wm_prog_data
.base
.binding_table
.texture_start
= 1;
189 nir
= brw_preprocess_nir(compiler
, nir
);
190 nir_remove_dead_variables(nir
, nir_var_shader_in
);
191 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
193 /* Uniforms are required to be lowered before going into compile_fs. For
194 * BLORP, we'll assume that whoever builds the shader sets the location
195 * they want so we just need to lower them and figure out how many we have
198 nir
->num_uniforms
= 0;
199 nir_foreach_variable(var
, &nir
->uniforms
) {
200 var
->data
.driver_location
= var
->data
.location
;
201 unsigned end
= var
->data
.location
+ nir_uniform_type_size(var
->type
);
202 nir
->num_uniforms
= MAX2(nir
->num_uniforms
, end
);
204 nir_lower_io(nir
, nir_var_uniform
, nir_uniform_type_size
);
206 const unsigned *program
=
207 brw_compile_fs(compiler
, brw
, mem_ctx
, wm_key
, &wm_prog_data
, nir
,
208 NULL
, -1, -1, false, use_repclear
, program_size
, NULL
);
210 /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
211 prog_data
->dispatch_8
= wm_prog_data
.dispatch_8
;
212 prog_data
->dispatch_16
= wm_prog_data
.dispatch_16
;
213 prog_data
->first_curbe_grf_0
= wm_prog_data
.base
.dispatch_grf_start_reg
;
214 prog_data
->first_curbe_grf_2
= wm_prog_data
.dispatch_grf_start_reg_2
;
215 prog_data
->ksp_offset_2
= wm_prog_data
.prog_offset_2
;
216 prog_data
->persample_msaa_dispatch
= wm_prog_data
.persample_dispatch
;
217 prog_data
->flat_inputs
= wm_prog_data
.flat_inputs
;
218 prog_data
->num_varying_inputs
= wm_prog_data
.num_varying_inputs
;
219 prog_data
->inputs_read
= nir
->info
.inputs_read
;
221 assert(wm_prog_data
.base
.nr_params
== 0);
226 struct surface_state_info
{
228 unsigned ss_align
; /* Required alignment of RENDER_SURFACE_STATE in bytes */
230 unsigned aux_reloc_dw
;
235 static const struct surface_state_info surface_state_infos
[] = {
237 [7] = {8, 32, 1, 6, GEN7_MOCS_L3
, GEN7_MOCS_L3
},
238 [8] = {13, 64, 8, 10, BDW_MOCS_WB
, BDW_MOCS_PTE
},
239 [9] = {16, 64, 8, 10, SKL_MOCS_WB
, SKL_MOCS_PTE
},
243 brw_blorp_emit_surface_state(struct brw_context
*brw
,
244 const struct brw_blorp_surface_info
*surface
,
245 uint32_t read_domains
, uint32_t write_domain
,
246 bool is_render_target
)
248 const struct surface_state_info ss_info
= surface_state_infos
[brw
->gen
];
250 struct isl_surf surf
= surface
->surf
;
252 if (surf
.dim
== ISL_SURF_DIM_1D
&&
253 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
254 assert(surf
.logical_level0_px
.height
== 1);
255 surf
.dim
= ISL_SURF_DIM_2D
;
258 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
259 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
260 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
261 aux_usage
= ISL_AUX_USAGE_NONE
;
263 uint32_t surf_offset
;
264 uint32_t *dw
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
265 ss_info
.num_dwords
* 4, ss_info
.ss_align
,
268 const uint32_t mocs
= is_render_target
? ss_info
.rb_mocs
: ss_info
.tex_mocs
;
269 uint64_t aux_bo_offset
= surface
->aux_bo
? surface
->aux_bo
->offset64
: 0;
271 isl_surf_fill_state(&brw
->isl_dev
, dw
, .surf
= &surf
, .view
= &surface
->view
,
272 .address
= surface
->bo
->offset64
+ surface
->offset
,
273 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
274 .aux_address
= aux_bo_offset
+ surface
->aux_offset
,
275 .mocs
= mocs
, .clear_color
= surface
->clear_color
,
276 .x_offset_sa
= surface
->tile_x_sa
,
277 .y_offset_sa
= surface
->tile_y_sa
);
279 /* Emit relocation to surface contents */
280 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
281 surf_offset
+ ss_info
.reloc_dw
* 4,
283 dw
[ss_info
.reloc_dw
] - surface
->bo
->offset64
,
284 read_domains
, write_domain
);
286 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
287 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
288 * used to store other information. This should be ok, however, because
289 * surface buffer addresses are always 4K page alinged.
291 assert((surface
->aux_offset
& 0xfff) == 0);
292 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
293 surf_offset
+ ss_info
.aux_reloc_dw
* 4,
295 dw
[ss_info
.aux_reloc_dw
] & 0xfff,
296 read_domains
, write_domain
);
303 brw_blorp_exec(struct brw_context
*brw
, const struct brw_blorp_params
*params
)
305 struct gl_context
*ctx
= &brw
->ctx
;
306 const uint32_t estimated_max_batch_usage
= brw
->gen
>= 8 ? 1800 : 1500;
307 bool check_aperture_failed_once
= false;
309 /* Flush the sampler and render caches. We definitely need to flush the
310 * sampler cache so that we get updated contents from the render cache for
311 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
312 * docs to flush the cache between reinterpretations of the same surface
313 * data with different formats, which blorp does for stencil and depth
316 brw_emit_mi_flush(brw
);
318 brw_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
321 intel_batchbuffer_require_space(brw
, estimated_max_batch_usage
, RENDER_RING
);
322 intel_batchbuffer_save_state(brw
);
323 drm_intel_bo
*saved_bo
= brw
->batch
.bo
;
324 uint32_t saved_used
= USED_BATCH(brw
->batch
);
325 uint32_t saved_state_batch_offset
= brw
->batch
.state_batch_offset
;
329 gen6_blorp_exec(brw
, params
);
333 gen75_blorp_exec(brw
, params
);
335 gen7_blorp_exec(brw
, params
);
338 gen8_blorp_exec(brw
, params
);
341 gen9_blorp_exec(brw
, params
);
344 /* BLORP is not supported before Gen6. */
345 unreachable("not reached");
348 /* Make sure we didn't wrap the batch unintentionally, and make sure we
349 * reserved enough space that a wrap will never happen.
351 assert(brw
->batch
.bo
== saved_bo
);
352 assert((USED_BATCH(brw
->batch
) - saved_used
) * 4 +
353 (saved_state_batch_offset
- brw
->batch
.state_batch_offset
) <
354 estimated_max_batch_usage
);
355 /* Shut up compiler warnings on release build */
358 (void)saved_state_batch_offset
;
360 /* Check if the blorp op we just did would make our batch likely to fail to
361 * map all the BOs into the GPU at batch exec time later. If so, flush the
362 * batch and try again with nothing else in the batch.
364 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
365 if (!check_aperture_failed_once
) {
366 check_aperture_failed_once
= true;
367 intel_batchbuffer_reset_to_saved(brw
);
368 intel_batchbuffer_flush(brw
);
371 int ret
= intel_batchbuffer_flush(brw
);
372 WARN_ONCE(ret
== -ENOSPC
,
373 "i965: blorp emit exceeded available aperture space\n");
377 if (unlikely(brw
->always_flush_batch
))
378 intel_batchbuffer_flush(brw
);
380 /* We've smashed all state compared to what the normal 3D pipeline
381 * rendering tracks for GL.
383 brw
->ctx
.NewDriverState
|= BRW_NEW_BLORP
;
384 brw
->no_depth_or_stencil
= false;
387 /* Flush the sampler cache so any texturing from the destination is
390 brw_emit_mi_flush(brw
);
394 blorp_gen6_hiz_op(struct brw_context
*brw
, struct brw_blorp_surf
*surf
,
395 unsigned level
, unsigned layer
, enum gen6_hiz_op op
)
397 struct brw_blorp_params params
;
398 brw_blorp_params_init(¶ms
);
402 brw_blorp_surface_info_init(brw
, ¶ms
.depth
, surf
, level
, layer
,
403 surf
->surf
->format
, true);
405 /* Align the rectangle primitive to 8x4 pixels.
407 * During fast depth clears, the emitted rectangle primitive must be
408 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
409 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
411 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
412 * aligned to an 8x4 pixel block relative to the upper left corner
413 * of the depth buffer [...]
415 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
416 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
417 * Ivybridge simulator require the alignment.
419 * To be safe, let's just align the rect for all hiz operations and all
420 * hardware generations.
422 * However, for some miptree slices of a Z24 texture, emitting an 8x4
423 * aligned rectangle that covers the slice may clobber adjacent slices if
424 * we strictly adhered to the texture alignments specified in the PRM. The
425 * Ivybridge PRM, Section "Alignment Unit Size", states that
426 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
427 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
428 * prevents the clobbering.
430 params
.x1
= minify(params
.depth
.surf
.logical_level0_px
.width
,
431 params
.depth
.view
.base_level
);
432 params
.y1
= minify(params
.depth
.surf
.logical_level0_px
.height
,
433 params
.depth
.view
.base_level
);
434 params
.x1
= ALIGN(params
.x1
, 8);
435 params
.y1
= ALIGN(params
.y1
, 4);
437 if (params
.depth
.view
.base_level
== 0) {
438 /* TODO: What about MSAA? */
439 params
.depth
.surf
.logical_level0_px
.width
= params
.x1
;
440 params
.depth
.surf
.logical_level0_px
.height
= params
.y1
;
443 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
444 params
.dst
.surf
.logical_level0_px
= params
.depth
.surf
.logical_level0_px
;
446 switch (surf
->surf
->format
) {
447 case ISL_FORMAT_R16_UNORM
:
448 params
.depth_format
= BRW_DEPTHFORMAT_D16_UNORM
;
450 case ISL_FORMAT_R32_FLOAT
:
451 params
.depth_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
453 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
454 params
.depth_format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
457 unreachable("not reached");
460 brw_blorp_exec(brw
, ¶ms
);