src/mesa/drivers/dri/i965/blorp.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <errno.h>
  25 #include "intel_batchbuffer.h"
  26 #include "intel_fbo.h"
  27
  28 #include "blorp_priv.h"
  29 #include "brw_compiler.h"
  30 #include "brw_nir.h"
  31 #include "brw_state.h"
  32
  33 void
  34 blorp_init(struct blorp_context *blorp, void *driver_ctx,
  35            struct isl_device *isl_dev)
  36 {
  37    blorp->driver_ctx = driver_ctx;
  38    blorp->isl_dev = isl_dev;
  39 }
  40
  41 void
  42 blorp_finish(struct blorp_context *blorp)
  43 {
  44    blorp->driver_ctx = NULL;
  45 }
  46
  47 void
  48 blorp_batch_init(struct blorp_context *blorp,
  49                  struct blorp_batch *batch, void *driver_batch)
  50 {
  51    batch->blorp = blorp;
  52    batch->driver_batch = driver_batch;
  53 }
  54
  55 void
  56 blorp_batch_finish(struct blorp_batch *batch)
  57 {
  58    batch->blorp = NULL;
  59 }
  60
  61 void
  62 brw_blorp_surface_info_init(struct blorp_context *blorp,
  63                             struct brw_blorp_surface_info *info,
  64                             const struct brw_blorp_surf *surf,
  65                             unsigned int level, unsigned int layer,
  66                             enum isl_format format, bool is_render_target)
  67 {
  68    /* Layer is a physical layer, so if this is a 2D multisample array texture
  69     * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
  70     * be a multiple of num_samples.
  71     */
  72    unsigned layer_multiplier = 1;
  73    if (surf->surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
  74       assert(layer % surf->surf->samples == 0);
  75       layer_multiplier = surf->surf->samples;
  76    }
  77
  78    if (format == ISL_FORMAT_UNSUPPORTED)
  79       format = surf->surf->format;
  80
  81    if (format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
  82       /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
  83        * a render target, which would prevent us from blitting to 24-bit
  84        * depth.  The miptree consists of 32 bits per pixel, arranged as 24-bit
  85        * depth values interleaved with 8 "don't care" bits.  Since depth
  86        * values don't require any blending, it doesn't matter how we interpret
  87        * the bit pattern as long as we copy the right amount of data, so just
  88        * map it as 8-bit BGRA.
  89        */
  90       format = ISL_FORMAT_B8G8R8A8_UNORM;
  91    } else if (surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) {
  92       assert(surf->surf->format == ISL_FORMAT_R8_UINT);
  93       /* Prior to Broadwell, we can't render to R8_UINT */
  94       if (blorp->isl_dev->info->gen < 8)
  95          format = ISL_FORMAT_R8_UNORM;
  96    }
  97
  98    info->surf = *surf->surf;
  99    info->addr = surf->addr;
 100
 101    info->aux_usage = surf->aux_usage;
 102    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 103       info->aux_surf = *surf->aux_surf;
 104       info->aux_addr = surf->aux_addr;
 105    }
 106
 107    info->clear_color = surf->clear_color;
 108
 109    info->view = (struct isl_view) {
 110       .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
 111                                   ISL_SURF_USAGE_TEXTURE_BIT,
 112       .format = format,
 113       .base_level = level,
 114       .levels = 1,
 115       .channel_select = {
 116          ISL_CHANNEL_SELECT_RED,
 117          ISL_CHANNEL_SELECT_GREEN,
 118          ISL_CHANNEL_SELECT_BLUE,
 119          ISL_CHANNEL_SELECT_ALPHA,
 120       },
 121    };
 122
 123    if (!is_render_target &&
 124        (info->surf.dim == ISL_SURF_DIM_3D ||
 125         info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
 126       /* 3-D textures don't support base_array layer and neither do 2-D
 127        * multisampled textures on IVB so we need to pass it through the
 128        * sampler in those cases.  These are also two cases where we are
 129        * guaranteed that we won't be doing any funny surface hacks.
 130        */
 131       info->view.base_array_layer = 0;
 132       info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
 133                                   info->surf.logical_level0_px.array_len);
 134       info->z_offset = layer / layer_multiplier;
 135    } else {
 136       info->view.base_array_layer = layer / layer_multiplier;
 137       info->view.array_len = 1;
 138       info->z_offset = 0;
 139    }
 140 }
 141
 142
 143 void
 144 brw_blorp_params_init(struct brw_blorp_params *params)
 145 {
 146    memset(params, 0, sizeof(*params));
 147    params->hiz_op = GEN6_HIZ_OP_NONE;
 148    params->fast_clear_op = 0;
 149    params->num_draw_buffers = 1;
 150    params->num_layers = 1;
 151 }
 152
 153 void
 154 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
 155 {
 156    memset(wm_key, 0, sizeof(*wm_key));
 157    wm_key->nr_color_regions = 1;
 158    for (int i = 0; i < MAX_SAMPLERS; i++)
 159       wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
 160 }
 161
 162 static int
 163 nir_uniform_type_size(const struct glsl_type *type)
 164 {
 165    /* Only very basic types are allowed */
 166    assert(glsl_type_is_vector_or_scalar(type));
 167    assert(glsl_get_bit_size(type) == 32);
 168
 169    return glsl_get_vector_elements(type) * 4;
 170 }
 171
 172 const unsigned *
 173 brw_blorp_compile_nir_shader(struct blorp_context *blorp, struct nir_shader *nir,
 174                              const struct brw_wm_prog_key *wm_key,
 175                              bool use_repclear,
 176                              struct brw_blorp_prog_data *prog_data,
 177                              unsigned *program_size)
 178 {
 179    const struct brw_compiler *compiler = blorp->compiler;
 180
 181    void *mem_ctx = ralloc_context(NULL);
 182
 183    /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
 184     * enabled, may end up completely replacing the nir_shader.  Therefore, we
 185     * own it and might as well put it in our context for easy cleanup.
 186     */
 187    ralloc_steal(mem_ctx, nir);
 188    nir->options =
 189       compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
 190
 191    struct brw_wm_prog_data wm_prog_data;
 192    memset(&wm_prog_data, 0, sizeof(wm_prog_data));
 193
 194    wm_prog_data.base.nr_params = 0;
 195    wm_prog_data.base.param = NULL;
 196
 197    /* BLORP always just uses the first two binding table entries */
 198    wm_prog_data.binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX;
 199    wm_prog_data.base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
 200
 201    nir = brw_preprocess_nir(compiler, nir);
 202    nir_remove_dead_variables(nir, nir_var_shader_in);
 203    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 204
 205    /* Uniforms are required to be lowered before going into compile_fs.  For
 206     * BLORP, we'll assume that whoever builds the shader sets the location
 207     * they want so we just need to lower them and figure out how many we have
 208     * in total.
 209     */
 210    nir->num_uniforms = 0;
 211    nir_foreach_variable(var, &nir->uniforms) {
 212       var->data.driver_location = var->data.location;
 213       unsigned end = var->data.location + nir_uniform_type_size(var->type);
 214       nir->num_uniforms = MAX2(nir->num_uniforms, end);
 215    }
 216    nir_lower_io(nir, nir_var_uniform, nir_uniform_type_size);
 217
 218    const unsigned *program =
 219       brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx,
 220                      wm_key, &wm_prog_data, nir,
 221                      NULL, -1, -1, false, use_repclear, program_size, NULL);
 222
 223    /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
 224    prog_data->dispatch_8 = wm_prog_data.dispatch_8;
 225    prog_data->dispatch_16 = wm_prog_data.dispatch_16;
 226    prog_data->first_curbe_grf_0 = wm_prog_data.base.dispatch_grf_start_reg;
 227    prog_data->first_curbe_grf_2 = wm_prog_data.dispatch_grf_start_reg_2;
 228    prog_data->ksp_offset_2 = wm_prog_data.prog_offset_2;
 229    prog_data->persample_msaa_dispatch = wm_prog_data.persample_dispatch;
 230    prog_data->flat_inputs = wm_prog_data.flat_inputs;
 231    prog_data->num_varying_inputs = wm_prog_data.num_varying_inputs;
 232    prog_data->inputs_read = nir->info.inputs_read;
 233
 234    assert(wm_prog_data.base.nr_params == 0);
 235
 236    return program;
 237 }
 238
 239 void
 240 blorp_gen6_hiz_op(struct blorp_batch *batch,
 241                   struct brw_blorp_surf *surf, unsigned level, unsigned layer,
 242                   enum gen6_hiz_op op)
 243 {
 244    struct brw_blorp_params params;
 245    brw_blorp_params_init(&params);
 246
 247    params.hiz_op = op;
 248
 249    brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level, layer,
 250                                surf->surf->format, true);
 251
 252    /* Align the rectangle primitive to 8x4 pixels.
 253     *
 254     * During fast depth clears, the emitted rectangle primitive  must be
 255     * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 256     * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
 257     * PRM):
 258     *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 259     *     aligned to an 8x4 pixel block relative to the upper left corner
 260     *     of the depth buffer [...]
 261     *
 262     * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 263     * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 264     * Ivybridge simulator require the alignment.
 265     *
 266     * To be safe, let's just align the rect for all hiz operations and all
 267     * hardware generations.
 268     *
 269     * However, for some miptree slices of a Z24 texture, emitting an 8x4
 270     * aligned rectangle that covers the slice may clobber adjacent slices if
 271     * we strictly adhered to the texture alignments specified in the PRM.  The
 272     * Ivybridge PRM, Section "Alignment Unit Size", states that
 273     * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
 274     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 275     * prevents the clobbering.
 276     */
 277    params.x1 = minify(params.depth.surf.logical_level0_px.width,
 278                       params.depth.view.base_level);
 279    params.y1 = minify(params.depth.surf.logical_level0_px.height,
 280                       params.depth.view.base_level);
 281    params.x1 = ALIGN(params.x1, 8);
 282    params.y1 = ALIGN(params.y1, 4);
 283
 284    if (params.depth.view.base_level == 0) {
 285       /* TODO: What about MSAA? */
 286       params.depth.surf.logical_level0_px.width = params.x1;
 287       params.depth.surf.logical_level0_px.height = params.y1;
 288    }
 289
 290    params.dst.surf.samples = params.depth.surf.samples;
 291    params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
 292
 293    switch (surf->surf->format) {
 294    case ISL_FORMAT_R16_UNORM:
 295       params.depth_format = BRW_DEPTHFORMAT_D16_UNORM;
 296       break;
 297    case ISL_FORMAT_R32_FLOAT:
 298       params.depth_format = BRW_DEPTHFORMAT_D32_FLOAT;
 299       break;
 300    case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
 301       params.depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 302       break;
 303    default:
 304       unreachable("not reached");
 305    }
 306
 307    batch->blorp->exec(batch, &params);
 308 }